1[ 2 { 3 "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3", 6 "EventCode": "0xc3", 7 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 8 "PDIR_COUNTER": "na", 9 "PEBScounters": "0,1,2,3", 10 "SampleAfterValue": "20003", 11 "UMask": "0x2" 12 }, 13 { 14 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3", 17 "EventCode": "0x13", 18 "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", 19 "PEBS": "1", 20 "PEBScounters": "0,1,2,3", 21 "SampleAfterValue": "200003", 22 "UMask": "0x2" 23 }, 24 { 25 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 26 "CollectPEBSRecord": "2", 27 "Counter": "0,1,2,3", 28 "EventCode": "0x13", 29 "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", 30 "PEBS": "1", 31 "PEBScounters": "0,1,2,3", 32 "SampleAfterValue": "200003", 33 "UMask": "0x4" 34 }, 35 { 36 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 37 "Counter": "0,1,2,3", 38 "EventCode": "0XB7", 39 "EventName": "OCR.ALL_CODE_RD.L3_MISS", 40 "MSRIndex": "0x1a6,0x1a7", 41 "MSRValue": "0x2184000044", 42 "Offcore": "1", 43 "SampleAfterValue": "100003", 44 "UMask": "0x1" 45 }, 46 { 47 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 "Counter": "0,1,2,3", 49 "EventCode": "0XB7", 50 "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", 51 "MSRIndex": "0x1a6,0x1a7", 52 "MSRValue": "0x2184000044", 53 "Offcore": "1", 54 "SampleAfterValue": "100003", 55 "UMask": "0x1" 56 }, 57 { 58 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 59 "Counter": "0,1,2,3", 60 "EventCode": "0XB7", 61 "EventName": "OCR.COREWB_M.L3_MISS", 62 "MSRIndex": "0x1a6,0x1a7", 63 "MSRValue": "0x3002184000000", 64 "Offcore": "1", 65 "SampleAfterValue": "100003", 66 "UMask": "0x1" 67 }, 68 { 69 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 70 "Counter": "0,1,2,3", 71 "EventCode": "0XB7", 72 "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", 73 "MSRIndex": "0x1a6,0x1a7", 74 "MSRValue": "0x3002184000000", 75 "Offcore": "1", 76 "SampleAfterValue": "100003", 77 "UMask": "0x1" 78 }, 79 { 80 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 81 "Counter": "0,1,2,3", 82 "EventCode": "0XB7", 83 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 84 "MSRIndex": "0x1a6,0x1a7", 85 "MSRValue": "0x2184000004", 86 "Offcore": "1", 87 "SampleAfterValue": "100003", 88 "UMask": "0x1" 89 }, 90 { 91 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 92 "Counter": "0,1,2,3", 93 "EventCode": "0XB7", 94 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", 95 "MSRIndex": "0x1a6,0x1a7", 96 "MSRValue": "0x2184000004", 97 "Offcore": "1", 98 "SampleAfterValue": "100003", 99 "UMask": "0x1" 100 }, 101 { 102 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 103 "Counter": "0,1,2,3", 104 "EventCode": "0XB7", 105 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 106 "MSRIndex": "0x1a6,0x1a7", 107 "MSRValue": "0x2184000001", 108 "Offcore": "1", 109 "SampleAfterValue": "100003", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 114 "Counter": "0,1,2,3", 115 "EventCode": "0XB7", 116 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 117 "MSRIndex": "0x1a6,0x1a7", 118 "MSRValue": "0x2184000001", 119 "Offcore": "1", 120 "SampleAfterValue": "100003", 121 "UMask": "0x1" 122 }, 123 { 124 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 125 "Counter": "0,1,2,3", 126 "EventCode": "0XB7", 127 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 128 "MSRIndex": "0x1a6,0x1a7", 129 "MSRValue": "0x2184000001", 130 "Offcore": "1", 131 "SampleAfterValue": "100003", 132 "UMask": "0x1" 133 }, 134 { 135 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 136 "Counter": "0,1,2,3", 137 "EventCode": "0XB7", 138 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 139 "MSRIndex": "0x1a6,0x1a7", 140 "MSRValue": "0x2184000001", 141 "Offcore": "1", 142 "SampleAfterValue": "100003", 143 "UMask": "0x1" 144 }, 145 { 146 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 147 "Counter": "0,1,2,3", 148 "EventCode": "0XB7", 149 "EventName": "OCR.DEMAND_RFO.L3_MISS", 150 "MSRIndex": "0x1a6,0x1a7", 151 "MSRValue": "0x2184000002", 152 "Offcore": "1", 153 "SampleAfterValue": "100003", 154 "UMask": "0x1" 155 }, 156 { 157 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 158 "Counter": "0,1,2,3", 159 "EventCode": "0XB7", 160 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 161 "MSRIndex": "0x1a6,0x1a7", 162 "MSRValue": "0x2184000002", 163 "Offcore": "1", 164 "SampleAfterValue": "100003", 165 "UMask": "0x1" 166 }, 167 { 168 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", 169 "Counter": "0,1,2,3", 170 "EventCode": "0XB7", 171 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", 172 "MSRIndex": "0x1a6,0x1a7", 173 "MSRValue": "0x802184000000", 174 "Offcore": "1", 175 "SampleAfterValue": "100003", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", 180 "Counter": "0,1,2,3", 181 "EventCode": "0XB7", 182 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", 183 "MSRIndex": "0x1a6,0x1a7", 184 "MSRValue": "0x802184000000", 185 "Offcore": "1", 186 "SampleAfterValue": "100003", 187 "UMask": "0x1" 188 }, 189 { 190 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", 191 "Counter": "0,1,2,3", 192 "EventCode": "0XB7", 193 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", 194 "MSRIndex": "0x1a6,0x1a7", 195 "MSRValue": "0x2184000040", 196 "Offcore": "1", 197 "SampleAfterValue": "100003", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", 202 "Counter": "0,1,2,3", 203 "EventCode": "0XB7", 204 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", 205 "MSRIndex": "0x1a6,0x1a7", 206 "MSRValue": "0x2184000040", 207 "Offcore": "1", 208 "SampleAfterValue": "100003", 209 "UMask": "0x1" 210 }, 211 { 212 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", 213 "Counter": "0,1,2,3", 214 "EventCode": "0XB7", 215 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", 216 "MSRIndex": "0x1a6,0x1a7", 217 "MSRValue": "0x2184000010", 218 "Offcore": "1", 219 "SampleAfterValue": "100003", 220 "UMask": "0x1" 221 }, 222 { 223 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", 224 "Counter": "0,1,2,3", 225 "EventCode": "0XB7", 226 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", 227 "MSRIndex": "0x1a6,0x1a7", 228 "MSRValue": "0x2184000010", 229 "Offcore": "1", 230 "SampleAfterValue": "100003", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", 235 "Counter": "0,1,2,3", 236 "EventCode": "0XB7", 237 "EventName": "OCR.HWPF_L2_RFO.L3_MISS", 238 "MSRIndex": "0x1a6,0x1a7", 239 "MSRValue": "0x2184000020", 240 "Offcore": "1", 241 "SampleAfterValue": "100003", 242 "UMask": "0x1" 243 }, 244 { 245 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", 246 "Counter": "0,1,2,3", 247 "EventCode": "0XB7", 248 "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", 249 "MSRIndex": "0x1a6,0x1a7", 250 "MSRValue": "0x2184000020", 251 "Offcore": "1", 252 "SampleAfterValue": "100003", 253 "UMask": "0x1" 254 }, 255 { 256 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", 257 "Counter": "0,1,2,3", 258 "EventCode": "0XB7", 259 "EventName": "OCR.L1WB_M.L3_MISS", 260 "MSRIndex": "0x1a6,0x1a7", 261 "MSRValue": "0x1002184000000", 262 "Offcore": "1", 263 "SampleAfterValue": "100003", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", 268 "Counter": "0,1,2,3", 269 "EventCode": "0XB7", 270 "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x1002184000000", 273 "Offcore": "1", 274 "SampleAfterValue": "100003", 275 "UMask": "0x1" 276 }, 277 { 278 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", 279 "Counter": "0,1,2,3", 280 "EventCode": "0XB7", 281 "EventName": "OCR.L2WB_M.L3_MISS", 282 "MSRIndex": "0x1a6,0x1a7", 283 "MSRValue": "0x2002184000000", 284 "Offcore": "1", 285 "SampleAfterValue": "100003", 286 "UMask": "0x1" 287 }, 288 { 289 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", 290 "Counter": "0,1,2,3", 291 "EventCode": "0XB7", 292 "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", 293 "MSRIndex": "0x1a6,0x1a7", 294 "MSRValue": "0x2002184000000", 295 "Offcore": "1", 296 "SampleAfterValue": "100003", 297 "UMask": "0x1" 298 }, 299 { 300 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", 301 "Counter": "0,1,2,3", 302 "EventCode": "0XB7", 303 "EventName": "OCR.OTHER.L3_MISS", 304 "MSRIndex": "0x1a6,0x1a7", 305 "MSRValue": "0x2184008000", 306 "Offcore": "1", 307 "SampleAfterValue": "100003", 308 "UMask": "0x1" 309 }, 310 { 311 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", 312 "Counter": "0,1,2,3", 313 "EventCode": "0XB7", 314 "EventName": "OCR.OTHER.L3_MISS_LOCAL", 315 "MSRIndex": "0x1a6,0x1a7", 316 "MSRValue": "0x2184008000", 317 "Offcore": "1", 318 "SampleAfterValue": "100003", 319 "UMask": "0x1" 320 }, 321 { 322 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", 323 "Counter": "0,1,2,3", 324 "EventCode": "0XB7", 325 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", 326 "MSRIndex": "0x1a6,0x1a7", 327 "MSRValue": "0x402184000000", 328 "Offcore": "1", 329 "SampleAfterValue": "100003", 330 "UMask": "0x1" 331 }, 332 { 333 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", 334 "Counter": "0,1,2,3", 335 "EventCode": "0XB7", 336 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", 337 "MSRIndex": "0x1a6,0x1a7", 338 "MSRValue": "0x402184000000", 339 "Offcore": "1", 340 "SampleAfterValue": "100003", 341 "UMask": "0x1" 342 }, 343 { 344 "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.", 345 "Counter": "0,1,2,3", 346 "EventCode": "0XB7", 347 "EventName": "OCR.PREFETCHES.L3_MISS", 348 "MSRIndex": "0x1a6,0x1a7", 349 "MSRValue": "0x2184000470", 350 "Offcore": "1", 351 "SampleAfterValue": "100003", 352 "UMask": "0x1" 353 }, 354 { 355 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", 356 "Counter": "0,1,2,3", 357 "EventCode": "0XB7", 358 "EventName": "OCR.READS_TO_CORE.L3_MISS", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x2184000477", 361 "Offcore": "1", 362 "SampleAfterValue": "100003", 363 "UMask": "0x1" 364 }, 365 { 366 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", 367 "Counter": "0,1,2,3", 368 "EventCode": "0XB7", 369 "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 370 "MSRIndex": "0x1a6,0x1a7", 371 "MSRValue": "0x2184000477", 372 "Offcore": "1", 373 "SampleAfterValue": "100003", 374 "UMask": "0x1" 375 }, 376 { 377 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", 378 "Counter": "0,1,2,3", 379 "EventCode": "0XB7", 380 "EventName": "OCR.STREAMING_WR.L3_MISS", 381 "MSRIndex": "0x1a6,0x1a7", 382 "MSRValue": "0x2184000800", 383 "Offcore": "1", 384 "SampleAfterValue": "100003", 385 "UMask": "0x1" 386 }, 387 { 388 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", 389 "Counter": "0,1,2,3", 390 "EventCode": "0XB7", 391 "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 392 "MSRIndex": "0x1a6,0x1a7", 393 "MSRValue": "0x2184000800", 394 "Offcore": "1", 395 "SampleAfterValue": "100003", 396 "UMask": "0x1" 397 }, 398 { 399 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", 400 "Counter": "0,1,2,3", 401 "EventCode": "0XB7", 402 "EventName": "OCR.UC_RD.L3_MISS", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x102184000000", 405 "Offcore": "1", 406 "SampleAfterValue": "100003", 407 "UMask": "0x1" 408 }, 409 { 410 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", 411 "Counter": "0,1,2,3", 412 "EventCode": "0XB7", 413 "EventName": "OCR.UC_RD.L3_MISS_LOCAL", 414 "MSRIndex": "0x1a6,0x1a7", 415 "MSRValue": "0x102184000000", 416 "Offcore": "1", 417 "SampleAfterValue": "100003", 418 "UMask": "0x1" 419 }, 420 { 421 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", 422 "Counter": "0,1,2,3", 423 "EventCode": "0XB7", 424 "EventName": "OCR.UC_WR.L3_MISS", 425 "MSRIndex": "0x1a6,0x1a7", 426 "MSRValue": "0x202184000000", 427 "Offcore": "1", 428 "SampleAfterValue": "100003", 429 "UMask": "0x1" 430 }, 431 { 432 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", 433 "Counter": "0,1,2,3", 434 "EventCode": "0XB7", 435 "EventName": "OCR.UC_WR.L3_MISS_LOCAL", 436 "MSRIndex": "0x1a6,0x1a7", 437 "MSRValue": "0x202184000000", 438 "Offcore": "1", 439 "SampleAfterValue": "100003", 440 "UMask": "0x1" 441 } 442]