xref: /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/memory.json (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1[
2    {
3        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
4        "EventCode": "0XB7",
5        "MSRValue": "0x000000003F04000001",
6        "Counter": "0,1,2,3",
7        "UMask": "0x1",
8        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
9        "MSRIndex": "0x1a6,0x1a7",
10        "SampleAfterValue": "100003",
11        "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
12        "Offcore": "1"
13    },
14    {
15        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
16        "EventCode": "0XB7",
17        "MSRValue": "0x000000003F04000002",
18        "Counter": "0,1,2,3",
19        "UMask": "0x1",
20        "EventName": "OCR.DEMAND_RFO.L3_MISS",
21        "MSRIndex": "0x1a6,0x1a7",
22        "SampleAfterValue": "100003",
23        "BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
24        "Offcore": "1"
25    }
26]