1[ 2 { 3 "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3", 6 "EventCode": "0x31", 7 "EventName": "CORE_REJECT_L2Q.ANY", 8 "PDIR_COUNTER": "na", 9 "PEBScounters": "0,1,2,3", 10 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.", 11 "SampleAfterValue": "200003" 12 }, 13 { 14 "BriefDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3", 17 "EventCode": "0x51", 18 "EventName": "DL1.DIRTY_EVICTION", 19 "PDIR_COUNTER": "na", 20 "PEBScounters": "0,1,2,3", 21 "PublicDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 22 "SampleAfterValue": "200003", 23 "UMask": "0x1" 24 }, 25 { 26 "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.", 27 "CollectPEBSRecord": "2", 28 "Counter": "0,1,2,3", 29 "EventCode": "0x30", 30 "EventName": "L2_REJECT_XQ.ANY", 31 "PDIR_COUNTER": "na", 32 "PEBScounters": "0,1,2,3", 33 "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", 34 "SampleAfterValue": "200003" 35 }, 36 { 37 "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 38 "CollectPEBSRecord": "2", 39 "Counter": "0,1,2,3", 40 "EventCode": "0x24", 41 "EventName": "L2_REQUEST.ALL", 42 "PDIR_COUNTER": "na", 43 "PEBScounters": "0,1,2,3", 44 "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.", 45 "SampleAfterValue": "200003" 46 }, 47 { 48 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", 49 "CollectPEBSRecord": "2", 50 "Counter": "0,1,2,3", 51 "EventCode": "0x24", 52 "EventName": "L2_REQUEST.HIT", 53 "PDIR_COUNTER": "na", 54 "PEBScounters": "0,1,2,3", 55 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.", 56 "SampleAfterValue": "200003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.", 61 "CollectPEBSRecord": "2", 62 "Counter": "0,1,2,3", 63 "EventCode": "0x24", 64 "EventName": "L2_REQUEST.MISS", 65 "PDIR_COUNTER": "na", 66 "PEBScounters": "0,1,2,3", 67 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.", 68 "SampleAfterValue": "200003", 69 "UMask": "0x1" 70 }, 71 { 72 "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.", 73 "CollectPEBSRecord": "2", 74 "Counter": "0,1,2,3", 75 "EventCode": "0x24", 76 "EventName": "L2_REQUEST.REJECTS", 77 "PDIR_COUNTER": "na", 78 "PEBScounters": "0,1,2,3", 79 "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.", 80 "SampleAfterValue": "200003", 81 "UMask": "0x4" 82 }, 83 { 84 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 85 "CollectPEBSRecord": "2", 86 "Counter": "0,1,2,3", 87 "EventCode": "0x2e", 88 "EventName": "LONGEST_LAT_CACHE.MISS", 89 "PDIR_COUNTER": "na", 90 "PEBScounters": "0,1,2,3", 91 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 92 "SampleAfterValue": "200003", 93 "UMask": "0x41" 94 }, 95 { 96 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 97 "CollectPEBSRecord": "2", 98 "Counter": "0,1,2,3", 99 "EventCode": "0x2e", 100 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 101 "PDIR_COUNTER": "na", 102 "PEBScounters": "0,1,2,3", 103 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 104 "SampleAfterValue": "200003", 105 "UMask": "0x4f" 106 }, 107 { 108 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 109 "CollectPEBSRecord": "2", 110 "Counter": "0,1,2,3", 111 "EventCode": "0x34", 112 "EventName": "MEM_BOUND_STALLS.IFETCH", 113 "PEBScounters": "0,1,2,3", 114 "SampleAfterValue": "200003", 115 "UMask": "0x38" 116 }, 117 { 118 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 119 "CollectPEBSRecord": "2", 120 "Counter": "0,1,2,3", 121 "EventCode": "0x34", 122 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", 123 "PDIR_COUNTER": "na", 124 "PEBScounters": "0,1,2,3", 125 "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).", 126 "SampleAfterValue": "200003", 127 "UMask": "0x20" 128 }, 129 { 130 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 131 "CollectPEBSRecord": "2", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x34", 134 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", 135 "PDIR_COUNTER": "na", 136 "PEBScounters": "0,1,2,3", 137 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", 138 "SampleAfterValue": "200003", 139 "UMask": "0x8" 140 }, 141 { 142 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", 143 "CollectPEBSRecord": "2", 144 "Counter": "0,1,2,3", 145 "EventCode": "0x34", 146 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", 147 "PDIR_COUNTER": "na", 148 "PEBScounters": "0,1,2,3", 149 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", 150 "SampleAfterValue": "200003", 151 "UMask": "0x10" 152 }, 153 { 154 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 155 "CollectPEBSRecord": "2", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x34", 158 "EventName": "MEM_BOUND_STALLS.LOAD", 159 "PEBScounters": "0,1,2,3", 160 "SampleAfterValue": "200003", 161 "UMask": "0x7" 162 }, 163 { 164 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 165 "CollectPEBSRecord": "2", 166 "Counter": "0,1,2,3", 167 "EventCode": "0x34", 168 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", 169 "PDIR_COUNTER": "na", 170 "PEBScounters": "0,1,2,3", 171 "SampleAfterValue": "200003", 172 "UMask": "0x4" 173 }, 174 { 175 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 176 "CollectPEBSRecord": "2", 177 "Counter": "0,1,2,3", 178 "EventCode": "0x34", 179 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", 180 "PDIR_COUNTER": "na", 181 "PEBScounters": "0,1,2,3", 182 "SampleAfterValue": "200003", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", 187 "CollectPEBSRecord": "2", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x34", 190 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", 191 "PDIR_COUNTER": "na", 192 "PEBScounters": "0,1,2,3", 193 "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", 194 "SampleAfterValue": "200003", 195 "UMask": "0x2" 196 }, 197 { 198 "BriefDescription": "Counts the number of cycles a core is stalled due to a store buffer being full.", 199 "CollectPEBSRecord": "2", 200 "Counter": "0,1,2,3", 201 "EventCode": "0x34", 202 "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", 203 "PDIR_COUNTER": "na", 204 "PEBScounters": "0,1,2,3", 205 "SampleAfterValue": "200003", 206 "UMask": "0x40" 207 }, 208 { 209 "BriefDescription": "Counts the number of load ops retired that hit in DRAM.", 210 "CollectPEBSRecord": "2", 211 "Counter": "0,1,2,3", 212 "Data_LA": "1", 213 "EventCode": "0xd1", 214 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 215 "PEBS": "1", 216 "PEBScounters": "0,1,2,3", 217 "SampleAfterValue": "200003", 218 "UMask": "0x80" 219 }, 220 { 221 "BriefDescription": "Counts the number of retired loads that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core.", 222 "CollectPEBSRecord": "2", 223 "Counter": "0,1,2,3", 224 "Data_LA": "1", 225 "EventCode": "0xd1", 226 "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", 227 "PEBS": "1", 228 "PEBScounters": "0,1,2,3", 229 "SampleAfterValue": "200003", 230 "UMask": "0x20" 231 }, 232 { 233 "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.", 234 "CollectPEBSRecord": "2", 235 "Counter": "0,1,2,3", 236 "Data_LA": "1", 237 "EventCode": "0xd1", 238 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 239 "PEBS": "1", 240 "PEBScounters": "0,1,2,3", 241 "SampleAfterValue": "200003", 242 "UMask": "0x1" 243 }, 244 { 245 "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.", 246 "CollectPEBSRecord": "2", 247 "Counter": "0,1,2,3", 248 "Data_LA": "1", 249 "EventCode": "0xd1", 250 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 251 "PEBS": "1", 252 "PEBScounters": "0,1,2,3", 253 "SampleAfterValue": "200003", 254 "UMask": "0x8" 255 }, 256 { 257 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", 258 "CollectPEBSRecord": "2", 259 "Counter": "0,1,2,3", 260 "Data_LA": "1", 261 "EventCode": "0xd1", 262 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 263 "PEBS": "1", 264 "PEBScounters": "0,1,2,3", 265 "SampleAfterValue": "200003", 266 "UMask": "0x2" 267 }, 268 { 269 "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.", 270 "CollectPEBSRecord": "2", 271 "Counter": "0,1,2,3", 272 "Data_LA": "1", 273 "EventCode": "0xd1", 274 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 275 "PEBS": "1", 276 "PEBScounters": "0,1,2,3", 277 "SampleAfterValue": "200003", 278 "UMask": "0x10" 279 }, 280 { 281 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 282 "CollectPEBSRecord": "2", 283 "Counter": "0,1,2,3", 284 "EventCode": "0xd1", 285 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 286 "PEBS": "1", 287 "PEBScounters": "0,1,2,3", 288 "SampleAfterValue": "200003", 289 "UMask": "0x4" 290 }, 291 { 292 "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", 293 "CollectPEBSRecord": "2", 294 "Counter": "0,1,2,3", 295 "Data_LA": "1", 296 "EventCode": "0xd0", 297 "EventName": "MEM_UOPS_RETIRED.ALL", 298 "PEBS": "1", 299 "PEBScounters": "0,1,2,3", 300 "SampleAfterValue": "200003", 301 "UMask": "0x83" 302 }, 303 { 304 "BriefDescription": "Counts the number of load uops retired.", 305 "CollectPEBSRecord": "2", 306 "Counter": "0,1,2,3", 307 "Data_LA": "1", 308 "EventCode": "0xd0", 309 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 310 "PEBS": "1", 311 "PEBScounters": "0,1,2,3", 312 "PublicDescription": "Counts the total number of load uops retired.", 313 "SampleAfterValue": "200003", 314 "UMask": "0x81" 315 }, 316 { 317 "BriefDescription": "Counts the number of store uops retired.", 318 "CollectPEBSRecord": "2", 319 "Counter": "0,1,2,3", 320 "Data_LA": "1", 321 "EventCode": "0xd0", 322 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 323 "PEBS": "1", 324 "PEBScounters": "0,1,2,3", 325 "PublicDescription": "Counts the total number of store uops retired.", 326 "SampleAfterValue": "200003", 327 "UMask": "0x82" 328 }, 329 { 330 "BriefDescription": "Counts the number of load uops retired that performed one or more locks.", 331 "CollectPEBSRecord": "2", 332 "Counter": "0,1,2,3", 333 "Data_LA": "1", 334 "EventCode": "0xd0", 335 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 336 "PEBS": "1", 337 "PEBScounters": "0,1,2,3", 338 "SampleAfterValue": "200003", 339 "UMask": "0x21" 340 }, 341 { 342 "BriefDescription": "Counts the number of memory uops retired that were splits.", 343 "CollectPEBSRecord": "2", 344 "Counter": "0,1,2,3", 345 "Data_LA": "1", 346 "EventCode": "0xd0", 347 "EventName": "MEM_UOPS_RETIRED.SPLIT", 348 "PEBS": "1", 349 "PEBScounters": "0,1,2,3", 350 "SampleAfterValue": "200003", 351 "UMask": "0x43" 352 }, 353 { 354 "BriefDescription": "Counts the number of retired split loads uops.", 355 "CollectPEBSRecord": "2", 356 "Counter": "0,1,2,3", 357 "Data_LA": "1", 358 "EventCode": "0xd0", 359 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 360 "PEBS": "1", 361 "PEBScounters": "0,1,2,3", 362 "SampleAfterValue": "200003", 363 "UMask": "0x41" 364 }, 365 { 366 "BriefDescription": "Counts the number of retired split store uops.", 367 "CollectPEBSRecord": "2", 368 "Counter": "0,1,2,3", 369 "Data_LA": "1", 370 "EventCode": "0xd0", 371 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 372 "PEBS": "1", 373 "PEBScounters": "0,1,2,3", 374 "SampleAfterValue": "200003", 375 "UMask": "0x42" 376 }, 377 { 378 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 379 "Counter": "0,1,2,3", 380 "EventCode": "0XB7", 381 "EventName": "OCR.ALL_CODE_RD.L3_HIT", 382 "MSRIndex": "0x1a6,0x1a7", 383 "MSRValue": "0x1F803C0044", 384 "Offcore": "1", 385 "SampleAfterValue": "100003", 386 "UMask": "0x1" 387 }, 388 { 389 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 390 "Counter": "0,1,2,3", 391 "EventCode": "0XB7", 392 "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", 393 "MSRIndex": "0x1a6,0x1a7", 394 "MSRValue": "0x10003C0044", 395 "Offcore": "1", 396 "SampleAfterValue": "100003", 397 "UMask": "0x1" 398 }, 399 { 400 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 401 "Counter": "0,1,2,3", 402 "EventCode": "0XB7", 403 "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", 404 "MSRIndex": "0x1a6,0x1a7", 405 "MSRValue": "0x4003C0044", 406 "Offcore": "1", 407 "SampleAfterValue": "100003", 408 "UMask": "0x1" 409 }, 410 { 411 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 412 "Counter": "0,1,2,3", 413 "EventCode": "0XB7", 414 "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 415 "MSRIndex": "0x1a6,0x1a7", 416 "MSRValue": "0x8003C0044", 417 "Offcore": "1", 418 "SampleAfterValue": "100003", 419 "UMask": "0x1" 420 }, 421 { 422 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 423 "Counter": "0,1,2,3", 424 "EventCode": "0XB7", 425 "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", 426 "MSRIndex": "0x1a6,0x1a7", 427 "MSRValue": "0x2003C0044", 428 "Offcore": "1", 429 "SampleAfterValue": "100003", 430 "UMask": "0x1" 431 }, 432 { 433 "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 434 "Counter": "0,1,2,3", 435 "EventCode": "0XB7", 436 "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", 437 "MSRIndex": "0x1a6,0x1a7", 438 "MSRValue": "0x1003C0044", 439 "Offcore": "1", 440 "SampleAfterValue": "100003", 441 "UMask": "0x1" 442 }, 443 { 444 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", 445 "Counter": "0,1,2,3", 446 "EventCode": "0XB7", 447 "EventName": "OCR.COREWB_M.L3_HIT", 448 "MSRIndex": "0x1a6,0x1a7", 449 "MSRValue": "0x3001F803C0000", 450 "Offcore": "1", 451 "SampleAfterValue": "100003", 452 "UMask": "0x1" 453 }, 454 { 455 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", 456 "Counter": "0,1,2,3", 457 "EventCode": "0XB7", 458 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", 459 "MSRIndex": "0x1a6,0x1a7", 460 "MSRValue": "0x1F803C0004", 461 "Offcore": "1", 462 "SampleAfterValue": "100003", 463 "UMask": "0x1" 464 }, 465 { 466 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 467 "Counter": "0,1,2,3", 468 "EventCode": "0XB7", 469 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", 470 "MSRIndex": "0x1a6,0x1a7", 471 "MSRValue": "0x10003C0004", 472 "Offcore": "1", 473 "SampleAfterValue": "100003", 474 "UMask": "0x1" 475 }, 476 { 477 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 478 "Counter": "0,1,2,3", 479 "EventCode": "0XB7", 480 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", 481 "MSRIndex": "0x1a6,0x1a7", 482 "MSRValue": "0x4003C0004", 483 "Offcore": "1", 484 "SampleAfterValue": "100003", 485 "UMask": "0x1" 486 }, 487 { 488 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 489 "Counter": "0,1,2,3", 490 "EventCode": "0XB7", 491 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 492 "MSRIndex": "0x1a6,0x1a7", 493 "MSRValue": "0x8003C0004", 494 "Offcore": "1", 495 "SampleAfterValue": "100003", 496 "UMask": "0x1" 497 }, 498 { 499 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 500 "Counter": "0,1,2,3", 501 "EventCode": "0XB7", 502 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 503 "MSRIndex": "0x1a6,0x1a7", 504 "MSRValue": "0x2003C0004", 505 "Offcore": "1", 506 "SampleAfterValue": "100003", 507 "UMask": "0x1" 508 }, 509 { 510 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 511 "Counter": "0,1,2,3", 512 "EventCode": "0XB7", 513 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", 514 "MSRIndex": "0x1a6,0x1a7", 515 "MSRValue": "0x1003C0004", 516 "Offcore": "1", 517 "SampleAfterValue": "100003", 518 "UMask": "0x1" 519 }, 520 { 521 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", 522 "Counter": "0,1,2,3", 523 "EventCode": "0XB7", 524 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", 525 "MSRIndex": "0x1a6,0x1a7", 526 "MSRValue": "0x1F803C0001", 527 "Offcore": "1", 528 "SampleAfterValue": "100003", 529 "UMask": "0x1" 530 }, 531 { 532 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 533 "Counter": "0,1,2,3", 534 "EventCode": "0XB7", 535 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", 536 "MSRIndex": "0x1a6,0x1a7", 537 "MSRValue": "0x10003C0001", 538 "Offcore": "1", 539 "SampleAfterValue": "100003", 540 "UMask": "0x1" 541 }, 542 { 543 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 544 "Counter": "0,1,2,3", 545 "EventCode": "0XB7", 546 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", 547 "MSRIndex": "0x1a6,0x1a7", 548 "MSRValue": "0x4003C0001", 549 "Offcore": "1", 550 "SampleAfterValue": "100003", 551 "UMask": "0x1" 552 }, 553 { 554 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 555 "Counter": "0,1,2,3", 556 "EventCode": "0XB7", 557 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 558 "MSRIndex": "0x1a6,0x1a7", 559 "MSRValue": "0x8003C0001", 560 "Offcore": "1", 561 "SampleAfterValue": "100003", 562 "UMask": "0x1" 563 }, 564 { 565 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 566 "Counter": "0,1,2,3", 567 "EventCode": "0XB7", 568 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", 569 "MSRIndex": "0x1a6,0x1a7", 570 "MSRValue": "0x2003C0001", 571 "Offcore": "1", 572 "SampleAfterValue": "100003", 573 "UMask": "0x1" 574 }, 575 { 576 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 577 "Counter": "0,1,2,3", 578 "EventCode": "0XB7", 579 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", 580 "MSRIndex": "0x1a6,0x1a7", 581 "MSRValue": "0x1003C0001", 582 "Offcore": "1", 583 "SampleAfterValue": "100003", 584 "UMask": "0x1" 585 }, 586 { 587 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", 588 "Counter": "0,1,2,3", 589 "EventCode": "0XB7", 590 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", 591 "MSRIndex": "0x1a6,0x1a7", 592 "MSRValue": "0x1F803C0001", 593 "Offcore": "1", 594 "SampleAfterValue": "100003", 595 "UMask": "0x1" 596 }, 597 { 598 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", 599 "Counter": "0,1,2,3", 600 "EventCode": "0XB7", 601 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 602 "MSRIndex": "0x1a6,0x1a7", 603 "MSRValue": "0x10003C0001", 604 "Offcore": "1", 605 "SampleAfterValue": "100003", 606 "UMask": "0x1" 607 }, 608 { 609 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", 610 "Counter": "0,1,2,3", 611 "EventCode": "0XB7", 612 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 613 "MSRIndex": "0x1a6,0x1a7", 614 "MSRValue": "0x4003C0001", 615 "Offcore": "1", 616 "SampleAfterValue": "100003", 617 "UMask": "0x1" 618 }, 619 { 620 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 621 "Counter": "0,1,2,3", 622 "EventCode": "0XB7", 623 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 624 "MSRIndex": "0x1a6,0x1a7", 625 "MSRValue": "0x8003C0001", 626 "Offcore": "1", 627 "SampleAfterValue": "100003", 628 "UMask": "0x1" 629 }, 630 { 631 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", 632 "Counter": "0,1,2,3", 633 "EventCode": "0XB7", 634 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 635 "MSRIndex": "0x1a6,0x1a7", 636 "MSRValue": "0x2003C0001", 637 "Offcore": "1", 638 "SampleAfterValue": "100003", 639 "UMask": "0x1" 640 }, 641 { 642 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", 643 "Counter": "0,1,2,3", 644 "EventCode": "0XB7", 645 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", 646 "MSRIndex": "0x1a6,0x1a7", 647 "MSRValue": "0x1003C0001", 648 "Offcore": "1", 649 "SampleAfterValue": "100003", 650 "UMask": "0x1" 651 }, 652 { 653 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", 654 "Counter": "0,1,2,3", 655 "EventCode": "0XB7", 656 "EventName": "OCR.DEMAND_RFO.L3_HIT", 657 "MSRIndex": "0x1a6,0x1a7", 658 "MSRValue": "0x1F803C0002", 659 "Offcore": "1", 660 "SampleAfterValue": "100003", 661 "UMask": "0x1" 662 }, 663 { 664 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 665 "Counter": "0,1,2,3", 666 "EventCode": "0XB7", 667 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 668 "MSRIndex": "0x1a6,0x1a7", 669 "MSRValue": "0x10003C0002", 670 "Offcore": "1", 671 "SampleAfterValue": "100003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 676 "Counter": "0,1,2,3", 677 "EventCode": "0XB7", 678 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", 679 "MSRIndex": "0x1a6,0x1a7", 680 "MSRValue": "0x4003C0002", 681 "Offcore": "1", 682 "SampleAfterValue": "100003", 683 "UMask": "0x1" 684 }, 685 { 686 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 687 "Counter": "0,1,2,3", 688 "EventCode": "0XB7", 689 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 690 "MSRIndex": "0x1a6,0x1a7", 691 "MSRValue": "0x8003C0002", 692 "Offcore": "1", 693 "SampleAfterValue": "100003", 694 "UMask": "0x1" 695 }, 696 { 697 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 698 "Counter": "0,1,2,3", 699 "EventCode": "0XB7", 700 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 701 "MSRIndex": "0x1a6,0x1a7", 702 "MSRValue": "0x2003C0002", 703 "Offcore": "1", 704 "SampleAfterValue": "100003", 705 "UMask": "0x1" 706 }, 707 { 708 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 709 "Counter": "0,1,2,3", 710 "EventCode": "0XB7", 711 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", 712 "MSRIndex": "0x1a6,0x1a7", 713 "MSRValue": "0x1003C0002", 714 "Offcore": "1", 715 "SampleAfterValue": "100003", 716 "UMask": "0x1" 717 }, 718 { 719 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", 720 "Counter": "0,1,2,3", 721 "EventCode": "0XB7", 722 "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", 723 "MSRIndex": "0x1a6,0x1a7", 724 "MSRValue": "0x801F803C0000", 725 "Offcore": "1", 726 "SampleAfterValue": "100003", 727 "UMask": "0x1" 728 }, 729 { 730 "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 731 "Counter": "0,1,2,3", 732 "EventCode": "0XB7", 733 "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", 734 "MSRIndex": "0x1a6,0x1a7", 735 "MSRValue": "0x10003C0400", 736 "Offcore": "1", 737 "SampleAfterValue": "100003", 738 "UMask": "0x1" 739 }, 740 { 741 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", 742 "Counter": "0,1,2,3", 743 "EventCode": "0XB7", 744 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", 745 "MSRIndex": "0x1a6,0x1a7", 746 "MSRValue": "0x1F803C0040", 747 "Offcore": "1", 748 "SampleAfterValue": "100003", 749 "UMask": "0x1" 750 }, 751 { 752 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 753 "Counter": "0,1,2,3", 754 "EventCode": "0XB7", 755 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", 756 "MSRIndex": "0x1a6,0x1a7", 757 "MSRValue": "0x10003C0040", 758 "Offcore": "1", 759 "SampleAfterValue": "100003", 760 "UMask": "0x1" 761 }, 762 { 763 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 764 "Counter": "0,1,2,3", 765 "EventCode": "0XB7", 766 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", 767 "MSRIndex": "0x1a6,0x1a7", 768 "MSRValue": "0x4003C0040", 769 "Offcore": "1", 770 "SampleAfterValue": "100003", 771 "UMask": "0x1" 772 }, 773 { 774 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 775 "Counter": "0,1,2,3", 776 "EventCode": "0XB7", 777 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 778 "MSRIndex": "0x1a6,0x1a7", 779 "MSRValue": "0x8003C0040", 780 "Offcore": "1", 781 "SampleAfterValue": "100003", 782 "UMask": "0x1" 783 }, 784 { 785 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 786 "Counter": "0,1,2,3", 787 "EventCode": "0XB7", 788 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", 789 "MSRIndex": "0x1a6,0x1a7", 790 "MSRValue": "0x2003C0040", 791 "Offcore": "1", 792 "SampleAfterValue": "100003", 793 "UMask": "0x1" 794 }, 795 { 796 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 797 "Counter": "0,1,2,3", 798 "EventCode": "0XB7", 799 "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", 800 "MSRIndex": "0x1a6,0x1a7", 801 "MSRValue": "0x1003C0040", 802 "Offcore": "1", 803 "SampleAfterValue": "100003", 804 "UMask": "0x1" 805 }, 806 { 807 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", 808 "Counter": "0,1,2,3", 809 "EventCode": "0XB7", 810 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x1F803C0010", 813 "Offcore": "1", 814 "SampleAfterValue": "100003", 815 "UMask": "0x1" 816 }, 817 { 818 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 819 "Counter": "0,1,2,3", 820 "EventCode": "0XB7", 821 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", 822 "MSRIndex": "0x1a6,0x1a7", 823 "MSRValue": "0x10003C0010", 824 "Offcore": "1", 825 "SampleAfterValue": "100003", 826 "UMask": "0x1" 827 }, 828 { 829 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 830 "Counter": "0,1,2,3", 831 "EventCode": "0XB7", 832 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 833 "MSRIndex": "0x1a6,0x1a7", 834 "MSRValue": "0x4003C0010", 835 "Offcore": "1", 836 "SampleAfterValue": "100003", 837 "UMask": "0x1" 838 }, 839 { 840 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 841 "Counter": "0,1,2,3", 842 "EventCode": "0XB7", 843 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 844 "MSRIndex": "0x1a6,0x1a7", 845 "MSRValue": "0x8003C0010", 846 "Offcore": "1", 847 "SampleAfterValue": "100003", 848 "UMask": "0x1" 849 }, 850 { 851 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 852 "Counter": "0,1,2,3", 853 "EventCode": "0XB7", 854 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 855 "MSRIndex": "0x1a6,0x1a7", 856 "MSRValue": "0x2003C0010", 857 "Offcore": "1", 858 "SampleAfterValue": "100003", 859 "UMask": "0x1" 860 }, 861 { 862 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 863 "Counter": "0,1,2,3", 864 "EventCode": "0XB7", 865 "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", 866 "MSRIndex": "0x1a6,0x1a7", 867 "MSRValue": "0x1003C0010", 868 "Offcore": "1", 869 "SampleAfterValue": "100003", 870 "UMask": "0x1" 871 }, 872 { 873 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", 874 "Counter": "0,1,2,3", 875 "EventCode": "0XB7", 876 "EventName": "OCR.HWPF_L2_RFO.L3_HIT", 877 "MSRIndex": "0x1a6,0x1a7", 878 "MSRValue": "0x1F803C0020", 879 "Offcore": "1", 880 "SampleAfterValue": "100003", 881 "UMask": "0x1" 882 }, 883 { 884 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 885 "Counter": "0,1,2,3", 886 "EventCode": "0XB7", 887 "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", 888 "MSRIndex": "0x1a6,0x1a7", 889 "MSRValue": "0x10003C0020", 890 "Offcore": "1", 891 "SampleAfterValue": "100003", 892 "UMask": "0x1" 893 }, 894 { 895 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 896 "Counter": "0,1,2,3", 897 "EventCode": "0XB7", 898 "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0x4003C0020", 901 "Offcore": "1", 902 "SampleAfterValue": "100003", 903 "UMask": "0x1" 904 }, 905 { 906 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 907 "Counter": "0,1,2,3", 908 "EventCode": "0XB7", 909 "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 910 "MSRIndex": "0x1a6,0x1a7", 911 "MSRValue": "0x8003C0020", 912 "Offcore": "1", 913 "SampleAfterValue": "100003", 914 "UMask": "0x1" 915 }, 916 { 917 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 918 "Counter": "0,1,2,3", 919 "EventCode": "0XB7", 920 "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", 921 "MSRIndex": "0x1a6,0x1a7", 922 "MSRValue": "0x2003C0020", 923 "Offcore": "1", 924 "SampleAfterValue": "100003", 925 "UMask": "0x1" 926 }, 927 { 928 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 929 "Counter": "0,1,2,3", 930 "EventCode": "0XB7", 931 "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", 932 "MSRIndex": "0x1a6,0x1a7", 933 "MSRValue": "0x1003C0020", 934 "Offcore": "1", 935 "SampleAfterValue": "100003", 936 "UMask": "0x1" 937 }, 938 { 939 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", 940 "Counter": "0,1,2,3", 941 "EventCode": "0XB7", 942 "EventName": "OCR.L1WB_M.L3_HIT", 943 "MSRIndex": "0x1a6,0x1a7", 944 "MSRValue": "0x1001F803C0000", 945 "Offcore": "1", 946 "SampleAfterValue": "100003", 947 "UMask": "0x1" 948 }, 949 { 950 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", 951 "Counter": "0,1,2,3", 952 "EventCode": "0XB7", 953 "EventName": "OCR.L2WB_M.L3_HIT", 954 "MSRIndex": "0x1a6,0x1a7", 955 "MSRValue": "0x2001F803C0000", 956 "Offcore": "1", 957 "SampleAfterValue": "100003", 958 "UMask": "0x1" 959 }, 960 { 961 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", 962 "Counter": "0,1,2,3", 963 "EventCode": "0XB7", 964 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", 965 "MSRIndex": "0x1a6,0x1a7", 966 "MSRValue": "0x401F803C0000", 967 "Offcore": "1", 968 "SampleAfterValue": "100003", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", 973 "Counter": "0,1,2,3", 974 "EventCode": "0XB7", 975 "EventName": "OCR.READS_TO_CORE.L3_HIT", 976 "MSRIndex": "0x1a6,0x1a7", 977 "MSRValue": "0x1F803C0477", 978 "Offcore": "1", 979 "SampleAfterValue": "100003", 980 "UMask": "0x1" 981 }, 982 { 983 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 984 "Counter": "0,1,2,3", 985 "EventCode": "0XB7", 986 "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", 987 "MSRIndex": "0x1a6,0x1a7", 988 "MSRValue": "0x10003C0477", 989 "Offcore": "1", 990 "SampleAfterValue": "100003", 991 "UMask": "0x1" 992 }, 993 { 994 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 995 "Counter": "0,1,2,3", 996 "EventCode": "0XB7", 997 "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", 998 "MSRIndex": "0x1a6,0x1a7", 999 "MSRValue": "0x4003C0477", 1000 "Offcore": "1", 1001 "SampleAfterValue": "100003", 1002 "UMask": "0x1" 1003 }, 1004 { 1005 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 1006 "Counter": "0,1,2,3", 1007 "EventCode": "0XB7", 1008 "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", 1009 "MSRIndex": "0x1a6,0x1a7", 1010 "MSRValue": "0x8003C0477", 1011 "Offcore": "1", 1012 "SampleAfterValue": "100003", 1013 "UMask": "0x1" 1014 }, 1015 { 1016 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 1017 "Counter": "0,1,2,3", 1018 "EventCode": "0XB7", 1019 "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", 1020 "MSRIndex": "0x1a6,0x1a7", 1021 "MSRValue": "0x2003C0477", 1022 "Offcore": "1", 1023 "SampleAfterValue": "100003", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 1028 "Counter": "0,1,2,3", 1029 "EventCode": "0XB7", 1030 "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", 1031 "MSRIndex": "0x1a6,0x1a7", 1032 "MSRValue": "0x1003C0477", 1033 "Offcore": "1", 1034 "SampleAfterValue": "100003", 1035 "UMask": "0x1" 1036 }, 1037 { 1038 "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", 1039 "Counter": "0,1,2,3", 1040 "EventCode": "0XB7", 1041 "EventName": "OCR.STREAMING_WR.L3_HIT", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "MSRValue": "0x1F803C0800", 1044 "Offcore": "1", 1045 "SampleAfterValue": "100003", 1046 "UMask": "0x1" 1047 }, 1048 { 1049 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", 1050 "Counter": "0,1,2,3", 1051 "EventCode": "0XB7", 1052 "EventName": "OCR.UC_RD.L3_HIT", 1053 "MSRIndex": "0x1a6,0x1a7", 1054 "MSRValue": "0x101F803C0000", 1055 "Offcore": "1", 1056 "SampleAfterValue": "100003", 1057 "UMask": "0x1" 1058 }, 1059 { 1060 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 1061 "Counter": "0,1,2,3", 1062 "EventCode": "0XB7", 1063 "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", 1064 "MSRIndex": "0x1a6,0x1a7", 1065 "MSRValue": "0x1010003C0000", 1066 "Offcore": "1", 1067 "SampleAfterValue": "100003", 1068 "UMask": "0x1" 1069 }, 1070 { 1071 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 1072 "Counter": "0,1,2,3", 1073 "EventCode": "0XB7", 1074 "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", 1075 "MSRIndex": "0x1a6,0x1a7", 1076 "MSRValue": "0x1004003C0000", 1077 "Offcore": "1", 1078 "SampleAfterValue": "100003", 1079 "UMask": "0x1" 1080 }, 1081 { 1082 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 1083 "Counter": "0,1,2,3", 1084 "EventCode": "0XB7", 1085 "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 1086 "MSRIndex": "0x1a6,0x1a7", 1087 "MSRValue": "0x1008003C0000", 1088 "Offcore": "1", 1089 "SampleAfterValue": "100003", 1090 "UMask": "0x1" 1091 }, 1092 { 1093 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", 1094 "Counter": "0,1,2,3", 1095 "EventCode": "0XB7", 1096 "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", 1097 "MSRIndex": "0x1a6,0x1a7", 1098 "MSRValue": "0x1002003C0000", 1099 "Offcore": "1", 1100 "SampleAfterValue": "100003", 1101 "UMask": "0x1" 1102 }, 1103 { 1104 "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", 1105 "Counter": "0,1,2,3", 1106 "EventCode": "0XB7", 1107 "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", 1108 "MSRIndex": "0x1a6,0x1a7", 1109 "MSRValue": "0x1001003C0000", 1110 "Offcore": "1", 1111 "SampleAfterValue": "100003", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", 1116 "Counter": "0,1,2,3", 1117 "EventCode": "0XB7", 1118 "EventName": "OCR.UC_WR.L3_HIT", 1119 "MSRIndex": "0x1a6,0x1a7", 1120 "MSRValue": "0x201F803C0000", 1121 "Offcore": "1", 1122 "SampleAfterValue": "100003", 1123 "UMask": "0x1" 1124 }, 1125 { 1126 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", 1127 "CollectPEBSRecord": "2", 1128 "Counter": "0,1,2,3", 1129 "EventCode": "0x71", 1130 "EventName": "TOPDOWN_FE_BOUND.ICACHE", 1131 "PDIR_COUNTER": "na", 1132 "PEBScounters": "0,1,2,3", 1133 "SampleAfterValue": "1000003", 1134 "UMask": "0x20" 1135 } 1136]