1[ 2 { 3 "PublicDescription": "Number of times a TSX line had a cache conflict.", 4 "EventCode": "0x54", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "TX_MEM.ABORT_CONFLICT", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "EventCode": "0x54", 14 "Counter": "0,1,2,3", 15 "UMask": "0x2", 16 "EventName": "TX_MEM.ABORT_CAPACITY", 17 "SampleAfterValue": "2000003", 18 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 19 "CounterHTOff": "0,1,2,3,4,5,6,7" 20 }, 21 { 22 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 23 "EventCode": "0x54", 24 "Counter": "0,1,2,3", 25 "UMask": "0x4", 26 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 27 "SampleAfterValue": "2000003", 28 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 33 "EventCode": "0x54", 34 "Counter": "0,1,2,3", 35 "UMask": "0x8", 36 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 37 "SampleAfterValue": "2000003", 38 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 39 "CounterHTOff": "0,1,2,3,4,5,6,7" 40 }, 41 { 42 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 43 "EventCode": "0x54", 44 "Counter": "0,1,2,3", 45 "UMask": "0x10", 46 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 47 "SampleAfterValue": "2000003", 48 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 49 "CounterHTOff": "0,1,2,3,4,5,6,7" 50 }, 51 { 52 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 53 "EventCode": "0x54", 54 "Counter": "0,1,2,3", 55 "UMask": "0x20", 56 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 57 "SampleAfterValue": "2000003", 58 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 59 "CounterHTOff": "0,1,2,3,4,5,6,7" 60 }, 61 { 62 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 63 "EventCode": "0x54", 64 "Counter": "0,1,2,3", 65 "UMask": "0x40", 66 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 67 "SampleAfterValue": "2000003", 68 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 69 "CounterHTOff": "0,1,2,3,4,5,6,7" 70 }, 71 { 72 "EventCode": "0x5d", 73 "Counter": "0,1,2,3", 74 "UMask": "0x1", 75 "EventName": "TX_EXEC.MISC1", 76 "SampleAfterValue": "2000003", 77 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 78 "CounterHTOff": "0,1,2,3,4,5,6,7" 79 }, 80 { 81 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 82 "EventCode": "0x5d", 83 "Counter": "0,1,2,3", 84 "UMask": "0x2", 85 "EventName": "TX_EXEC.MISC2", 86 "SampleAfterValue": "2000003", 87 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 88 "CounterHTOff": "0,1,2,3,4,5,6,7" 89 }, 90 { 91 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 92 "EventCode": "0x5d", 93 "Counter": "0,1,2,3", 94 "UMask": "0x4", 95 "EventName": "TX_EXEC.MISC3", 96 "SampleAfterValue": "2000003", 97 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 98 "CounterHTOff": "0,1,2,3,4,5,6,7" 99 }, 100 { 101 "PublicDescription": "RTM region detected inside HLE.", 102 "EventCode": "0x5d", 103 "Counter": "0,1,2,3", 104 "UMask": "0x8", 105 "EventName": "TX_EXEC.MISC4", 106 "SampleAfterValue": "2000003", 107 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 108 "CounterHTOff": "0,1,2,3,4,5,6,7" 109 }, 110 { 111 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 112 "EventCode": "0x5d", 113 "Counter": "0,1,2,3", 114 "UMask": "0x10", 115 "EventName": "TX_EXEC.MISC5", 116 "SampleAfterValue": "2000003", 117 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 118 "CounterHTOff": "0,1,2,3,4,5,6,7" 119 }, 120 { 121 "EventCode": "0x60", 122 "Counter": "0,1,2,3", 123 "UMask": "0x10", 124 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 125 "SampleAfterValue": "2000003", 126 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 127 "CounterHTOff": "0,1,2,3,4,5,6,7" 128 }, 129 { 130 "EventCode": "0x60", 131 "Counter": "0,1,2,3", 132 "UMask": "0x10", 133 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 134 "SampleAfterValue": "2000003", 135 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 136 "CounterMask": "1", 137 "CounterHTOff": "0,1,2,3,4,5,6,7" 138 }, 139 { 140 "EventCode": "0x60", 141 "Counter": "0,1,2,3", 142 "UMask": "0x10", 143 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 144 "SampleAfterValue": "2000003", 145 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 146 "CounterMask": "6", 147 "CounterHTOff": "0,1,2,3,4,5,6,7" 148 }, 149 { 150 "EventCode": "0xA3", 151 "Counter": "0,1,2,3", 152 "UMask": "0x2", 153 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 154 "SampleAfterValue": "2000003", 155 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 156 "CounterMask": "2", 157 "CounterHTOff": "0,1,2,3,4,5,6,7" 158 }, 159 { 160 "EventCode": "0xA3", 161 "Counter": "0,1,2,3", 162 "UMask": "0x6", 163 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 164 "SampleAfterValue": "2000003", 165 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 166 "CounterMask": "6", 167 "CounterHTOff": "0,1,2,3,4,5,6,7" 168 }, 169 { 170 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 171 "EventCode": "0xB0", 172 "Counter": "0,1,2,3", 173 "UMask": "0x10", 174 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 175 "SampleAfterValue": "100003", 176 "BriefDescription": "Demand Data Read requests who miss L3 cache", 177 "CounterHTOff": "0,1,2,3,4,5,6,7" 178 }, 179 { 180 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 181 "EventCode": "0xC3", 182 "Counter": "0,1,2,3", 183 "UMask": "0x2", 184 "Errata": "SKL089", 185 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 186 "SampleAfterValue": "100003", 187 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 188 "CounterHTOff": "0,1,2,3,4,5,6,7" 189 }, 190 { 191 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 192 "EventCode": "0xC8", 193 "Counter": "0,1,2,3", 194 "UMask": "0x1", 195 "EventName": "HLE_RETIRED.START", 196 "SampleAfterValue": "2000003", 197 "BriefDescription": "Number of times an HLE execution started.", 198 "CounterHTOff": "0,1,2,3,4,5,6,7" 199 }, 200 { 201 "PublicDescription": "Number of times HLE commit succeeded.", 202 "EventCode": "0xC8", 203 "Counter": "0,1,2,3", 204 "UMask": "0x2", 205 "EventName": "HLE_RETIRED.COMMIT", 206 "SampleAfterValue": "2000003", 207 "BriefDescription": "Number of times an HLE execution successfully committed", 208 "CounterHTOff": "0,1,2,3,4,5,6,7" 209 }, 210 { 211 "PEBS": "1", 212 "PublicDescription": "Number of times HLE abort was triggered. (PEBS)", 213 "EventCode": "0xC8", 214 "Counter": "0,1,2,3", 215 "UMask": "0x4", 216 "EventName": "HLE_RETIRED.ABORTED", 217 "SampleAfterValue": "2000003", 218 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 219 "CounterHTOff": "0,1,2,3,4,5,6,7" 220 }, 221 { 222 "EventCode": "0xC8", 223 "Counter": "0,1,2,3", 224 "UMask": "0x8", 225 "EventName": "HLE_RETIRED.ABORTED_MEM", 226 "SampleAfterValue": "2000003", 227 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 228 "CounterHTOff": "0,1,2,3,4,5,6,7" 229 }, 230 { 231 "EventCode": "0xC8", 232 "Counter": "0,1,2,3", 233 "UMask": "0x10", 234 "EventName": "HLE_RETIRED.ABORTED_TIMER", 235 "SampleAfterValue": "2000003", 236 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 237 "CounterHTOff": "0,1,2,3,4,5,6,7" 238 }, 239 { 240 "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 241 "EventCode": "0xC8", 242 "Counter": "0,1,2,3", 243 "UMask": "0x20", 244 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 245 "SampleAfterValue": "2000003", 246 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 247 "CounterHTOff": "0,1,2,3,4,5,6,7" 248 }, 249 { 250 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 251 "EventCode": "0xC8", 252 "Counter": "0,1,2,3", 253 "UMask": "0x40", 254 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 255 "SampleAfterValue": "2000003", 256 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 257 "CounterHTOff": "0,1,2,3,4,5,6,7" 258 }, 259 { 260 "EventCode": "0xC8", 261 "Counter": "0,1,2,3", 262 "UMask": "0x80", 263 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 264 "SampleAfterValue": "2000003", 265 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 266 "CounterHTOff": "0,1,2,3,4,5,6,7" 267 }, 268 { 269 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 270 "EventCode": "0xC9", 271 "Counter": "0,1,2,3", 272 "UMask": "0x1", 273 "EventName": "RTM_RETIRED.START", 274 "SampleAfterValue": "2000003", 275 "BriefDescription": "Number of times an RTM execution started.", 276 "CounterHTOff": "0,1,2,3,4,5,6,7" 277 }, 278 { 279 "PublicDescription": "Number of times RTM commit succeeded.", 280 "EventCode": "0xC9", 281 "Counter": "0,1,2,3", 282 "UMask": "0x2", 283 "EventName": "RTM_RETIRED.COMMIT", 284 "SampleAfterValue": "2000003", 285 "BriefDescription": "Number of times an RTM execution successfully committed", 286 "CounterHTOff": "0,1,2,3,4,5,6,7" 287 }, 288 { 289 "PEBS": "1", 290 "PublicDescription": "Number of times RTM abort was triggered. (PEBS)", 291 "EventCode": "0xC9", 292 "Counter": "0,1,2,3", 293 "UMask": "0x4", 294 "EventName": "RTM_RETIRED.ABORTED", 295 "SampleAfterValue": "2000003", 296 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 297 "CounterHTOff": "0,1,2,3,4,5,6,7" 298 }, 299 { 300 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 301 "EventCode": "0xC9", 302 "Counter": "0,1,2,3", 303 "UMask": "0x8", 304 "EventName": "RTM_RETIRED.ABORTED_MEM", 305 "SampleAfterValue": "2000003", 306 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 307 "CounterHTOff": "0,1,2,3,4,5,6,7" 308 }, 309 { 310 "EventCode": "0xC9", 311 "Counter": "0,1,2,3", 312 "UMask": "0x10", 313 "EventName": "RTM_RETIRED.ABORTED_TIMER", 314 "SampleAfterValue": "2000003", 315 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 316 "CounterHTOff": "0,1,2,3,4,5,6,7" 317 }, 318 { 319 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 320 "EventCode": "0xC9", 321 "Counter": "0,1,2,3", 322 "UMask": "0x20", 323 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 324 "SampleAfterValue": "2000003", 325 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 326 "CounterHTOff": "0,1,2,3,4,5,6,7" 327 }, 328 { 329 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 330 "EventCode": "0xC9", 331 "Counter": "0,1,2,3", 332 "UMask": "0x40", 333 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 334 "SampleAfterValue": "2000003", 335 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 336 "CounterHTOff": "0,1,2,3,4,5,6,7" 337 }, 338 { 339 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 340 "EventCode": "0xC9", 341 "Counter": "0,1,2,3", 342 "UMask": "0x80", 343 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 344 "SampleAfterValue": "2000003", 345 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 346 "CounterHTOff": "0,1,2,3,4,5,6,7" 347 }, 348 { 349 "PEBS": "2", 350 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 351 "EventCode": "0xCD", 352 "MSRValue": "0x4", 353 "Counter": "0,1,2,3", 354 "UMask": "0x1", 355 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 356 "MSRIndex": "0x3F6", 357 "SampleAfterValue": "100003", 358 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 359 "TakenAlone": "1", 360 "CounterHTOff": "0,1,2,3" 361 }, 362 { 363 "PEBS": "2", 364 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 365 "EventCode": "0xCD", 366 "MSRValue": "0x8", 367 "Counter": "0,1,2,3", 368 "UMask": "0x1", 369 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 370 "MSRIndex": "0x3F6", 371 "SampleAfterValue": "50021", 372 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 373 "TakenAlone": "1", 374 "CounterHTOff": "0,1,2,3" 375 }, 376 { 377 "PEBS": "2", 378 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 379 "EventCode": "0xCD", 380 "MSRValue": "0x10", 381 "Counter": "0,1,2,3", 382 "UMask": "0x1", 383 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 384 "MSRIndex": "0x3F6", 385 "SampleAfterValue": "20011", 386 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 387 "TakenAlone": "1", 388 "CounterHTOff": "0,1,2,3" 389 }, 390 { 391 "PEBS": "2", 392 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 393 "EventCode": "0xCD", 394 "MSRValue": "0x20", 395 "Counter": "0,1,2,3", 396 "UMask": "0x1", 397 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 398 "MSRIndex": "0x3F6", 399 "SampleAfterValue": "100007", 400 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 401 "TakenAlone": "1", 402 "CounterHTOff": "0,1,2,3" 403 }, 404 { 405 "PEBS": "2", 406 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 407 "EventCode": "0xCD", 408 "MSRValue": "0x40", 409 "Counter": "0,1,2,3", 410 "UMask": "0x1", 411 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 412 "MSRIndex": "0x3F6", 413 "SampleAfterValue": "2003", 414 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 415 "TakenAlone": "1", 416 "CounterHTOff": "0,1,2,3" 417 }, 418 { 419 "PEBS": "2", 420 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 421 "EventCode": "0xCD", 422 "MSRValue": "0x80", 423 "Counter": "0,1,2,3", 424 "UMask": "0x1", 425 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 426 "MSRIndex": "0x3F6", 427 "SampleAfterValue": "1009", 428 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 429 "TakenAlone": "1", 430 "CounterHTOff": "0,1,2,3" 431 }, 432 { 433 "PEBS": "2", 434 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 435 "EventCode": "0xCD", 436 "MSRValue": "0x100", 437 "Counter": "0,1,2,3", 438 "UMask": "0x1", 439 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 440 "MSRIndex": "0x3F6", 441 "SampleAfterValue": "503", 442 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 443 "TakenAlone": "1", 444 "CounterHTOff": "0,1,2,3" 445 }, 446 { 447 "PEBS": "2", 448 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 449 "EventCode": "0xCD", 450 "MSRValue": "0x200", 451 "Counter": "0,1,2,3", 452 "UMask": "0x1", 453 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 454 "MSRIndex": "0x3F6", 455 "SampleAfterValue": "101", 456 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 457 "TakenAlone": "1", 458 "CounterHTOff": "0,1,2,3" 459 }, 460 { 461 "PublicDescription": "Counts any other requests", 462 "EventCode": "0xB7, 0xBB", 463 "MSRValue": "0x3FFC408000", 464 "Counter": "0,1,2,3", 465 "UMask": "0x1", 466 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", 467 "MSRIndex": "0x1a6, 0x1a7", 468 "SampleAfterValue": "100003", 469 "BriefDescription": "Counts any other requests", 470 "Offcore": "1", 471 "CounterHTOff": "0,1,2,3" 472 }, 473 { 474 "PublicDescription": "Counts any other requests", 475 "EventCode": "0xB7, 0xBB", 476 "MSRValue": "0x203C408000", 477 "Counter": "0,1,2,3", 478 "UMask": "0x1", 479 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", 480 "MSRIndex": "0x1a6, 0x1a7", 481 "SampleAfterValue": "100003", 482 "BriefDescription": "Counts any other requests", 483 "Offcore": "1", 484 "CounterHTOff": "0,1,2,3" 485 }, 486 { 487 "PublicDescription": "Counts any other requests", 488 "EventCode": "0xB7, 0xBB", 489 "MSRValue": "0x103C408000", 490 "Counter": "0,1,2,3", 491 "UMask": "0x1", 492 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", 493 "MSRIndex": "0x1a6, 0x1a7", 494 "SampleAfterValue": "100003", 495 "BriefDescription": "Counts any other requests", 496 "Offcore": "1", 497 "CounterHTOff": "0,1,2,3" 498 }, 499 { 500 "PublicDescription": "Counts any other requests", 501 "EventCode": "0xB7, 0xBB", 502 "MSRValue": "0x043C408000", 503 "Counter": "0,1,2,3", 504 "UMask": "0x1", 505 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", 506 "MSRIndex": "0x1a6, 0x1a7", 507 "SampleAfterValue": "100003", 508 "BriefDescription": "Counts any other requests", 509 "Offcore": "1", 510 "CounterHTOff": "0,1,2,3" 511 }, 512 { 513 "PublicDescription": "Counts any other requests", 514 "EventCode": "0xB7, 0xBB", 515 "MSRValue": "0x023C408000", 516 "Counter": "0,1,2,3", 517 "UMask": "0x1", 518 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 519 "MSRIndex": "0x1a6, 0x1a7", 520 "SampleAfterValue": "100003", 521 "BriefDescription": "Counts any other requests", 522 "Offcore": "1", 523 "CounterHTOff": "0,1,2,3" 524 }, 525 { 526 "PublicDescription": "Counts any other requests", 527 "EventCode": "0xB7, 0xBB", 528 "MSRValue": "0x013C408000", 529 "Counter": "0,1,2,3", 530 "UMask": "0x1", 531 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 532 "MSRIndex": "0x1a6, 0x1a7", 533 "SampleAfterValue": "100003", 534 "BriefDescription": "Counts any other requests", 535 "Offcore": "1", 536 "CounterHTOff": "0,1,2,3" 537 }, 538 { 539 "PublicDescription": "Counts any other requests", 540 "EventCode": "0xB7, 0xBB", 541 "MSRValue": "0x00BC408000", 542 "Counter": "0,1,2,3", 543 "UMask": "0x1", 544 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 545 "MSRIndex": "0x1a6, 0x1a7", 546 "SampleAfterValue": "100003", 547 "BriefDescription": "Counts any other requests", 548 "Offcore": "1", 549 "CounterHTOff": "0,1,2,3" 550 }, 551 { 552 "PublicDescription": "Counts any other requests", 553 "EventCode": "0xB7, 0xBB", 554 "MSRValue": "0x007C408000", 555 "Counter": "0,1,2,3", 556 "UMask": "0x1", 557 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", 558 "MSRIndex": "0x1a6, 0x1a7", 559 "SampleAfterValue": "100003", 560 "BriefDescription": "Counts any other requests", 561 "Offcore": "1", 562 "CounterHTOff": "0,1,2,3" 563 }, 564 { 565 "PublicDescription": "Counts any other requests", 566 "EventCode": "0xB7, 0xBB", 567 "MSRValue": "0x3FC4008000", 568 "Counter": "0,1,2,3", 569 "UMask": "0x1", 570 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 571 "MSRIndex": "0x1a6, 0x1a7", 572 "SampleAfterValue": "100003", 573 "BriefDescription": "Counts any other requests", 574 "Offcore": "1", 575 "CounterHTOff": "0,1,2,3" 576 }, 577 { 578 "PublicDescription": "Counts any other requests", 579 "EventCode": "0xB7, 0xBB", 580 "MSRValue": "0x2004008000", 581 "Counter": "0,1,2,3", 582 "UMask": "0x1", 583 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 584 "MSRIndex": "0x1a6, 0x1a7", 585 "SampleAfterValue": "100003", 586 "BriefDescription": "Counts any other requests", 587 "Offcore": "1", 588 "CounterHTOff": "0,1,2,3" 589 }, 590 { 591 "PublicDescription": "Counts any other requests", 592 "EventCode": "0xB7, 0xBB", 593 "MSRValue": "0x1004008000", 594 "Counter": "0,1,2,3", 595 "UMask": "0x1", 596 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 597 "MSRIndex": "0x1a6, 0x1a7", 598 "SampleAfterValue": "100003", 599 "BriefDescription": "Counts any other requests", 600 "Offcore": "1", 601 "CounterHTOff": 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"PublicDescription": "Counts demand data reads", 1580 "EventCode": "0xB7, 0xBB", 1581 "MSRValue": "0x2000040001", 1582 "Counter": "0,1,2,3", 1583 "UMask": "0x1", 1584 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 1585 "MSRIndex": "0x1a6, 0x1a7", 1586 "SampleAfterValue": "100003", 1587 "BriefDescription": "Counts demand data reads", 1588 "Offcore": "1", 1589 "CounterHTOff": "0,1,2,3" 1590 }, 1591 { 1592 "PublicDescription": "Counts demand data reads", 1593 "EventCode": "0xB7, 0xBB", 1594 "MSRValue": "0x2000020001", 1595 "Counter": "0,1,2,3", 1596 "UMask": "0x1", 1597 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1598 "MSRIndex": "0x1a6, 0x1a7", 1599 "SampleAfterValue": "100003", 1600 "BriefDescription": "Counts demand data reads", 1601 "Offcore": "1", 1602 "CounterHTOff": "0,1,2,3" 1603 } 1604]