1959826caSMatt Macy[ 2959826caSMatt Macy { 3*18054d02SAlexander Motin "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 4959826caSMatt Macy "Counter": "0,1,2,3", 5*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 6959826caSMatt Macy "EventCode": "0x5C", 7959826caSMatt Macy "EventName": "CPL_CYCLES.RING0", 8959826caSMatt Macy "SampleAfterValue": "2000003", 9*18054d02SAlexander Motin "UMask": "0x1" 10959826caSMatt Macy }, 11959826caSMatt Macy { 12*18054d02SAlexander Motin "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 13959826caSMatt Macy "Counter": "0,1,2,3", 14*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 15*18054d02SAlexander Motin "CounterMask": "1", 16959826caSMatt Macy "EdgeDetect": "1", 17*18054d02SAlexander Motin "EventCode": "0x5C", 18959826caSMatt Macy "EventName": "CPL_CYCLES.RING0_TRANS", 19959826caSMatt Macy "SampleAfterValue": "100007", 20*18054d02SAlexander Motin "UMask": "0x1" 21959826caSMatt Macy }, 22959826caSMatt Macy { 23*18054d02SAlexander Motin "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 24959826caSMatt Macy "Counter": "0,1,2,3", 25*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 26*18054d02SAlexander Motin "EventCode": "0x5C", 27959826caSMatt Macy "EventName": "CPL_CYCLES.RING123", 28959826caSMatt Macy "SampleAfterValue": "2000003", 29*18054d02SAlexander Motin "UMask": "0x2" 30959826caSMatt Macy }, 31959826caSMatt Macy { 32*18054d02SAlexander Motin "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 33959826caSMatt Macy "Counter": "0,1,2,3", 34*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 35*18054d02SAlexander Motin "EventCode": "0x4E", 36*18054d02SAlexander Motin "EventName": "HW_PRE_REQ.DL1_MISS", 37*18054d02SAlexander Motin "SampleAfterValue": "2000003", 38*18054d02SAlexander Motin "UMask": "0x2" 39*18054d02SAlexander Motin }, 40*18054d02SAlexander Motin { 41*18054d02SAlexander Motin "BriefDescription": "Valid instructions written to IQ per cycle.", 42*18054d02SAlexander Motin "Counter": "0,1,2,3", 43*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 44*18054d02SAlexander Motin "EventCode": "0x17", 45*18054d02SAlexander Motin "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 46*18054d02SAlexander Motin "SampleAfterValue": "2000003", 47*18054d02SAlexander Motin "UMask": "0x1" 48*18054d02SAlexander Motin }, 49*18054d02SAlexander Motin { 50*18054d02SAlexander Motin "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 51*18054d02SAlexander Motin "Counter": "0,1,2,3", 52*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 53*18054d02SAlexander Motin "EventCode": "0x63", 54959826caSMatt Macy "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 55959826caSMatt Macy "SampleAfterValue": "2000003", 56*18054d02SAlexander Motin "UMask": "0x1" 57959826caSMatt Macy } 58959826caSMatt Macy]