1*959826caSMatt Macy[ 2*959826caSMatt Macy { 3*959826caSMatt Macy "EventCode": "0xE8", 4*959826caSMatt Macy "Counter": "0,1,2,3", 5*959826caSMatt Macy "UMask": "0x1", 6*959826caSMatt Macy "EventName": "BPU_CLEARS.EARLY", 7*959826caSMatt Macy "SampleAfterValue": "2000000", 8*959826caSMatt Macy "BriefDescription": "Early Branch Prediciton Unit clears" 9*959826caSMatt Macy }, 10*959826caSMatt Macy { 11*959826caSMatt Macy "EventCode": "0xE8", 12*959826caSMatt Macy "Counter": "0,1,2,3", 13*959826caSMatt Macy "UMask": "0x2", 14*959826caSMatt Macy "EventName": "BPU_CLEARS.LATE", 15*959826caSMatt Macy "SampleAfterValue": "2000000", 16*959826caSMatt Macy "BriefDescription": "Late Branch Prediction Unit clears" 17*959826caSMatt Macy }, 18*959826caSMatt Macy { 19*959826caSMatt Macy "EventCode": "0xE5", 20*959826caSMatt Macy "Counter": "0,1,2,3", 21*959826caSMatt Macy "UMask": "0x1", 22*959826caSMatt Macy "EventName": "BPU_MISSED_CALL_RET", 23*959826caSMatt Macy "SampleAfterValue": "2000000", 24*959826caSMatt Macy "BriefDescription": "Branch prediction unit missed call or return" 25*959826caSMatt Macy }, 26*959826caSMatt Macy { 27*959826caSMatt Macy "EventCode": "0xD5", 28*959826caSMatt Macy "Counter": "0,1,2,3", 29*959826caSMatt Macy "UMask": "0x1", 30*959826caSMatt Macy "EventName": "ES_REG_RENAMES", 31*959826caSMatt Macy "SampleAfterValue": "2000000", 32*959826caSMatt Macy "BriefDescription": "ES segment renames" 33*959826caSMatt Macy }, 34*959826caSMatt Macy { 35*959826caSMatt Macy "EventCode": "0x6C", 36*959826caSMatt Macy "Counter": "0,1,2,3", 37*959826caSMatt Macy "UMask": "0x1", 38*959826caSMatt Macy "EventName": "IO_TRANSACTIONS", 39*959826caSMatt Macy "SampleAfterValue": "2000000", 40*959826caSMatt Macy "BriefDescription": "I/O transactions" 41*959826caSMatt Macy }, 42*959826caSMatt Macy { 43*959826caSMatt Macy "EventCode": "0x80", 44*959826caSMatt Macy "Counter": "0,1,2,3", 45*959826caSMatt Macy "UMask": "0x4", 46*959826caSMatt Macy "EventName": "L1I.CYCLES_STALLED", 47*959826caSMatt Macy "SampleAfterValue": "2000000", 48*959826caSMatt Macy "BriefDescription": "L1I instruction fetch stall cycles" 49*959826caSMatt Macy }, 50*959826caSMatt Macy { 51*959826caSMatt Macy "EventCode": "0x80", 52*959826caSMatt Macy "Counter": "0,1,2,3", 53*959826caSMatt Macy "UMask": "0x1", 54*959826caSMatt Macy "EventName": "L1I.HITS", 55*959826caSMatt Macy "SampleAfterValue": "2000000", 56*959826caSMatt Macy "BriefDescription": "L1I instruction fetch hits" 57*959826caSMatt Macy }, 58*959826caSMatt Macy { 59*959826caSMatt Macy "EventCode": "0x80", 60*959826caSMatt Macy "Counter": "0,1,2,3", 61*959826caSMatt Macy "UMask": "0x2", 62*959826caSMatt Macy "EventName": "L1I.MISSES", 63*959826caSMatt Macy "SampleAfterValue": "2000000", 64*959826caSMatt Macy "BriefDescription": "L1I instruction fetch misses" 65*959826caSMatt Macy }, 66*959826caSMatt Macy { 67*959826caSMatt Macy "EventCode": "0x80", 68*959826caSMatt Macy "Counter": "0,1,2,3", 69*959826caSMatt Macy "UMask": "0x3", 70*959826caSMatt Macy "EventName": "L1I.READS", 71*959826caSMatt Macy "SampleAfterValue": "2000000", 72*959826caSMatt Macy "BriefDescription": "L1I Instruction fetches" 73*959826caSMatt Macy }, 74*959826caSMatt Macy { 75*959826caSMatt Macy "EventCode": "0x82", 76*959826caSMatt Macy "Counter": "0,1,2,3", 77*959826caSMatt Macy "UMask": "0x1", 78*959826caSMatt Macy "EventName": "LARGE_ITLB.HIT", 79*959826caSMatt Macy "SampleAfterValue": "200000", 80*959826caSMatt Macy "BriefDescription": "Large ITLB hit" 81*959826caSMatt Macy }, 82*959826caSMatt Macy { 83*959826caSMatt Macy "EventCode": "0x13", 84*959826caSMatt Macy "Counter": "0,1,2,3", 85*959826caSMatt Macy "UMask": "0x7", 86*959826caSMatt Macy "EventName": "LOAD_DISPATCH.ANY", 87*959826caSMatt Macy "SampleAfterValue": "2000000", 88*959826caSMatt Macy "BriefDescription": "All loads dispatched" 89*959826caSMatt Macy }, 90*959826caSMatt Macy { 91*959826caSMatt Macy "EventCode": "0x13", 92*959826caSMatt Macy "Counter": "0,1,2,3", 93*959826caSMatt Macy "UMask": "0x4", 94*959826caSMatt Macy "EventName": "LOAD_DISPATCH.MOB", 95*959826caSMatt Macy "SampleAfterValue": "2000000", 96*959826caSMatt Macy "BriefDescription": "Loads dispatched from the MOB" 97*959826caSMatt Macy }, 98*959826caSMatt Macy { 99*959826caSMatt Macy "EventCode": "0x13", 100*959826caSMatt Macy "Counter": "0,1,2,3", 101*959826caSMatt Macy "UMask": "0x1", 102*959826caSMatt Macy "EventName": "LOAD_DISPATCH.RS", 103*959826caSMatt Macy "SampleAfterValue": "2000000", 104*959826caSMatt Macy "BriefDescription": "Loads dispatched that bypass the MOB" 105*959826caSMatt Macy }, 106*959826caSMatt Macy { 107*959826caSMatt Macy "EventCode": "0x13", 108*959826caSMatt Macy "Counter": "0,1,2,3", 109*959826caSMatt Macy "UMask": "0x2", 110*959826caSMatt Macy "EventName": "LOAD_DISPATCH.RS_DELAYED", 111*959826caSMatt Macy "SampleAfterValue": "2000000", 112*959826caSMatt Macy "BriefDescription": "Loads dispatched from stage 305" 113*959826caSMatt Macy }, 114*959826caSMatt Macy { 115*959826caSMatt Macy "EventCode": "0x7", 116*959826caSMatt Macy "Counter": "0,1,2,3", 117*959826caSMatt Macy "UMask": "0x1", 118*959826caSMatt Macy "EventName": "PARTIAL_ADDRESS_ALIAS", 119*959826caSMatt Macy "SampleAfterValue": "200000", 120*959826caSMatt Macy "BriefDescription": "False dependencies due to partial address aliasing" 121*959826caSMatt Macy }, 122*959826caSMatt Macy { 123*959826caSMatt Macy "EventCode": "0xD2", 124*959826caSMatt Macy "Counter": "0,1,2,3", 125*959826caSMatt Macy "UMask": "0xf", 126*959826caSMatt Macy "EventName": "RAT_STALLS.ANY", 127*959826caSMatt Macy "SampleAfterValue": "2000000", 128*959826caSMatt Macy "BriefDescription": "All RAT stall cycles" 129*959826caSMatt Macy }, 130*959826caSMatt Macy { 131*959826caSMatt Macy "EventCode": "0xD2", 132*959826caSMatt Macy "Counter": "0,1,2,3", 133*959826caSMatt Macy "UMask": "0x1", 134*959826caSMatt Macy "EventName": "RAT_STALLS.FLAGS", 135*959826caSMatt Macy "SampleAfterValue": "2000000", 136*959826caSMatt Macy "BriefDescription": "Flag stall cycles" 137*959826caSMatt Macy }, 138*959826caSMatt Macy { 139*959826caSMatt Macy "EventCode": "0xD2", 140*959826caSMatt Macy "Counter": "0,1,2,3", 141*959826caSMatt Macy "UMask": "0x2", 142*959826caSMatt Macy "EventName": "RAT_STALLS.REGISTERS", 143*959826caSMatt Macy "SampleAfterValue": "2000000", 144*959826caSMatt Macy "BriefDescription": "Partial register stall cycles" 145*959826caSMatt Macy }, 146*959826caSMatt Macy { 147*959826caSMatt Macy "EventCode": "0xD2", 148*959826caSMatt Macy "Counter": "0,1,2,3", 149*959826caSMatt Macy "UMask": "0x4", 150*959826caSMatt Macy "EventName": "RAT_STALLS.ROB_READ_PORT", 151*959826caSMatt Macy "SampleAfterValue": "2000000", 152*959826caSMatt Macy "BriefDescription": "ROB read port stalls cycles" 153*959826caSMatt Macy }, 154*959826caSMatt Macy { 155*959826caSMatt Macy "EventCode": "0xD2", 156*959826caSMatt Macy "Counter": "0,1,2,3", 157*959826caSMatt Macy "UMask": "0x8", 158*959826caSMatt Macy "EventName": "RAT_STALLS.SCOREBOARD", 159*959826caSMatt Macy "SampleAfterValue": "2000000", 160*959826caSMatt Macy "BriefDescription": "Scoreboard stall cycles" 161*959826caSMatt Macy }, 162*959826caSMatt Macy { 163*959826caSMatt Macy "EventCode": "0x4", 164*959826caSMatt Macy "Counter": "0,1,2,3", 165*959826caSMatt Macy "UMask": "0x7", 166*959826caSMatt Macy "EventName": "SB_DRAIN.ANY", 167*959826caSMatt Macy "SampleAfterValue": "200000", 168*959826caSMatt Macy "BriefDescription": "All Store buffer stall cycles" 169*959826caSMatt Macy }, 170*959826caSMatt Macy { 171*959826caSMatt Macy "EventCode": "0xD4", 172*959826caSMatt Macy "Counter": "0,1,2,3", 173*959826caSMatt Macy "UMask": "0x1", 174*959826caSMatt Macy "EventName": "SEG_RENAME_STALLS", 175*959826caSMatt Macy "SampleAfterValue": "2000000", 176*959826caSMatt Macy "BriefDescription": "Segment rename stall cycles" 177*959826caSMatt Macy }, 178*959826caSMatt Macy { 179*959826caSMatt Macy "EventCode": "0xB8", 180*959826caSMatt Macy "Counter": "0,1,2,3", 181*959826caSMatt Macy "UMask": "0x1", 182*959826caSMatt Macy "EventName": "SNOOP_RESPONSE.HIT", 183*959826caSMatt Macy "SampleAfterValue": "100000", 184*959826caSMatt Macy "BriefDescription": "Thread responded HIT to snoop" 185*959826caSMatt Macy }, 186*959826caSMatt Macy { 187*959826caSMatt Macy "EventCode": "0xB8", 188*959826caSMatt Macy "Counter": "0,1,2,3", 189*959826caSMatt Macy "UMask": "0x2", 190*959826caSMatt Macy "EventName": "SNOOP_RESPONSE.HITE", 191*959826caSMatt Macy "SampleAfterValue": "100000", 192*959826caSMatt Macy "BriefDescription": "Thread responded HITE to snoop" 193*959826caSMatt Macy }, 194*959826caSMatt Macy { 195*959826caSMatt Macy "EventCode": "0xB8", 196*959826caSMatt Macy "Counter": "0,1,2,3", 197*959826caSMatt Macy "UMask": "0x4", 198*959826caSMatt Macy "EventName": "SNOOP_RESPONSE.HITM", 199*959826caSMatt Macy "SampleAfterValue": "100000", 200*959826caSMatt Macy "BriefDescription": "Thread responded HITM to snoop" 201*959826caSMatt Macy }, 202*959826caSMatt Macy { 203*959826caSMatt Macy "EventCode": "0xF6", 204*959826caSMatt Macy "Counter": "0,1,2,3", 205*959826caSMatt Macy "UMask": "0x1", 206*959826caSMatt Macy "EventName": "SQ_FULL_STALL_CYCLES", 207*959826caSMatt Macy "SampleAfterValue": "2000000", 208*959826caSMatt Macy "BriefDescription": "Super Queue full stall cycles" 209*959826caSMatt Macy } 210*959826caSMatt Macy]