1[ 2 { 3 "EventCode": "0x80", 4 "Counter": "0,1", 5 "UMask": "0x3", 6 "EventName": "ICACHE.ACCESSES", 7 "SampleAfterValue": "200003", 8 "BriefDescription": "Counts all instruction fetches, including uncacheable fetches." 9 }, 10 { 11 "EventCode": "0x80", 12 "Counter": "0,1", 13 "UMask": "0x1", 14 "EventName": "ICACHE.HIT", 15 "SampleAfterValue": "200003", 16 "BriefDescription": "Counts all instruction fetches that hit the instruction cache." 17 }, 18 { 19 "EventCode": "0x80", 20 "Counter": "0,1", 21 "UMask": "0x2", 22 "EventName": "ICACHE.MISSES", 23 "SampleAfterValue": "200003", 24 "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding." 25 }, 26 { 27 "EventCode": "0xE7", 28 "Counter": "0,1", 29 "UMask": "0x1", 30 "EventName": "MS_DECODED.MS_ENTRY", 31 "SampleAfterValue": "200003", 32 "BriefDescription": "Counts the number of times the MSROM starts a flow of uops." 33 } 34]