1959826caSMatt Macy[ 2959826caSMatt Macy { 3*18054d02SAlexander Motin "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", 4959826caSMatt Macy "Counter": "0,1", 5*18054d02SAlexander Motin "EventCode": "0xE6", 6*18054d02SAlexander Motin "EventName": "BACLEARS.ALL", 7*18054d02SAlexander Motin "SampleAfterValue": "200003", 8*18054d02SAlexander Motin "UMask": "0x1" 9*18054d02SAlexander Motin }, 10*18054d02SAlexander Motin { 11*18054d02SAlexander Motin "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.", 12*18054d02SAlexander Motin "Counter": "0,1", 13*18054d02SAlexander Motin "EventCode": "0xE6", 14*18054d02SAlexander Motin "EventName": "BACLEARS.COND", 15*18054d02SAlexander Motin "SampleAfterValue": "200003", 16*18054d02SAlexander Motin "UMask": "0x10" 17*18054d02SAlexander Motin }, 18*18054d02SAlexander Motin { 19*18054d02SAlexander Motin "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.", 20*18054d02SAlexander Motin "Counter": "0,1", 21*18054d02SAlexander Motin "EventCode": "0xE6", 22*18054d02SAlexander Motin "EventName": "BACLEARS.RETURN", 23*18054d02SAlexander Motin "SampleAfterValue": "200003", 24*18054d02SAlexander Motin "UMask": "0x8" 25*18054d02SAlexander Motin }, 26*18054d02SAlexander Motin { 27*18054d02SAlexander Motin "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.", 28*18054d02SAlexander Motin "Counter": "0,1", 29*18054d02SAlexander Motin "EventCode": "0x80", 30959826caSMatt Macy "EventName": "ICACHE.ACCESSES", 31959826caSMatt Macy "SampleAfterValue": "200003", 32*18054d02SAlexander Motin "UMask": "0x3" 33959826caSMatt Macy }, 34959826caSMatt Macy { 35*18054d02SAlexander Motin "BriefDescription": "Counts all instruction fetches that hit the instruction cache.", 36959826caSMatt Macy "Counter": "0,1", 37*18054d02SAlexander Motin "EventCode": "0x80", 38959826caSMatt Macy "EventName": "ICACHE.HIT", 39959826caSMatt Macy "SampleAfterValue": "200003", 40*18054d02SAlexander Motin "UMask": "0x1" 41959826caSMatt Macy }, 42959826caSMatt Macy { 43*18054d02SAlexander Motin "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", 44959826caSMatt Macy "Counter": "0,1", 45*18054d02SAlexander Motin "EventCode": "0x80", 46959826caSMatt Macy "EventName": "ICACHE.MISSES", 47959826caSMatt Macy "SampleAfterValue": "200003", 48*18054d02SAlexander Motin "UMask": "0x2" 49959826caSMatt Macy }, 50959826caSMatt Macy { 51*18054d02SAlexander Motin "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.", 52959826caSMatt Macy "Counter": "0,1", 53*18054d02SAlexander Motin "EventCode": "0xE7", 54959826caSMatt Macy "EventName": "MS_DECODED.MS_ENTRY", 55959826caSMatt Macy "SampleAfterValue": "200003", 56*18054d02SAlexander Motin "UMask": "0x1" 57959826caSMatt Macy } 58959826caSMatt Macy]