1[ 2 { 3 "EventCode": "0x17", 4 "Counter": "0,1,2,3", 5 "UMask": "0x1", 6 "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 7 "SampleAfterValue": "2000003", 8 "BriefDescription": "Valid instructions written to IQ per cycle.", 9 "CounterHTOff": "0,1,2,3,4,5,6,7" 10 }, 11 { 12 "EventCode": "0x5C", 13 "Counter": "0,1,2,3", 14 "UMask": "0x1", 15 "EventName": "CPL_CYCLES.RING0", 16 "SampleAfterValue": "2000003", 17 "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 18 "CounterHTOff": "0,1,2,3,4,5,6,7" 19 }, 20 { 21 "EventCode": "0x5C", 22 "Counter": "0,1,2,3", 23 "UMask": "0x1", 24 "EdgeDetect": "1", 25 "EventName": "CPL_CYCLES.RING0_TRANS", 26 "SampleAfterValue": "100007", 27 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 28 "CounterMask": "1", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "EventCode": "0x5C", 33 "Counter": "0,1,2,3", 34 "UMask": "0x2", 35 "EventName": "CPL_CYCLES.RING123", 36 "SampleAfterValue": "2000003", 37 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 38 "CounterHTOff": "0,1,2,3,4,5,6,7" 39 }, 40 { 41 "EventCode": "0x4E", 42 "Counter": "0,1,2,3", 43 "UMask": "0x2", 44 "EventName": "HW_PRE_REQ.DL1_MISS", 45 "SampleAfterValue": "2000003", 46 "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 47 "CounterHTOff": "0,1,2,3,4,5,6,7" 48 }, 49 { 50 "EventCode": "0x63", 51 "Counter": "0,1,2,3", 52 "UMask": "0x1", 53 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 54 "SampleAfterValue": "2000003", 55 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 56 "CounterHTOff": "0,1,2,3,4,5,6,7" 57 } 58]