1[ 2 { 3 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", 4 "EventCode": "0xC3", 5 "Counter": "0,1,2,3", 6 "UMask": "0x2", 7 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 8 "SampleAfterValue": "100003", 9 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PEBS": "2", 14 "EventCode": "0xCD", 15 "MSRValue": "0x4", 16 "Counter": "3", 17 "UMask": "0x1", 18 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 19 "MSRIndex": "0x3F6", 20 "SampleAfterValue": "100003", 21 "BriefDescription": "Loads with latency value being above 4 .", 22 "TakenAlone": "1", 23 "CounterHTOff": "3" 24 }, 25 { 26 "PEBS": "2", 27 "EventCode": "0xCD", 28 "MSRValue": "0x8", 29 "Counter": "3", 30 "UMask": "0x1", 31 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 32 "MSRIndex": "0x3F6", 33 "SampleAfterValue": "50021", 34 "BriefDescription": "Loads with latency value being above 8.", 35 "TakenAlone": "1", 36 "CounterHTOff": "3" 37 }, 38 { 39 "PEBS": "2", 40 "EventCode": "0xCD", 41 "MSRValue": "0x10", 42 "Counter": "3", 43 "UMask": "0x1", 44 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 45 "MSRIndex": "0x3F6", 46 "SampleAfterValue": "20011", 47 "BriefDescription": "Loads with latency value being above 16.", 48 "TakenAlone": "1", 49 "CounterHTOff": "3" 50 }, 51 { 52 "PEBS": "2", 53 "EventCode": "0xCD", 54 "MSRValue": "0x20", 55 "Counter": "3", 56 "UMask": "0x1", 57 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 58 "MSRIndex": "0x3F6", 59 "SampleAfterValue": "100007", 60 "BriefDescription": "Loads with latency value being above 32.", 61 "TakenAlone": "1", 62 "CounterHTOff": "3" 63 }, 64 { 65 "PEBS": "2", 66 "EventCode": "0xCD", 67 "MSRValue": "0x40", 68 "Counter": "3", 69 "UMask": "0x1", 70 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 71 "MSRIndex": "0x3F6", 72 "SampleAfterValue": "2003", 73 "BriefDescription": "Loads with latency value being above 64.", 74 "TakenAlone": "1", 75 "CounterHTOff": "3" 76 }, 77 { 78 "PEBS": "2", 79 "EventCode": "0xCD", 80 "MSRValue": "0x80", 81 "Counter": "3", 82 "UMask": "0x1", 83 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 84 "MSRIndex": "0x3F6", 85 "SampleAfterValue": "1009", 86 "BriefDescription": "Loads with latency value being above 128.", 87 "TakenAlone": "1", 88 "CounterHTOff": "3" 89 }, 90 { 91 "PEBS": "2", 92 "EventCode": "0xCD", 93 "MSRValue": "0x100", 94 "Counter": "3", 95 "UMask": "0x1", 96 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 97 "MSRIndex": "0x3F6", 98 "SampleAfterValue": "503", 99 "BriefDescription": "Loads with latency value being above 256.", 100 "TakenAlone": "1", 101 "CounterHTOff": "3" 102 }, 103 { 104 "PEBS": "2", 105 "EventCode": "0xCD", 106 "MSRValue": "0x200", 107 "Counter": "3", 108 "UMask": "0x1", 109 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 110 "MSRIndex": "0x3F6", 111 "SampleAfterValue": "101", 112 "BriefDescription": "Loads with latency value being above 512.", 113 "TakenAlone": "1", 114 "CounterHTOff": "3" 115 }, 116 { 117 "PEBS": "2", 118 "EventCode": "0xCD", 119 "Counter": "3", 120 "UMask": "0x2", 121 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 122 "SampleAfterValue": "2000003", 123 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", 124 "PRECISE_STORE": "1", 125 "TakenAlone": "1", 126 "CounterHTOff": "3" 127 }, 128 { 129 "EventCode": "0x05", 130 "Counter": "0,1,2,3", 131 "UMask": "0x1", 132 "EventName": "MISALIGN_MEM_REF.LOADS", 133 "SampleAfterValue": "2000003", 134 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", 135 "CounterHTOff": "0,1,2,3,4,5,6,7" 136 }, 137 { 138 "EventCode": "0x05", 139 "Counter": "0,1,2,3", 140 "UMask": "0x2", 141 "EventName": "MISALIGN_MEM_REF.STORES", 142 "SampleAfterValue": "2000003", 143 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", 144 "CounterHTOff": "0,1,2,3,4,5,6,7" 145 }, 146 { 147 "EventCode": "0xB7, 0xBB", 148 "MSRValue": "0x3fffc20004", 149 "Counter": "0,1,2,3", 150 "UMask": "0x1", 151 "Offcore": "1", 152 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", 153 "MSRIndex": "0x1a6,0x1a7", 154 "SampleAfterValue": "100003", 155 "BriefDescription": "Counts all demand code reads that miss the LLC", 156 "CounterHTOff": "0,1,2,3" 157 }, 158 { 159 "EventCode": "0xB7, 0xBB", 160 "MSRValue": "0x600400004", 161 "Counter": "0,1,2,3", 162 "UMask": "0x1", 163 "Offcore": "1", 164 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", 165 "MSRIndex": "0x1a6,0x1a7", 166 "SampleAfterValue": "100003", 167 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", 168 "CounterHTOff": "0,1,2,3" 169 }, 170 { 171 "EventCode": "0xB7, 0xBB", 172 "MSRValue": "0x67f800004", 173 "Counter": "0,1,2,3", 174 "UMask": "0x1", 175 "Offcore": "1", 176 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", 177 "MSRIndex": "0x1a6,0x1a7", 178 "SampleAfterValue": "100003", 179 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", 180 "CounterHTOff": "0,1,2,3" 181 }, 182 { 183 "EventCode": "0xB7, 0xBB", 184 "MSRValue": "0x87f820004", 185 "Counter": "0,1,2,3", 186 "UMask": "0x1", 187 "Offcore": "1", 188 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", 189 "MSRIndex": "0x1a6,0x1a7", 190 "SampleAfterValue": "100003", 191 "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", 192 "CounterHTOff": "0,1,2,3" 193 }, 194 { 195 "EventCode": "0xB7, 0xBB", 196 "MSRValue": "0x107fc00004", 197 "Counter": "0,1,2,3", 198 "UMask": "0x1", 199 "Offcore": "1", 200 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", 201 "MSRIndex": "0x1a6,0x1a7", 202 "SampleAfterValue": "100003", 203 "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", 204 "CounterHTOff": "0,1,2,3" 205 }, 206 { 207 "EventCode": "0xB7, 0xBB", 208 "MSRValue": "0x67fc00001", 209 "Counter": "0,1,2,3", 210 "UMask": "0x1", 211 "Offcore": "1", 212 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", 213 "MSRIndex": "0x1a6,0x1a7", 214 "SampleAfterValue": "100003", 215 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", 216 "CounterHTOff": "0,1,2,3" 217 }, 218 { 219 "EventCode": "0xB7, 0xBB", 220 "MSRValue": "0x3fffc20001", 221 "Counter": "0,1,2,3", 222 "UMask": "0x1", 223 "Offcore": "1", 224 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", 225 "MSRIndex": "0x1a6,0x1a7", 226 "SampleAfterValue": "100003", 227 "BriefDescription": "Counts demand data reads that miss in the LLC", 228 "CounterHTOff": "0,1,2,3" 229 }, 230 { 231 "EventCode": "0xB7, 0xBB", 232 "MSRValue": "0x600400001", 233 "Counter": "0,1,2,3", 234 "UMask": "0x1", 235 "Offcore": "1", 236 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", 237 "MSRIndex": "0x1a6,0x1a7", 238 "SampleAfterValue": "100003", 239 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", 240 "CounterHTOff": "0,1,2,3" 241 }, 242 { 243 "EventCode": "0xB7, 0xBB", 244 "MSRValue": "0x67f800001", 245 "Counter": "0,1,2,3", 246 "UMask": "0x1", 247 "Offcore": "1", 248 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", 249 "MSRIndex": "0x1a6,0x1a7", 250 "SampleAfterValue": "100003", 251 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", 252 "CounterHTOff": "0,1,2,3" 253 }, 254 { 255 "EventCode": "0xB7, 0xBB", 256 "MSRValue": "0x87f820001", 257 "Counter": "0,1,2,3", 258 "UMask": "0x1", 259 "Offcore": "1", 260 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 261 "MSRIndex": "0x1a6,0x1a7", 262 "SampleAfterValue": "100003", 263 "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", 264 "CounterHTOff": "0,1,2,3" 265 }, 266 { 267 "EventCode": "0xB7, 0xBB", 268 "MSRValue": "0x107fc00001", 269 "Counter": "0,1,2,3", 270 "UMask": "0x1", 271 "Offcore": "1", 272 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", 273 "MSRIndex": "0x1a6,0x1a7", 274 "SampleAfterValue": "100003", 275 "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", 276 "CounterHTOff": "0,1,2,3" 277 }, 278 { 279 "EventCode": "0xB7, 0xBB", 280 "MSRValue": "0x3fffc20040", 281 "Counter": "0,1,2,3", 282 "UMask": "0x1", 283 "Offcore": "1", 284 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", 285 "MSRIndex": "0x1a6,0x1a7", 286 "SampleAfterValue": "100003", 287 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", 288 "CounterHTOff": "0,1,2,3" 289 }, 290 { 291 "EventCode": "0xB7, 0xBB", 292 "MSRValue": "0x67fc00010", 293 "Counter": "0,1,2,3", 294 "UMask": "0x1", 295 "Offcore": "1", 296 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", 297 "MSRIndex": "0x1a6,0x1a7", 298 "SampleAfterValue": "100003", 299 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", 300 "CounterHTOff": "0,1,2,3" 301 }, 302 { 303 "EventCode": "0xB7, 0xBB", 304 "MSRValue": "0x3fffc20010", 305 "Counter": "0,1,2,3", 306 "UMask": "0x1", 307 "Offcore": "1", 308 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", 309 "MSRIndex": "0x1a6,0x1a7", 310 "SampleAfterValue": "100003", 311 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", 312 "CounterHTOff": "0,1,2,3" 313 }, 314 { 315 "EventCode": "0xB7, 0xBB", 316 "MSRValue": "0x600400010", 317 "Counter": "0,1,2,3", 318 "UMask": "0x1", 319 "Offcore": "1", 320 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", 321 "MSRIndex": "0x1a6,0x1a7", 322 "SampleAfterValue": "100003", 323 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", 324 "CounterHTOff": "0,1,2,3" 325 }, 326 { 327 "EventCode": "0xB7, 0xBB", 328 "MSRValue": "0x67f800010", 329 "Counter": "0,1,2,3", 330 "UMask": "0x1", 331 "Offcore": "1", 332 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", 333 "MSRIndex": "0x1a6,0x1a7", 334 "SampleAfterValue": "100003", 335 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", 336 "CounterHTOff": "0,1,2,3" 337 }, 338 { 339 "EventCode": "0xB7, 0xBB", 340 "MSRValue": "0x87f820010", 341 "Counter": "0,1,2,3", 342 "UMask": "0x1", 343 "Offcore": "1", 344 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 345 "MSRIndex": "0x1a6,0x1a7", 346 "SampleAfterValue": "100003", 347 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", 348 "CounterHTOff": "0,1,2,3" 349 }, 350 { 351 "EventCode": "0xB7, 0xBB", 352 "MSRValue": "0x107fc00010", 353 "Counter": "0,1,2,3", 354 "UMask": "0x1", 355 "Offcore": "1", 356 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", 357 "MSRIndex": "0x1a6,0x1a7", 358 "SampleAfterValue": "100003", 359 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", 360 "CounterHTOff": "0,1,2,3" 361 }, 362 { 363 "EventCode": "0xB7, 0xBB", 364 "MSRValue": "0x3fffc20200", 365 "Counter": "0,1,2,3", 366 "UMask": "0x1", 367 "Offcore": "1", 368 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 369 "MSRIndex": "0x1a6,0x1a7", 370 "SampleAfterValue": "100003", 371 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", 372 "CounterHTOff": "0,1,2,3" 373 }, 374 { 375 "EventCode": "0xB7, 0xBB", 376 "MSRValue": "0x3fffc20080", 377 "Counter": "0,1,2,3", 378 "UMask": "0x1", 379 "Offcore": "1", 380 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", 381 "MSRIndex": "0x1a6,0x1a7", 382 "SampleAfterValue": "100003", 383 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 384 "CounterHTOff": "0,1,2,3" 385 }, 386 { 387 "EventCode": "0xB7, 0xBB", 388 "MSRValue": "0x600400077", 389 "Counter": "0,1,2,3", 390 "UMask": "0x1", 391 "Offcore": "1", 392 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", 393 "MSRIndex": "0x1a6,0x1a7", 394 "SampleAfterValue": "100003", 395 "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", 396 "CounterHTOff": "0,1,2,3" 397 }, 398 { 399 "EventCode": "0xB7, 0xBB", 400 "MSRValue": "0x3FFFC20077", 401 "Counter": "0,1,2,3", 402 "UMask": "0x1", 403 "Offcore": "1", 404 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", 405 "MSRIndex": "0x1a6,0x1a7", 406 "SampleAfterValue": "100003", 407 "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", 408 "CounterHTOff": "0,1,2,3" 409 }, 410 { 411 "EventCode": "0xB7, 0xBB", 412 "MSRValue": "0x187FC20077", 413 "Counter": "0,1,2,3", 414 "UMask": "0x1", 415 "Offcore": "1", 416 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", 417 "MSRIndex": "0x1a6,0x1a7", 418 "SampleAfterValue": "100003", 419 "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", 420 "CounterHTOff": "0,1,2,3" 421 } 422]