1[ 2 { 3 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", 4 "EventCode": "0x08", 5 "Counter": "0,1,2,3", 6 "UMask": "0x81", 7 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 8 "SampleAfterValue": "100003", 9 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "EventCode": "0x08", 14 "Counter": "0,1,2,3", 15 "UMask": "0x82", 16 "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", 17 "SampleAfterValue": "100003", 18 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 19 "CounterHTOff": "0,1,2,3,4,5,6,7" 20 }, 21 { 22 "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", 23 "EventCode": "0x08", 24 "Counter": "0,1,2,3", 25 "UMask": "0x82", 26 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 27 "SampleAfterValue": "100003", 28 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "EventCode": "0x08", 33 "Counter": "0,1,2,3", 34 "UMask": "0x84", 35 "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", 36 "SampleAfterValue": "2000003", 37 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 38 "CounterHTOff": "0,1,2,3,4,5,6,7" 39 }, 40 { 41 "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", 42 "EventCode": "0x08", 43 "Counter": "0,1,2,3", 44 "UMask": "0x84", 45 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 46 "SampleAfterValue": "2000003", 47 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 48 "CounterHTOff": "0,1,2,3,4,5,6,7" 49 }, 50 { 51 "EventCode": "0x08", 52 "Counter": "0,1,2,3", 53 "UMask": "0x88", 54 "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", 55 "SampleAfterValue": "100003", 56 "BriefDescription": "Page walk for a large page completed for Demand load.", 57 "CounterHTOff": "0,1,2,3,4,5,6,7" 58 }, 59 { 60 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 61 "EventCode": "0x49", 62 "Counter": "0,1,2,3", 63 "UMask": "0x1", 64 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 65 "SampleAfterValue": "100003", 66 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 67 "CounterHTOff": "0,1,2,3,4,5,6,7" 68 }, 69 { 70 "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", 71 "EventCode": "0x49", 72 "Counter": "0,1,2,3", 73 "UMask": "0x2", 74 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 75 "SampleAfterValue": "100003", 76 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 77 "CounterHTOff": "0,1,2,3,4,5,6,7" 78 }, 79 { 80 "PublicDescription": "Cycles PMH is busy with this walk.", 81 "EventCode": "0x49", 82 "Counter": "0,1,2,3", 83 "UMask": "0x4", 84 "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 85 "SampleAfterValue": "2000003", 86 "BriefDescription": "Cycles when PMH is busy with page walks", 87 "CounterHTOff": "0,1,2,3,4,5,6,7" 88 }, 89 { 90 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 91 "EventCode": "0x49", 92 "Counter": "0,1,2,3", 93 "UMask": "0x10", 94 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 95 "SampleAfterValue": "100003", 96 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 97 "CounterHTOff": "0,1,2,3,4,5,6,7" 98 }, 99 { 100 "EventCode": "0x4F", 101 "Counter": "0,1,2,3", 102 "UMask": "0x10", 103 "EventName": "EPT.WALK_CYCLES", 104 "SampleAfterValue": "2000003", 105 "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", 106 "CounterHTOff": "0,1,2,3,4,5,6,7" 107 }, 108 { 109 "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", 110 "EventCode": "0x5F", 111 "Counter": "0,1,2,3", 112 "UMask": "0x4", 113 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 114 "SampleAfterValue": "100003", 115 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 116 "CounterHTOff": "0,1,2,3,4,5,6,7" 117 }, 118 { 119 "PublicDescription": "Misses in all ITLB levels that cause page walks.", 120 "EventCode": "0x85", 121 "Counter": "0,1,2,3", 122 "UMask": "0x1", 123 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 124 "SampleAfterValue": "100003", 125 "BriefDescription": "Misses at all ITLB levels that cause page walks", 126 "CounterHTOff": "0,1,2,3,4,5,6,7" 127 }, 128 { 129 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", 130 "EventCode": "0x85", 131 "Counter": "0,1,2,3", 132 "UMask": "0x2", 133 "EventName": "ITLB_MISSES.WALK_COMPLETED", 134 "SampleAfterValue": "100003", 135 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 136 "CounterHTOff": "0,1,2,3,4,5,6,7" 137 }, 138 { 139 "PublicDescription": "Cycle PMH is busy with a walk.", 140 "EventCode": "0x85", 141 "Counter": "0,1,2,3", 142 "UMask": "0x4", 143 "EventName": "ITLB_MISSES.WALK_DURATION", 144 "SampleAfterValue": "2000003", 145 "BriefDescription": "Cycles when PMH is busy with page walks", 146 "CounterHTOff": "0,1,2,3,4,5,6,7" 147 }, 148 { 149 "PublicDescription": "Number of cache load STLB hits. No page walk.", 150 "EventCode": "0x85", 151 "Counter": "0,1,2,3", 152 "UMask": "0x10", 153 "EventName": "ITLB_MISSES.STLB_HIT", 154 "SampleAfterValue": "100003", 155 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 156 "CounterHTOff": "0,1,2,3,4,5,6,7" 157 }, 158 { 159 "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", 160 "EventCode": "0x85", 161 "Counter": "0,1,2,3", 162 "UMask": "0x80", 163 "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", 164 "SampleAfterValue": "100003", 165 "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", 166 "CounterHTOff": "0,1,2,3,4,5,6,7" 167 }, 168 { 169 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 170 "EventCode": "0xAE", 171 "Counter": "0,1,2,3", 172 "UMask": "0x1", 173 "EventName": "ITLB.ITLB_FLUSH", 174 "SampleAfterValue": "100007", 175 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 176 "CounterHTOff": "0,1,2,3,4,5,6,7" 177 }, 178 { 179 "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 180 "EventCode": "0xBD", 181 "Counter": "0,1,2,3", 182 "UMask": "0x1", 183 "EventName": "TLB_FLUSH.DTLB_THREAD", 184 "SampleAfterValue": "100007", 185 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 186 "CounterHTOff": "0,1,2,3,4,5,6,7" 187 }, 188 { 189 "PublicDescription": "Count number of STLB flush attempts.", 190 "EventCode": "0xBD", 191 "Counter": "0,1,2,3", 192 "UMask": "0x20", 193 "EventName": "TLB_FLUSH.STLB_ANY", 194 "SampleAfterValue": "100007", 195 "BriefDescription": "STLB flush attempts", 196 "CounterHTOff": "0,1,2,3,4,5,6,7" 197 } 198]