1[ 2 { 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 4 "EventCode": "0x24", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 8 "SampleAfterValue": "200003", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 14 "EventCode": "0x24", 15 "Counter": "0,1,2,3", 16 "UMask": "0x3", 17 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 18 "SampleAfterValue": "200003", 19 "BriefDescription": "Demand Data Read requests", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "RFO requests that hit L2 cache.", 24 "EventCode": "0x24", 25 "Counter": "0,1,2,3", 26 "UMask": "0x4", 27 "EventName": "L2_RQSTS.RFO_HIT", 28 "SampleAfterValue": "200003", 29 "BriefDescription": "RFO requests that hit L2 cache", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 }, 32 { 33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 34 "EventCode": "0x24", 35 "Counter": "0,1,2,3", 36 "UMask": "0x8", 37 "EventName": "L2_RQSTS.RFO_MISS", 38 "SampleAfterValue": "200003", 39 "BriefDescription": "RFO requests that miss L2 cache", 40 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 }, 42 { 43 "PublicDescription": "Counts all L2 store RFO requests.", 44 "EventCode": "0x24", 45 "Counter": "0,1,2,3", 46 "UMask": "0xc", 47 "EventName": "L2_RQSTS.ALL_RFO", 48 "SampleAfterValue": "200003", 49 "BriefDescription": "RFO requests to L2 cache", 50 "CounterHTOff": "0,1,2,3,4,5,6,7" 51 }, 52 { 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 54 "EventCode": "0x24", 55 "Counter": "0,1,2,3", 56 "UMask": "0x10", 57 "EventName": "L2_RQSTS.CODE_RD_HIT", 58 "SampleAfterValue": "200003", 59 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 60 "CounterHTOff": "0,1,2,3,4,5,6,7" 61 }, 62 { 63 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 64 "EventCode": "0x24", 65 "Counter": "0,1,2,3", 66 "UMask": "0x20", 67 "EventName": "L2_RQSTS.CODE_RD_MISS", 68 "SampleAfterValue": "200003", 69 "BriefDescription": "L2 cache misses when fetching instructions", 70 "CounterHTOff": "0,1,2,3,4,5,6,7" 71 }, 72 { 73 "PublicDescription": "Counts all L2 code requests.", 74 "EventCode": "0x24", 75 "Counter": "0,1,2,3", 76 "UMask": "0x30", 77 "EventName": "L2_RQSTS.ALL_CODE_RD", 78 "SampleAfterValue": "200003", 79 "BriefDescription": "L2 code requests", 80 "CounterHTOff": "0,1,2,3,4,5,6,7" 81 }, 82 { 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 84 "EventCode": "0x24", 85 "Counter": "0,1,2,3", 86 "UMask": "0x40", 87 "EventName": "L2_RQSTS.PF_HIT", 88 "SampleAfterValue": "200003", 89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 90 "CounterHTOff": "0,1,2,3,4,5,6,7" 91 }, 92 { 93 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 94 "EventCode": "0x24", 95 "Counter": "0,1,2,3", 96 "UMask": "0x80", 97 "EventName": "L2_RQSTS.PF_MISS", 98 "SampleAfterValue": "200003", 99 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", 100 "CounterHTOff": "0,1,2,3,4,5,6,7" 101 }, 102 { 103 "PublicDescription": "Counts all L2 HW prefetcher requests.", 104 "EventCode": "0x24", 105 "Counter": "0,1,2,3", 106 "UMask": "0xc0", 107 "EventName": "L2_RQSTS.ALL_PF", 108 "SampleAfterValue": "200003", 109 "BriefDescription": "Requests from L2 hardware prefetchers", 110 "CounterHTOff": "0,1,2,3,4,5,6,7" 111 }, 112 { 113 "PublicDescription": "RFOs that miss cache lines.", 114 "EventCode": "0x27", 115 "Counter": "0,1,2,3", 116 "UMask": "0x1", 117 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 118 "SampleAfterValue": "200003", 119 "BriefDescription": "RFOs that miss cache lines", 120 "CounterHTOff": "0,1,2,3,4,5,6,7" 121 }, 122 { 123 "PublicDescription": "RFOs that hit cache lines in M state.", 124 "EventCode": "0x27", 125 "Counter": "0,1,2,3", 126 "UMask": "0x8", 127 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 128 "SampleAfterValue": "200003", 129 "BriefDescription": "RFOs that hit cache lines in M state", 130 "CounterHTOff": "0,1,2,3,4,5,6,7" 131 }, 132 { 133 "PublicDescription": "RFOs that access cache lines in any state.", 134 "EventCode": "0x27", 135 "Counter": "0,1,2,3", 136 "UMask": "0xf", 137 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 138 "SampleAfterValue": "200003", 139 "BriefDescription": "RFOs that access cache lines in any state", 140 "CounterHTOff": "0,1,2,3,4,5,6,7" 141 }, 142 { 143 "PublicDescription": "Not rejected writebacks that missed LLC.", 144 "EventCode": "0x28", 145 "Counter": "0,1,2,3", 146 "UMask": "0x1", 147 "EventName": "L2_L1D_WB_RQSTS.MISS", 148 "SampleAfterValue": "200003", 149 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", 150 "CounterHTOff": "0,1,2,3,4,5,6,7" 151 }, 152 { 153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 154 "EventCode": "0x28", 155 "Counter": "0,1,2,3", 156 "UMask": "0x4", 157 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 158 "SampleAfterValue": "200003", 159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 160 "CounterHTOff": "0,1,2,3,4,5,6,7" 161 }, 162 { 163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 164 "EventCode": "0x28", 165 "Counter": "0,1,2,3", 166 "UMask": "0x8", 167 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 168 "SampleAfterValue": "200003", 169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 170 "CounterHTOff": "0,1,2,3,4,5,6,7" 171 }, 172 { 173 "EventCode": "0x28", 174 "Counter": "0,1,2,3", 175 "UMask": "0xf", 176 "EventName": "L2_L1D_WB_RQSTS.ALL", 177 "SampleAfterValue": "200003", 178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 179 "CounterHTOff": "0,1,2,3,4,5,6,7" 180 }, 181 { 182 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 183 "EventCode": "0x2E", 184 "Counter": "0,1,2,3", 185 "UMask": "0x41", 186 "EventName": "LONGEST_LAT_CACHE.MISS", 187 "SampleAfterValue": "100003", 188 "BriefDescription": "Core-originated cacheable demand requests missed LLC", 189 "CounterHTOff": "0,1,2,3,4,5,6,7" 190 }, 191 { 192 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 193 "EventCode": "0x2E", 194 "Counter": "0,1,2,3", 195 "UMask": "0x4f", 196 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 197 "SampleAfterValue": "100003", 198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", 199 "CounterHTOff": "0,1,2,3,4,5,6,7" 200 }, 201 { 202 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 203 "EventCode": "0x48", 204 "Counter": "2", 205 "UMask": "0x1", 206 "EventName": "L1D_PEND_MISS.PENDING", 207 "SampleAfterValue": "2000003", 208 "BriefDescription": "L1D miss oustandings duration in cycles", 209 "CounterHTOff": "2" 210 }, 211 { 212 "EventCode": "0x48", 213 "Counter": "2", 214 "UMask": "0x1", 215 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 216 "SampleAfterValue": "2000003", 217 "BriefDescription": "Cycles with L1D load Misses outstanding.", 218 "CounterMask": "1", 219 "CounterHTOff": "2" 220 }, 221 { 222 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 223 "EventCode": "0x48", 224 "Counter": "2", 225 "UMask": "0x1", 226 "AnyThread": "1", 227 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 228 "SampleAfterValue": "2000003", 229 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 230 "CounterMask": "1", 231 "CounterHTOff": "2" 232 }, 233 { 234 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 235 "EventCode": "0x48", 236 "Counter": "0,1,2,3", 237 "UMask": "0x2", 238 "EventName": "L1D_PEND_MISS.FB_FULL", 239 "SampleAfterValue": "2000003", 240 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", 241 "CounterMask": "1", 242 "CounterHTOff": "0,1,2,3,4,5,6,7" 243 }, 244 { 245 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 246 "EventCode": "0x51", 247 "Counter": "0,1,2,3", 248 "UMask": "0x1", 249 "EventName": "L1D.REPLACEMENT", 250 "SampleAfterValue": "2000003", 251 "BriefDescription": "L1D data line replacements", 252 "CounterHTOff": "0,1,2,3,4,5,6,7" 253 }, 254 { 255 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 256 "EventCode": "0x60", 257 "Counter": "0,1,2,3", 258 "UMask": "0x1", 259 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 260 "SampleAfterValue": "2000003", 261 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 262 "CounterHTOff": "0,1,2,3,4,5,6,7" 263 }, 264 { 265 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 266 "EventCode": "0x60", 267 "Counter": "0,1,2,3", 268 "UMask": "0x1", 269 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 270 "SampleAfterValue": "2000003", 271 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 272 "CounterMask": "1", 273 "CounterHTOff": "0,1,2,3,4,5,6,7" 274 }, 275 { 276 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 277 "EventCode": "0x60", 278 "Counter": "0,1,2,3", 279 "UMask": "0x1", 280 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 281 "SampleAfterValue": "2000003", 282 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", 283 "CounterMask": "6", 284 "CounterHTOff": "0,1,2,3,4,5,6,7" 285 }, 286 { 287 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 288 "EventCode": "0x60", 289 "Counter": "0,1,2,3", 290 "UMask": "0x2", 291 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 292 "SampleAfterValue": "2000003", 293 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 294 "CounterHTOff": "0,1,2,3,4,5,6,7" 295 }, 296 { 297 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 298 "EventCode": "0x60", 299 "Counter": "0,1,2,3", 300 "UMask": "0x2", 301 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 302 "SampleAfterValue": "2000003", 303 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 304 "CounterMask": "1", 305 "CounterHTOff": "0,1,2,3,4,5,6,7" 306 }, 307 { 308 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 309 "EventCode": "0x60", 310 "Counter": "0,1,2,3", 311 "UMask": "0x4", 312 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 313 "SampleAfterValue": "2000003", 314 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 315 "CounterHTOff": "0,1,2,3,4,5,6,7" 316 }, 317 { 318 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 319 "EventCode": "0x60", 320 "Counter": "0,1,2,3", 321 "UMask": "0x4", 322 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 323 "SampleAfterValue": "2000003", 324 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 325 "CounterMask": "1", 326 "CounterHTOff": "0,1,2,3,4,5,6,7" 327 }, 328 { 329 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 330 "EventCode": "0x60", 331 "Counter": "0,1,2,3", 332 "UMask": "0x8", 333 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 334 "SampleAfterValue": "2000003", 335 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 336 "CounterHTOff": "0,1,2,3,4,5,6,7" 337 }, 338 { 339 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 340 "EventCode": "0x60", 341 "Counter": "0,1,2,3", 342 "UMask": "0x8", 343 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 344 "SampleAfterValue": "2000003", 345 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 346 "CounterMask": "1", 347 "CounterHTOff": "0,1,2,3,4,5,6,7" 348 }, 349 { 350 "PublicDescription": "Cycles in which the L1D is locked.", 351 "EventCode": "0x63", 352 "Counter": "0,1,2,3", 353 "UMask": "0x2", 354 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 355 "SampleAfterValue": "2000003", 356 "BriefDescription": "Cycles when L1D is locked", 357 "CounterHTOff": "0,1,2,3,4,5,6,7" 358 }, 359 { 360 "PublicDescription": "Demand data read requests sent to uncore.", 361 "EventCode": "0xB0", 362 "Counter": "0,1,2,3", 363 "UMask": "0x1", 364 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 365 "SampleAfterValue": "100003", 366 "BriefDescription": "Demand Data Read requests sent to uncore", 367 "CounterHTOff": "0,1,2,3,4,5,6,7" 368 }, 369 { 370 "PublicDescription": "Demand code read requests sent to uncore.", 371 "EventCode": "0xB0", 372 "Counter": "0,1,2,3", 373 "UMask": "0x2", 374 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 375 "SampleAfterValue": "100003", 376 "BriefDescription": "Cacheable and noncachaeble code read requests", 377 "CounterHTOff": "0,1,2,3,4,5,6,7" 378 }, 379 { 380 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 381 "EventCode": "0xB0", 382 "Counter": "0,1,2,3", 383 "UMask": "0x4", 384 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 385 "SampleAfterValue": "100003", 386 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 387 "CounterHTOff": "0,1,2,3,4,5,6,7" 388 }, 389 { 390 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 391 "EventCode": "0xB0", 392 "Counter": "0,1,2,3", 393 "UMask": "0x8", 394 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 395 "SampleAfterValue": "100003", 396 "BriefDescription": "Demand and prefetch data reads", 397 "CounterHTOff": "0,1,2,3,4,5,6,7" 398 }, 399 { 400 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", 401 "EventCode": "0xB2", 402 "Counter": "0,1,2,3", 403 "UMask": "0x1", 404 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 405 "SampleAfterValue": "2000003", 406 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", 407 "CounterHTOff": "0,1,2,3,4,5,6,7" 408 }, 409 { 410 "PEBS": "1", 411 "EventCode": "0xD0", 412 "Counter": "0,1,2,3", 413 "UMask": "0x11", 414 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 415 "SampleAfterValue": "100003", 416 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", 417 "CounterHTOff": "0,1,2,3" 418 }, 419 { 420 "PEBS": "1", 421 "EventCode": "0xD0", 422 "Counter": "0,1,2,3", 423 "UMask": "0x12", 424 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 425 "SampleAfterValue": "100003", 426 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", 427 "CounterHTOff": "0,1,2,3" 428 }, 429 { 430 "PEBS": "1", 431 "EventCode": "0xD0", 432 "Counter": "0,1,2,3", 433 "UMask": "0x21", 434 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 435 "SampleAfterValue": "100007", 436 "BriefDescription": "Retired load uops with locked access. (Precise Event)", 437 "CounterHTOff": "0,1,2,3" 438 }, 439 { 440 "PEBS": "1", 441 "EventCode": "0xD0", 442 "Counter": "0,1,2,3", 443 "UMask": "0x41", 444 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 445 "SampleAfterValue": "100003", 446 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", 447 "CounterHTOff": "0,1,2,3" 448 }, 449 { 450 "PEBS": "1", 451 "EventCode": "0xD0", 452 "Counter": "0,1,2,3", 453 "UMask": "0x42", 454 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 455 "SampleAfterValue": "100003", 456 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", 457 "CounterHTOff": "0,1,2,3" 458 }, 459 { 460 "PEBS": "1", 461 "EventCode": "0xD0", 462 "Counter": "0,1,2,3", 463 "UMask": "0x81", 464 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 465 "SampleAfterValue": "2000003", 466 "BriefDescription": "All retired load uops. (Precise Event)", 467 "CounterHTOff": "0,1,2,3" 468 }, 469 { 470 "PEBS": "1", 471 "EventCode": "0xD0", 472 "Counter": "0,1,2,3", 473 "UMask": "0x82", 474 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 475 "SampleAfterValue": "2000003", 476 "BriefDescription": "All retired store uops. (Precise Event)", 477 "CounterHTOff": "0,1,2,3" 478 }, 479 { 480 "PEBS": "1", 481 "EventCode": "0xD1", 482 "Counter": "0,1,2,3", 483 "UMask": "0x1", 484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 485 "SampleAfterValue": "2000003", 486 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 487 "CounterHTOff": "0,1,2,3" 488 }, 489 { 490 "PEBS": "1", 491 "EventCode": "0xD1", 492 "Counter": "0,1,2,3", 493 "UMask": "0x2", 494 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 495 "SampleAfterValue": "100003", 496 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 497 "CounterHTOff": "0,1,2,3" 498 }, 499 { 500 "PEBS": "1", 501 "EventCode": "0xD1", 502 "Counter": "0,1,2,3", 503 "UMask": "0x4", 504 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 505 "SampleAfterValue": "50021", 506 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", 507 "CounterHTOff": "0,1,2,3" 508 }, 509 { 510 "PEBS": "1", 511 "EventCode": "0xD1", 512 "Counter": "0,1,2,3", 513 "UMask": "0x8", 514 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 515 "SampleAfterValue": "100003", 516 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", 517 "CounterHTOff": "0,1,2,3" 518 }, 519 { 520 "PEBS": "1", 521 "EventCode": "0xD1", 522 "Counter": "0,1,2,3", 523 "UMask": "0x10", 524 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 525 "SampleAfterValue": "50021", 526 "BriefDescription": "Retired load uops with L2 cache misses as data sources.", 527 "CounterHTOff": "0,1,2,3" 528 }, 529 { 530 "PEBS": "1", 531 "EventCode": "0xD1", 532 "Counter": "0,1,2,3", 533 "UMask": "0x20", 534 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 535 "SampleAfterValue": "100007", 536 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 537 "CounterHTOff": "0,1,2,3" 538 }, 539 { 540 "PEBS": "1", 541 "EventCode": "0xD1", 542 "Counter": "0,1,2,3", 543 "UMask": "0x40", 544 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 545 "SampleAfterValue": "100003", 546 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 547 "CounterHTOff": "0,1,2,3" 548 }, 549 { 550 "PEBS": "1", 551 "EventCode": "0xD2", 552 "Counter": "0,1,2,3", 553 "UMask": "0x1", 554 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 555 "SampleAfterValue": "20011", 556 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", 557 "CounterHTOff": "0,1,2,3" 558 }, 559 { 560 "PEBS": "1", 561 "EventCode": "0xD2", 562 "Counter": "0,1,2,3", 563 "UMask": "0x2", 564 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 565 "SampleAfterValue": "20011", 566 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", 567 "CounterHTOff": "0,1,2,3" 568 }, 569 { 570 "PEBS": "1", 571 "EventCode": "0xD2", 572 "Counter": "0,1,2,3", 573 "UMask": "0x4", 574 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 575 "SampleAfterValue": "20011", 576 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", 577 "CounterHTOff": "0,1,2,3" 578 }, 579 { 580 "PEBS": "1", 581 "EventCode": "0xD2", 582 "Counter": "0,1,2,3", 583 "UMask": "0x8", 584 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 585 "SampleAfterValue": "100003", 586 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", 587 "CounterHTOff": "0,1,2,3" 588 }, 589 { 590 "EventCode": "0xD3", 591 "Counter": "0,1,2,3", 592 "UMask": "0x3", 593 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 594 "SampleAfterValue": "100007", 595 "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", 596 "CounterHTOff": "0,1,2,3" 597 }, 598 { 599 "EventCode": "0xD3", 600 "Counter": "0,1,2,3", 601 "UMask": "0xc", 602 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", 603 "SampleAfterValue": "100007", 604 "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", 605 "CounterHTOff": "0,1,2,3" 606 }, 607 { 608 "EventCode": "0xD3", 609 "Counter": "0,1,2,3", 610 "UMask": "0x10", 611 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", 612 "SampleAfterValue": "100007", 613 "BriefDescription": "Remote cache HITM.", 614 "CounterHTOff": "0,1,2,3" 615 }, 616 { 617 "EventCode": "0xD3", 618 "Counter": "0,1,2,3", 619 "UMask": "0x20", 620 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", 621 "SampleAfterValue": "100007", 622 "BriefDescription": "Data forwarded from remote cache.", 623 "CounterHTOff": "0,1,2,3" 624 }, 625 { 626 "PublicDescription": "Demand Data Read requests that access L2 cache.", 627 "EventCode": "0xF0", 628 "Counter": "0,1,2,3", 629 "UMask": "0x1", 630 "EventName": "L2_TRANS.DEMAND_DATA_RD", 631 "SampleAfterValue": "200003", 632 "BriefDescription": "Demand Data Read requests that access L2 cache", 633 "CounterHTOff": "0,1,2,3,4,5,6,7" 634 }, 635 { 636 "PublicDescription": "RFO requests that access L2 cache.", 637 "EventCode": "0xF0", 638 "Counter": "0,1,2,3", 639 "UMask": "0x2", 640 "EventName": "L2_TRANS.RFO", 641 "SampleAfterValue": "200003", 642 "BriefDescription": "RFO requests that access L2 cache", 643 "CounterHTOff": "0,1,2,3,4,5,6,7" 644 }, 645 { 646 "PublicDescription": "L2 cache accesses when fetching instructions.", 647 "EventCode": "0xF0", 648 "Counter": "0,1,2,3", 649 "UMask": "0x4", 650 "EventName": "L2_TRANS.CODE_RD", 651 "SampleAfterValue": "200003", 652 "BriefDescription": "L2 cache accesses when fetching instructions", 653 "CounterHTOff": "0,1,2,3,4,5,6,7" 654 }, 655 { 656 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", 657 "EventCode": "0xF0", 658 "Counter": "0,1,2,3", 659 "UMask": "0x8", 660 "EventName": "L2_TRANS.ALL_PF", 661 "SampleAfterValue": "200003", 662 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", 663 "CounterHTOff": "0,1,2,3,4,5,6,7" 664 }, 665 { 666 "PublicDescription": "L1D writebacks that access L2 cache.", 667 "EventCode": "0xF0", 668 "Counter": "0,1,2,3", 669 "UMask": "0x10", 670 "EventName": "L2_TRANS.L1D_WB", 671 "SampleAfterValue": "200003", 672 "BriefDescription": "L1D writebacks that access L2 cache", 673 "CounterHTOff": "0,1,2,3,4,5,6,7" 674 }, 675 { 676 "PublicDescription": "L2 fill requests that access L2 cache.", 677 "EventCode": "0xF0", 678 "Counter": "0,1,2,3", 679 "UMask": "0x20", 680 "EventName": "L2_TRANS.L2_FILL", 681 "SampleAfterValue": "200003", 682 "BriefDescription": "L2 fill requests that access L2 cache", 683 "CounterHTOff": "0,1,2,3,4,5,6,7" 684 }, 685 { 686 "PublicDescription": "L2 writebacks that access L2 cache.", 687 "EventCode": "0xF0", 688 "Counter": "0,1,2,3", 689 "UMask": "0x40", 690 "EventName": "L2_TRANS.L2_WB", 691 "SampleAfterValue": "200003", 692 "BriefDescription": "L2 writebacks that access L2 cache", 693 "CounterHTOff": "0,1,2,3,4,5,6,7" 694 }, 695 { 696 "PublicDescription": "Transactions accessing L2 pipe.", 697 "EventCode": "0xF0", 698 "Counter": "0,1,2,3", 699 "UMask": "0x80", 700 "EventName": "L2_TRANS.ALL_REQUESTS", 701 "SampleAfterValue": "200003", 702 "BriefDescription": "Transactions accessing L2 pipe", 703 "CounterHTOff": "0,1,2,3,4,5,6,7" 704 }, 705 { 706 "PublicDescription": "L2 cache lines in I state filling L2.", 707 "EventCode": "0xF1", 708 "Counter": "0,1,2,3", 709 "UMask": "0x1", 710 "EventName": "L2_LINES_IN.I", 711 "SampleAfterValue": "100003", 712 "BriefDescription": "L2 cache lines in I state filling L2", 713 "CounterHTOff": "0,1,2,3,4,5,6,7" 714 }, 715 { 716 "PublicDescription": "L2 cache lines in S state filling L2.", 717 "EventCode": "0xF1", 718 "Counter": "0,1,2,3", 719 "UMask": "0x2", 720 "EventName": "L2_LINES_IN.S", 721 "SampleAfterValue": "100003", 722 "BriefDescription": "L2 cache lines in S state filling L2", 723 "CounterHTOff": "0,1,2,3,4,5,6,7" 724 }, 725 { 726 "PublicDescription": "L2 cache lines in E state filling L2.", 727 "EventCode": "0xF1", 728 "Counter": "0,1,2,3", 729 "UMask": "0x4", 730 "EventName": "L2_LINES_IN.E", 731 "SampleAfterValue": "100003", 732 "BriefDescription": "L2 cache lines in E state filling L2", 733 "CounterHTOff": "0,1,2,3,4,5,6,7" 734 }, 735 { 736 "PublicDescription": "L2 cache lines filling L2.", 737 "EventCode": "0xF1", 738 "Counter": "0,1,2,3", 739 "UMask": "0x7", 740 "EventName": "L2_LINES_IN.ALL", 741 "SampleAfterValue": "100003", 742 "BriefDescription": "L2 cache lines filling L2", 743 "CounterHTOff": "0,1,2,3,4,5,6,7" 744 }, 745 { 746 "PublicDescription": "Clean L2 cache lines evicted by demand.", 747 "EventCode": "0xF2", 748 "Counter": "0,1,2,3", 749 "UMask": "0x1", 750 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 751 "SampleAfterValue": "100003", 752 "BriefDescription": "Clean L2 cache lines evicted by demand", 753 "CounterHTOff": "0,1,2,3,4,5,6,7" 754 }, 755 { 756 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 757 "EventCode": "0xF2", 758 "Counter": "0,1,2,3", 759 "UMask": "0x2", 760 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 761 "SampleAfterValue": "100003", 762 "BriefDescription": "Dirty L2 cache lines evicted by demand", 763 "CounterHTOff": "0,1,2,3,4,5,6,7" 764 }, 765 { 766 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", 767 "EventCode": "0xF2", 768 "Counter": "0,1,2,3", 769 "UMask": "0x4", 770 "EventName": "L2_LINES_OUT.PF_CLEAN", 771 "SampleAfterValue": "100003", 772 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", 773 "CounterHTOff": "0,1,2,3,4,5,6,7" 774 }, 775 { 776 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", 777 "EventCode": "0xF2", 778 "Counter": "0,1,2,3", 779 "UMask": "0x8", 780 "EventName": "L2_LINES_OUT.PF_DIRTY", 781 "SampleAfterValue": "100003", 782 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", 783 "CounterHTOff": "0,1,2,3,4,5,6,7" 784 }, 785 { 786 "PublicDescription": "Dirty L2 cache lines filling the L2.", 787 "EventCode": "0xF2", 788 "Counter": "0,1,2,3", 789 "UMask": "0xa", 790 "EventName": "L2_LINES_OUT.DIRTY_ALL", 791 "SampleAfterValue": "100003", 792 "BriefDescription": "Dirty L2 cache lines filling the L2", 793 "CounterHTOff": "0,1,2,3,4,5,6,7" 794 }, 795 { 796 "EventCode": "0xF4", 797 "Counter": "0,1,2,3", 798 "UMask": "0x10", 799 "EventName": "SQ_MISC.SPLIT_LOCK", 800 "SampleAfterValue": "100003", 801 "BriefDescription": "Split locks in SQ", 802 "CounterHTOff": "0,1,2,3,4,5,6,7" 803 }, 804 { 805 "EventCode": "0xB7, 0xBB", 806 "MSRValue": "0x4003c0091", 807 "Counter": "0,1,2,3", 808 "UMask": "0x1", 809 "Offcore": "1", 810 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 811 "MSRIndex": "0x1a6,0x1a7", 812 "SampleAfterValue": "100003", 813 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 814 "CounterHTOff": "0,1,2,3" 815 }, 816 { 817 "EventCode": "0xB7, 0xBB", 818 "MSRValue": "0x10003c0091", 819 "Counter": "0,1,2,3", 820 "UMask": "0x1", 821 "Offcore": "1", 822 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 823 "MSRIndex": "0x1a6,0x1a7", 824 "SampleAfterValue": "100003", 825 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 826 "CounterHTOff": "0,1,2,3" 827 }, 828 { 829 "EventCode": "0xB7, 0xBB", 830 "MSRValue": "0x1003c0091", 831 "Counter": "0,1,2,3", 832 "UMask": "0x1", 833 "Offcore": "1", 834 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 835 "MSRIndex": "0x1a6,0x1a7", 836 "SampleAfterValue": "100003", 837 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 838 "CounterHTOff": "0,1,2,3" 839 }, 840 { 841 "EventCode": "0xB7, 0xBB", 842 "MSRValue": "0x2003c0091", 843 "Counter": "0,1,2,3", 844 "UMask": "0x1", 845 "Offcore": "1", 846 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", 847 "MSRIndex": "0x1a6,0x1a7", 848 "SampleAfterValue": "100003", 849 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 850 "CounterHTOff": "0,1,2,3" 851 }, 852 { 853 "EventCode": "0xB7, 0xBB", 854 "MSRValue": "0x3f803c0090", 855 "Counter": "0,1,2,3", 856 "UMask": "0x1", 857 "Offcore": "1", 858 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", 859 "MSRIndex": "0x1a6,0x1a7", 860 "SampleAfterValue": "100003", 861 "BriefDescription": "Counts all prefetch data reads that hit the LLC", 862 "CounterHTOff": "0,1,2,3" 863 }, 864 { 865 "EventCode": "0xB7, 0xBB", 866 "MSRValue": "0x4003c0090", 867 "Counter": "0,1,2,3", 868 "UMask": "0x1", 869 "Offcore": "1", 870 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 871 "MSRIndex": "0x1a6,0x1a7", 872 "SampleAfterValue": "100003", 873 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 874 "CounterHTOff": "0,1,2,3" 875 }, 876 { 877 "EventCode": "0xB7, 0xBB", 878 "MSRValue": "0x10003c0090", 879 "Counter": "0,1,2,3", 880 "UMask": "0x1", 881 "Offcore": "1", 882 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 883 "MSRIndex": "0x1a6,0x1a7", 884 "SampleAfterValue": "100003", 885 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 886 "CounterHTOff": "0,1,2,3" 887 }, 888 { 889 "EventCode": "0xB7, 0xBB", 890 "MSRValue": "0x1003c0090", 891 "Counter": "0,1,2,3", 892 "UMask": "0x1", 893 "Offcore": "1", 894 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 895 "MSRIndex": "0x1a6,0x1a7", 896 "SampleAfterValue": "100003", 897 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 898 "CounterHTOff": "0,1,2,3" 899 }, 900 { 901 "EventCode": "0xB7, 0xBB", 902 "MSRValue": "0x2003c0090", 903 "Counter": "0,1,2,3", 904 "UMask": "0x1", 905 "Offcore": "1", 906 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", 907 "MSRIndex": "0x1a6,0x1a7", 908 "SampleAfterValue": "100003", 909 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 910 "CounterHTOff": "0,1,2,3" 911 }, 912 { 913 "EventCode": "0xB7, 0xBB", 914 "MSRValue": "0x3f803c03f7", 915 "Counter": "0,1,2,3", 916 "UMask": "0x1", 917 "Offcore": "1", 918 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", 919 "MSRIndex": "0x1a6,0x1a7", 920 "SampleAfterValue": "100003", 921 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", 922 "CounterHTOff": "0,1,2,3" 923 }, 924 { 925 "EventCode": "0xB7, 0xBB", 926 "MSRValue": "0x4003c03f7", 927 "Counter": "0,1,2,3", 928 "UMask": "0x1", 929 "Offcore": "1", 930 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 931 "MSRIndex": "0x1a6,0x1a7", 932 "SampleAfterValue": "100003", 933 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 934 "CounterHTOff": "0,1,2,3" 935 }, 936 { 937 "EventCode": "0xB7, 0xBB", 938 "MSRValue": "0x10003c03f7", 939 "Counter": "0,1,2,3", 940 "UMask": "0x1", 941 "Offcore": "1", 942 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 943 "MSRIndex": "0x1a6,0x1a7", 944 "SampleAfterValue": "100003", 945 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 946 "CounterHTOff": "0,1,2,3" 947 }, 948 { 949 "EventCode": "0xB7, 0xBB", 950 "MSRValue": "0x1003c03f7", 951 "Counter": "0,1,2,3", 952 "UMask": "0x1", 953 "Offcore": "1", 954 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", 955 "MSRIndex": "0x1a6,0x1a7", 956 "SampleAfterValue": "100003", 957 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 958 "CounterHTOff": "0,1,2,3" 959 }, 960 { 961 "EventCode": "0xB7, 0xBB", 962 "MSRValue": "0x2003c03f7", 963 "Counter": "0,1,2,3", 964 "UMask": "0x1", 965 "Offcore": "1", 966 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", 967 "MSRIndex": "0x1a6,0x1a7", 968 "SampleAfterValue": "100003", 969 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", 970 "CounterHTOff": "0,1,2,3" 971 }, 972 { 973 "EventCode": "0xB7, 0xBB", 974 "MSRValue": "0x10008", 975 "Counter": "0,1,2,3", 976 "UMask": "0x1", 977 "Offcore": "1", 978 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 979 "MSRIndex": "0x1a6,0x1a7", 980 "SampleAfterValue": "100003", 981 "BriefDescription": "Counts all writebacks from the core to the LLC", 982 "CounterHTOff": "0,1,2,3" 983 }, 984 { 985 "EventCode": "0xB7, 0xBB", 986 "MSRValue": "0x3f803c0004", 987 "Counter": "0,1,2,3", 988 "UMask": "0x1", 989 "Offcore": "1", 990 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 991 "MSRIndex": "0x1a6,0x1a7", 992 "SampleAfterValue": "100003", 993 "BriefDescription": "Counts all demand code reads that hit in the LLC", 994 "CounterHTOff": "0,1,2,3" 995 }, 996 { 997 "EventCode": "0xB7, 0xBB", 998 "MSRValue": "0x3f803c0001", 999 "Counter": "0,1,2,3", 1000 "UMask": "0x1", 1001 "Offcore": "1", 1002 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "SampleAfterValue": "100003", 1005 "BriefDescription": "Counts all demand data reads that hit in the LLC", 1006 "CounterHTOff": "0,1,2,3" 1007 }, 1008 { 1009 "EventCode": "0xB7, 0xBB", 1010 "MSRValue": "0x4003c0001", 1011 "Counter": "0,1,2,3", 1012 "UMask": "0x1", 1013 "Offcore": "1", 1014 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1015 "MSRIndex": "0x1a6,0x1a7", 1016 "SampleAfterValue": "100003", 1017 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1018 "CounterHTOff": "0,1,2,3" 1019 }, 1020 { 1021 "EventCode": "0xB7, 0xBB", 1022 "MSRValue": "0x10003c0001", 1023 "Counter": "0,1,2,3", 1024 "UMask": "0x1", 1025 "Offcore": "1", 1026 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "SampleAfterValue": "100003", 1029 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1030 "CounterHTOff": "0,1,2,3" 1031 }, 1032 { 1033 "EventCode": "0xB7, 0xBB", 1034 "MSRValue": "0x1003c0001", 1035 "Counter": "0,1,2,3", 1036 "UMask": "0x1", 1037 "Offcore": "1", 1038 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1039 "MSRIndex": "0x1a6,0x1a7", 1040 "SampleAfterValue": "100003", 1041 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1042 "CounterHTOff": "0,1,2,3" 1043 }, 1044 { 1045 "EventCode": "0xB7, 0xBB", 1046 "MSRValue": "0x2003c0001", 1047 "Counter": "0,1,2,3", 1048 "UMask": "0x1", 1049 "Offcore": "1", 1050 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", 1051 "MSRIndex": "0x1a6,0x1a7", 1052 "SampleAfterValue": "100003", 1053 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", 1054 "CounterHTOff": "0,1,2,3" 1055 }, 1056 { 1057 "EventCode": "0xB7, 0xBB", 1058 "MSRValue": "0x10003c0002", 1059 "Counter": "0,1,2,3", 1060 "UMask": "0x1", 1061 "Offcore": "1", 1062 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "SampleAfterValue": "100003", 1065 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1066 "CounterHTOff": "0,1,2,3" 1067 }, 1068 { 1069 "EventCode": "0xB7, 0xBB", 1070 "MSRValue": "0x803c8000", 1071 "Counter": "0,1,2,3", 1072 "UMask": "0x1", 1073 "Offcore": "1", 1074 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", 1075 "MSRIndex": "0x1a6,0x1a7", 1076 "SampleAfterValue": "100003", 1077 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", 1078 "CounterHTOff": "0,1,2,3" 1079 }, 1080 { 1081 "EventCode": "0xB7, 0xBB", 1082 "MSRValue": "0x23ffc08000", 1083 "Counter": "0,1,2,3", 1084 "UMask": "0x1", 1085 "Offcore": "1", 1086 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", 1087 "MSRIndex": "0x1a6,0x1a7", 1088 "SampleAfterValue": "100003", 1089 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", 1090 "CounterHTOff": "0,1,2,3" 1091 }, 1092 { 1093 "EventCode": "0xB7, 0xBB", 1094 "MSRValue": "0x3f803c0040", 1095 "Counter": "0,1,2,3", 1096 "UMask": "0x1", 1097 "Offcore": "1", 1098 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "SampleAfterValue": "100003", 1101 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", 1102 "CounterHTOff": "0,1,2,3" 1103 }, 1104 { 1105 "EventCode": "0xB7, 0xBB", 1106 "MSRValue": "0x3f803c0010", 1107 "Counter": "0,1,2,3", 1108 "UMask": "0x1", 1109 "Offcore": "1", 1110 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 1111 "MSRIndex": "0x1a6,0x1a7", 1112 "SampleAfterValue": "100003", 1113 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", 1114 "CounterHTOff": "0,1,2,3" 1115 }, 1116 { 1117 "EventCode": "0xB7, 0xBB", 1118 "MSRValue": "0x4003c0010", 1119 "Counter": "0,1,2,3", 1120 "UMask": "0x1", 1121 "Offcore": "1", 1122 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1123 "MSRIndex": "0x1a6,0x1a7", 1124 "SampleAfterValue": "100003", 1125 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1126 "CounterHTOff": "0,1,2,3" 1127 }, 1128 { 1129 "EventCode": "0xB7, 0xBB", 1130 "MSRValue": "0x10003c0010", 1131 "Counter": "0,1,2,3", 1132 "UMask": "0x1", 1133 "Offcore": "1", 1134 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1135 "MSRIndex": "0x1a6,0x1a7", 1136 "SampleAfterValue": "100003", 1137 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1138 "CounterHTOff": "0,1,2,3" 1139 }, 1140 { 1141 "EventCode": "0xB7, 0xBB", 1142 "MSRValue": "0x1003c0010", 1143 "Counter": "0,1,2,3", 1144 "UMask": "0x1", 1145 "Offcore": "1", 1146 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1147 "MSRIndex": "0x1a6,0x1a7", 1148 "SampleAfterValue": "100003", 1149 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1150 "CounterHTOff": "0,1,2,3" 1151 }, 1152 { 1153 "EventCode": "0xB7, 0xBB", 1154 "MSRValue": "0x2003c0010", 1155 "Counter": "0,1,2,3", 1156 "UMask": "0x1", 1157 "Offcore": "1", 1158 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", 1159 "MSRIndex": "0x1a6,0x1a7", 1160 "SampleAfterValue": "100003", 1161 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1162 "CounterHTOff": "0,1,2,3" 1163 }, 1164 { 1165 "EventCode": "0xB7, 0xBB", 1166 "MSRValue": "0x3f803c0200", 1167 "Counter": "0,1,2,3", 1168 "UMask": "0x1", 1169 "Offcore": "1", 1170 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 1171 "MSRIndex": "0x1a6,0x1a7", 1172 "SampleAfterValue": "100003", 1173 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", 1174 "CounterHTOff": "0,1,2,3" 1175 }, 1176 { 1177 "EventCode": "0xB7, 0xBB", 1178 "MSRValue": "0x3f803c0080", 1179 "Counter": "0,1,2,3", 1180 "UMask": "0x1", 1181 "Offcore": "1", 1182 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 1183 "MSRIndex": "0x1a6,0x1a7", 1184 "SampleAfterValue": "100003", 1185 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", 1186 "CounterHTOff": "0,1,2,3" 1187 }, 1188 { 1189 "EventCode": "0xB7, 0xBB", 1190 "MSRValue": "0x4003c0080", 1191 "Counter": "0,1,2,3", 1192 "UMask": "0x1", 1193 "Offcore": "1", 1194 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1195 "MSRIndex": "0x1a6,0x1a7", 1196 "SampleAfterValue": "100003", 1197 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1198 "CounterHTOff": "0,1,2,3" 1199 }, 1200 { 1201 "EventCode": "0xB7, 0xBB", 1202 "MSRValue": "0x10003c0080", 1203 "Counter": "0,1,2,3", 1204 "UMask": "0x1", 1205 "Offcore": "1", 1206 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1207 "MSRIndex": "0x1a6,0x1a7", 1208 "SampleAfterValue": "100003", 1209 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1210 "CounterHTOff": "0,1,2,3" 1211 }, 1212 { 1213 "EventCode": "0xB7, 0xBB", 1214 "MSRValue": "0x1003c0080", 1215 "Counter": "0,1,2,3", 1216 "UMask": "0x1", 1217 "Offcore": "1", 1218 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1219 "MSRIndex": "0x1a6,0x1a7", 1220 "SampleAfterValue": "100003", 1221 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1222 "CounterHTOff": "0,1,2,3" 1223 }, 1224 { 1225 "EventCode": "0xB7, 0xBB", 1226 "MSRValue": "0x2003c0080", 1227 "Counter": "0,1,2,3", 1228 "UMask": "0x1", 1229 "Offcore": "1", 1230 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", 1231 "MSRIndex": "0x1a6,0x1a7", 1232 "SampleAfterValue": "100003", 1233 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1234 "CounterHTOff": "0,1,2,3" 1235 }, 1236 { 1237 "EventCode": "0xB7, 0xBB", 1238 "MSRValue": "0x10400", 1239 "Counter": "0,1,2,3", 1240 "UMask": "0x1", 1241 "Offcore": "1", 1242 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1243 "MSRIndex": "0x1a6,0x1a7", 1244 "SampleAfterValue": "100003", 1245 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", 1246 "CounterHTOff": "0,1,2,3" 1247 }, 1248 { 1249 "EventCode": "0xB7, 0xBB", 1250 "MSRValue": "0x10800", 1251 "Counter": "0,1,2,3", 1252 "UMask": "0x1", 1253 "Offcore": "1", 1254 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1255 "MSRIndex": "0x1a6,0x1a7", 1256 "SampleAfterValue": "100003", 1257 "BriefDescription": "Counts non-temporal stores", 1258 "CounterHTOff": "0,1,2,3" 1259 } 1260]