1[ 2 { 3 "Counter": "Fixed counter 0", 4 "UMask": "0x1", 5 "EventName": "INST_RETIRED.ANY", 6 "SampleAfterValue": "2000003", 7 "BriefDescription": "Instructions retired from execution.", 8 "CounterHTOff": "Fixed counter 0" 9 }, 10 { 11 "Counter": "Fixed counter 1", 12 "UMask": "0x2", 13 "EventName": "CPU_CLK_UNHALTED.THREAD", 14 "SampleAfterValue": "2000003", 15 "BriefDescription": "Core cycles when the thread is not in halt state.", 16 "CounterHTOff": "Fixed counter 1" 17 }, 18 { 19 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 20 "Counter": "Fixed counter 1", 21 "UMask": "0x2", 22 "AnyThread": "1", 23 "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", 24 "SampleAfterValue": "2000003", 25 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", 26 "CounterHTOff": "Fixed counter 1" 27 }, 28 { 29 "Counter": "Fixed counter 2", 30 "UMask": "0x3", 31 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 32 "SampleAfterValue": "2000003", 33 "BriefDescription": "Reference cycles when the core is not in halt state.", 34 "CounterHTOff": "Fixed counter 2" 35 }, 36 { 37 "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", 38 "EventCode": "0x03", 39 "Counter": "0,1,2,3", 40 "UMask": "0x2", 41 "EventName": "LD_BLOCKS.STORE_FORWARD", 42 "SampleAfterValue": "100003", 43 "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", 44 "CounterHTOff": "0,1,2,3,4,5,6,7" 45 }, 46 { 47 "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 48 "EventCode": "0x03", 49 "Counter": "0,1,2,3", 50 "UMask": "0x8", 51 "EventName": "LD_BLOCKS.NO_SR", 52 "SampleAfterValue": "100003", 53 "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 54 "CounterHTOff": "0,1,2,3,4,5,6,7" 55 }, 56 { 57 "PublicDescription": "False dependencies in MOB due to partial compare on address.", 58 "EventCode": "0x07", 59 "Counter": "0,1,2,3", 60 "UMask": "0x1", 61 "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 62 "SampleAfterValue": "100003", 63 "BriefDescription": "False dependencies in MOB due to partial compare on address", 64 "CounterHTOff": "0,1,2,3,4,5,6,7" 65 }, 66 { 67 "EventCode": "0x0D", 68 "Counter": "0,1,2,3", 69 "UMask": "0x3", 70 "EventName": "INT_MISC.RECOVERY_CYCLES", 71 "SampleAfterValue": "2000003", 72 "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", 73 "CounterMask": "1", 74 "CounterHTOff": "0,1,2,3,4,5,6,7" 75 }, 76 { 77 "EventCode": "0x0D", 78 "Counter": "0,1,2,3", 79 "UMask": "0x3", 80 "EdgeDetect": "1", 81 "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", 82 "SampleAfterValue": "2000003", 83 "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", 84 "CounterMask": "1", 85 "CounterHTOff": "0,1,2,3,4,5,6,7" 86 }, 87 { 88 "EventCode": "0x0D", 89 "Counter": "0,1,2,3", 90 "UMask": "0x3", 91 "AnyThread": "1", 92 "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", 93 "SampleAfterValue": "2000003", 94 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", 95 "CounterMask": "1", 96 "CounterHTOff": "0,1,2,3,4,5,6,7" 97 }, 98 { 99 "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", 100 "EventCode": "0x0E", 101 "Counter": "0,1,2,3", 102 "UMask": "0x1", 103 "EventName": "UOPS_ISSUED.ANY", 104 "SampleAfterValue": "2000003", 105 "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", 106 "CounterHTOff": "0,1,2,3,4,5,6,7" 107 }, 108 { 109 "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", 110 "EventCode": "0x0E", 111 "Invert": "1", 112 "Counter": "0,1,2,3", 113 "UMask": "0x1", 114 "EventName": "UOPS_ISSUED.STALL_CYCLES", 115 "SampleAfterValue": "2000003", 116 "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", 117 "CounterMask": "1", 118 "CounterHTOff": "0,1,2,3" 119 }, 120 { 121 "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", 122 "EventCode": "0x0E", 123 "Invert": "1", 124 "Counter": "0,1,2,3", 125 "UMask": "0x1", 126 "AnyThread": "1", 127 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", 128 "SampleAfterValue": "2000003", 129 "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", 130 "CounterMask": "1", 131 "CounterHTOff": "0,1,2,3" 132 }, 133 { 134 "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", 135 "EventCode": "0x0E", 136 "Counter": "0,1,2,3", 137 "UMask": "0x10", 138 "EventName": "UOPS_ISSUED.FLAGS_MERGE", 139 "SampleAfterValue": "2000003", 140 "BriefDescription": "Number of flags-merge uops being allocated.", 141 "CounterHTOff": "0,1,2,3,4,5,6,7" 142 }, 143 { 144 "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", 145 "EventCode": "0x0E", 146 "Counter": "0,1,2,3", 147 "UMask": "0x20", 148 "EventName": "UOPS_ISSUED.SLOW_LEA", 149 "SampleAfterValue": "2000003", 150 "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", 151 "CounterHTOff": "0,1,2,3,4,5,6,7" 152 }, 153 { 154 "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", 155 "EventCode": "0x0E", 156 "Counter": "0,1,2,3", 157 "UMask": "0x40", 158 "EventName": "UOPS_ISSUED.SINGLE_MUL", 159 "SampleAfterValue": "2000003", 160 "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", 161 "CounterHTOff": "0,1,2,3,4,5,6,7" 162 }, 163 { 164 "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", 165 "EventCode": "0x14", 166 "Counter": "0,1,2,3", 167 "UMask": "0x1", 168 "EventName": "ARITH.FPU_DIV_ACTIVE", 169 "SampleAfterValue": "2000003", 170 "BriefDescription": "Cycles when divider is busy executing divide operations", 171 "CounterHTOff": "0,1,2,3,4,5,6,7" 172 }, 173 { 174 "PublicDescription": "Divide operations executed.", 175 "EventCode": "0x14", 176 "Counter": "0,1,2,3", 177 "UMask": "0x4", 178 "EdgeDetect": "1", 179 "EventName": "ARITH.FPU_DIV", 180 "SampleAfterValue": "100003", 181 "BriefDescription": "Divide operations executed", 182 "CounterMask": "1", 183 "CounterHTOff": "0,1,2,3,4,5,6,7" 184 }, 185 { 186 "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", 187 "EventCode": "0x3C", 188 "Counter": "0,1,2,3", 189 "UMask": "0x0", 190 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 191 "SampleAfterValue": "2000003", 192 "BriefDescription": "Thread cycles when thread is not in halt state", 193 "CounterHTOff": "0,1,2,3,4,5,6,7" 194 }, 195 { 196 "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 197 "EventCode": "0x3C", 198 "Counter": "0,1,2,3", 199 "UMask": "0x0", 200 "AnyThread": "1", 201 "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", 202 "SampleAfterValue": "2000003", 203 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", 204 "CounterHTOff": "0,1,2,3,4,5,6,7" 205 }, 206 { 207 "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", 208 "EventCode": "0x3C", 209 "Counter": "0,1,2,3", 210 "UMask": "0x1", 211 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", 212 "SampleAfterValue": "2000003", 213 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 214 "CounterHTOff": "0,1,2,3,4,5,6,7" 215 }, 216 { 217 "EventCode": "0x3C", 218 "Counter": "0,1,2,3", 219 "UMask": "0x1", 220 "AnyThread": "1", 221 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", 222 "SampleAfterValue": "2000003", 223 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", 224 "CounterHTOff": "0,1,2,3,4,5,6,7" 225 }, 226 { 227 "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 228 "EventCode": "0x3C", 229 "Counter": "0,1,2,3", 230 "UMask": "0x1", 231 "EventName": "CPU_CLK_UNHALTED.REF_XCLK", 232 "SampleAfterValue": "2000003", 233 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 234 "CounterHTOff": "0,1,2,3,4,5,6,7" 235 }, 236 { 237 "EventCode": "0x3C", 238 "Counter": "0,1,2,3", 239 "UMask": "0x1", 240 "AnyThread": "1", 241 "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", 242 "SampleAfterValue": "2000003", 243 "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", 244 "CounterHTOff": "0,1,2,3,4,5,6,7" 245 }, 246 { 247 "EventCode": "0x3C", 248 "Counter": "0,1,2,3", 249 "UMask": "0x2", 250 "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 251 "SampleAfterValue": "2000003", 252 "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", 253 "CounterHTOff": "0,1,2,3" 254 }, 255 { 256 "EventCode": "0x3C", 257 "Counter": "0,1,2,3", 258 "UMask": "0x2", 259 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 260 "SampleAfterValue": "2000003", 261 "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", 262 "CounterHTOff": "0,1,2,3,4,5,6,7" 263 }, 264 { 265 "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", 266 "EventCode": "0x4C", 267 "Counter": "0,1,2,3", 268 "UMask": "0x1", 269 "EventName": "LOAD_HIT_PRE.SW_PF", 270 "SampleAfterValue": "100003", 271 "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", 272 "CounterHTOff": "0,1,2,3,4,5,6,7" 273 }, 274 { 275 "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", 276 "EventCode": "0x4C", 277 "Counter": "0,1,2,3", 278 "UMask": "0x2", 279 "EventName": "LOAD_HIT_PRE.HW_PF", 280 "SampleAfterValue": "100003", 281 "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", 282 "CounterHTOff": "0,1,2,3,4,5,6,7" 283 }, 284 { 285 "EventCode": "0x58", 286 "Counter": "0,1,2,3", 287 "UMask": "0x1", 288 "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", 289 "SampleAfterValue": "1000003", 290 "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", 291 "CounterHTOff": "0,1,2,3,4,5,6,7" 292 }, 293 { 294 "EventCode": "0x58", 295 "Counter": "0,1,2,3", 296 "UMask": "0x2", 297 "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", 298 "SampleAfterValue": "1000003", 299 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", 300 "CounterHTOff": "0,1,2,3,4,5,6,7" 301 }, 302 { 303 "EventCode": "0x58", 304 "Counter": "0,1,2,3", 305 "UMask": "0x4", 306 "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", 307 "SampleAfterValue": "1000003", 308 "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", 309 "CounterHTOff": "0,1,2,3,4,5,6,7" 310 }, 311 { 312 "EventCode": "0x58", 313 "Counter": "0,1,2,3", 314 "UMask": "0x8", 315 "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", 316 "SampleAfterValue": "1000003", 317 "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", 318 "CounterHTOff": "0,1,2,3,4,5,6,7" 319 }, 320 { 321 "PublicDescription": "Cycles the RS is empty for the thread.", 322 "EventCode": "0x5E", 323 "Counter": "0,1,2,3", 324 "UMask": "0x1", 325 "EventName": "RS_EVENTS.EMPTY_CYCLES", 326 "SampleAfterValue": "2000003", 327 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", 328 "CounterHTOff": "0,1,2,3,4,5,6,7" 329 }, 330 { 331 "EventCode": "0x5E", 332 "Invert": "1", 333 "Counter": "0,1,2,3", 334 "UMask": "0x1", 335 "EdgeDetect": "1", 336 "EventName": "RS_EVENTS.EMPTY_END", 337 "SampleAfterValue": "200003", 338 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", 339 "CounterMask": "1", 340 "CounterHTOff": "0,1,2,3,4,5,6,7" 341 }, 342 { 343 "EventCode": "0x87", 344 "Counter": "0,1,2,3", 345 "UMask": "0x1", 346 "EventName": "ILD_STALL.LCP", 347 "SampleAfterValue": "2000003", 348 "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 349 "CounterHTOff": "0,1,2,3,4,5,6,7" 350 }, 351 { 352 "PublicDescription": "Stall cycles due to IQ is full.", 353 "EventCode": "0x87", 354 "Counter": "0,1,2,3", 355 "UMask": "0x4", 356 "EventName": "ILD_STALL.IQ_FULL", 357 "SampleAfterValue": "2000003", 358 "BriefDescription": "Stall cycles because IQ is full", 359 "CounterHTOff": "0,1,2,3,4,5,6,7" 360 }, 361 { 362 "PublicDescription": "Not taken macro-conditional branches.", 363 "EventCode": "0x88", 364 "Counter": "0,1,2,3", 365 "UMask": "0x41", 366 "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", 367 "SampleAfterValue": "200003", 368 "BriefDescription": "Not taken macro-conditional branches", 369 "CounterHTOff": "0,1,2,3,4,5,6,7" 370 }, 371 { 372 "PublicDescription": "Taken speculative and retired macro-conditional branches.", 373 "EventCode": "0x88", 374 "Counter": "0,1,2,3", 375 "UMask": "0x81", 376 "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", 377 "SampleAfterValue": "200003", 378 "BriefDescription": "Taken speculative and retired macro-conditional branches", 379 "CounterHTOff": "0,1,2,3,4,5,6,7" 380 }, 381 { 382 "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", 383 "EventCode": "0x88", 384 "Counter": "0,1,2,3", 385 "UMask": "0x82", 386 "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", 387 "SampleAfterValue": "200003", 388 "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", 389 "CounterHTOff": "0,1,2,3,4,5,6,7" 390 }, 391 { 392 "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", 393 "EventCode": "0x88", 394 "Counter": "0,1,2,3", 395 "UMask": "0x84", 396 "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", 397 "SampleAfterValue": "200003", 398 "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", 399 "CounterHTOff": "0,1,2,3,4,5,6,7" 400 }, 401 { 402 "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", 403 "EventCode": "0x88", 404 "Counter": "0,1,2,3", 405 "UMask": "0x88", 406 "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", 407 "SampleAfterValue": "200003", 408 "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", 409 "CounterHTOff": "0,1,2,3,4,5,6,7" 410 }, 411 { 412 "PublicDescription": "Taken speculative and retired direct near calls.", 413 "EventCode": "0x88", 414 "Counter": "0,1,2,3", 415 "UMask": "0x90", 416 "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", 417 "SampleAfterValue": "200003", 418 "BriefDescription": "Taken speculative and retired direct near calls", 419 "CounterHTOff": "0,1,2,3,4,5,6,7" 420 }, 421 { 422 "PublicDescription": "Taken speculative and retired indirect calls.", 423 "EventCode": "0x88", 424 "Counter": "0,1,2,3", 425 "UMask": "0xa0", 426 "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", 427 "SampleAfterValue": "200003", 428 "BriefDescription": "Taken speculative and retired indirect calls", 429 "CounterHTOff": "0,1,2,3,4,5,6,7" 430 }, 431 { 432 "PublicDescription": "Speculative and retired macro-conditional branches.", 433 "EventCode": "0x88", 434 "Counter": "0,1,2,3", 435 "UMask": "0xc1", 436 "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", 437 "SampleAfterValue": "200003", 438 "BriefDescription": "Speculative and retired macro-conditional branches", 439 "CounterHTOff": "0,1,2,3,4,5,6,7" 440 }, 441 { 442 "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", 443 "EventCode": "0x88", 444 "Counter": "0,1,2,3", 445 "UMask": "0xc2", 446 "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", 447 "SampleAfterValue": "200003", 448 "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", 449 "CounterHTOff": "0,1,2,3,4,5,6,7" 450 }, 451 { 452 "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", 453 "EventCode": "0x88", 454 "Counter": "0,1,2,3", 455 "UMask": "0xc4", 456 "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", 457 "SampleAfterValue": "200003", 458 "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", 459 "CounterHTOff": "0,1,2,3,4,5,6,7" 460 }, 461 { 462 "EventCode": "0x88", 463 "Counter": "0,1,2,3", 464 "UMask": "0xc8", 465 "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", 466 "SampleAfterValue": "200003", 467 "BriefDescription": "Speculative and retired indirect return branches.", 468 "CounterHTOff": "0,1,2,3,4,5,6,7" 469 }, 470 { 471 "PublicDescription": "Speculative and retired direct near calls.", 472 "EventCode": "0x88", 473 "Counter": "0,1,2,3", 474 "UMask": "0xd0", 475 "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", 476 "SampleAfterValue": "200003", 477 "BriefDescription": "Speculative and retired direct near calls", 478 "CounterHTOff": "0,1,2,3,4,5,6,7" 479 }, 480 { 481 "PublicDescription": "Counts all near executed branches (not necessarily retired).", 482 "EventCode": "0x88", 483 "Counter": "0,1,2,3", 484 "UMask": "0xff", 485 "EventName": "BR_INST_EXEC.ALL_BRANCHES", 486 "SampleAfterValue": "200003", 487 "BriefDescription": "Speculative and retired branches", 488 "CounterHTOff": "0,1,2,3,4,5,6,7" 489 }, 490 { 491 "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", 492 "EventCode": "0x89", 493 "Counter": "0,1,2,3", 494 "UMask": "0x41", 495 "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", 496 "SampleAfterValue": "200003", 497 "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", 498 "CounterHTOff": "0,1,2,3,4,5,6,7" 499 }, 500 { 501 "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", 502 "EventCode": "0x89", 503 "Counter": "0,1,2,3", 504 "UMask": "0x81", 505 "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", 506 "SampleAfterValue": "200003", 507 "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", 508 "CounterHTOff": "0,1,2,3,4,5,6,7" 509 }, 510 { 511 "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", 512 "EventCode": "0x89", 513 "Counter": "0,1,2,3", 514 "UMask": "0x84", 515 "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", 516 "SampleAfterValue": "200003", 517 "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", 518 "CounterHTOff": "0,1,2,3,4,5,6,7" 519 }, 520 { 521 "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", 522 "EventCode": "0x89", 523 "Counter": "0,1,2,3", 524 "UMask": "0x88", 525 "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", 526 "SampleAfterValue": "200003", 527 "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", 528 "CounterHTOff": "0,1,2,3,4,5,6,7" 529 }, 530 { 531 "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", 532 "EventCode": "0x89", 533 "Counter": "0,1,2,3", 534 "UMask": "0xa0", 535 "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", 536 "SampleAfterValue": "200003", 537 "BriefDescription": "Taken speculative and retired mispredicted indirect calls", 538 "CounterHTOff": "0,1,2,3,4,5,6,7" 539 }, 540 { 541 "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", 542 "EventCode": "0x89", 543 "Counter": "0,1,2,3", 544 "UMask": "0xc1", 545 "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", 546 "SampleAfterValue": "200003", 547 "BriefDescription": "Speculative and retired mispredicted macro conditional branches", 548 "CounterHTOff": "0,1,2,3,4,5,6,7" 549 }, 550 { 551 "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", 552 "EventCode": "0x89", 553 "Counter": "0,1,2,3", 554 "UMask": "0xc4", 555 "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", 556 "SampleAfterValue": "200003", 557 "BriefDescription": "Mispredicted indirect branches excluding calls and returns", 558 "CounterHTOff": "0,1,2,3,4,5,6,7" 559 }, 560 { 561 "PublicDescription": "Counts all near executed branches (not necessarily retired).", 562 "EventCode": "0x89", 563 "Counter": "0,1,2,3", 564 "UMask": "0xff", 565 "EventName": "BR_MISP_EXEC.ALL_BRANCHES", 566 "SampleAfterValue": "200003", 567 "BriefDescription": "Speculative and retired mispredicted macro conditional branches", 568 "CounterHTOff": "0,1,2,3,4,5,6,7" 569 }, 570 { 571 "PublicDescription": "Cycles which a Uop is dispatched on port 0.", 572 "EventCode": "0xA1", 573 "Counter": "0,1,2,3", 574 "UMask": "0x1", 575 "EventName": "UOPS_DISPATCHED_PORT.PORT_0", 576 "SampleAfterValue": "2000003", 577 "BriefDescription": "Cycles per thread when uops are dispatched to port 0", 578 "CounterHTOff": "0,1,2,3,4,5,6,7" 579 }, 580 { 581 "PublicDescription": "Cycles per core when uops are dispatched to port 0.", 582 "EventCode": "0xA1", 583 "Counter": "0,1,2,3", 584 "UMask": "0x1", 585 "AnyThread": "1", 586 "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", 587 "SampleAfterValue": "2000003", 588 "BriefDescription": "Cycles per core when uops are dispatched to port 0", 589 "CounterHTOff": "0,1,2,3,4,5,6,7" 590 }, 591 { 592 "PublicDescription": "Cycles which a Uop is dispatched on port 1.", 593 "EventCode": "0xA1", 594 "Counter": "0,1,2,3", 595 "UMask": "0x2", 596 "EventName": "UOPS_DISPATCHED_PORT.PORT_1", 597 "SampleAfterValue": "2000003", 598 "BriefDescription": "Cycles per thread when uops are dispatched to port 1", 599 "CounterHTOff": "0,1,2,3,4,5,6,7" 600 }, 601 { 602 "PublicDescription": "Cycles per core when uops are dispatched to port 1.", 603 "EventCode": "0xA1", 604 "Counter": "0,1,2,3", 605 "UMask": "0x2", 606 "AnyThread": "1", 607 "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", 608 "SampleAfterValue": "2000003", 609 "BriefDescription": "Cycles per core when uops are dispatched to port 1", 610 "CounterHTOff": "0,1,2,3,4,5,6,7" 611 }, 612 { 613 "PublicDescription": "Cycles which a Uop is dispatched on port 2.", 614 "EventCode": "0xA1", 615 "Counter": "0,1,2,3", 616 "UMask": "0xc", 617 "EventName": "UOPS_DISPATCHED_PORT.PORT_2", 618 "SampleAfterValue": "2000003", 619 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", 620 "CounterHTOff": "0,1,2,3,4,5,6,7" 621 }, 622 { 623 "EventCode": "0xA1", 624 "Counter": "0,1,2,3", 625 "UMask": "0xc", 626 "AnyThread": "1", 627 "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", 628 "SampleAfterValue": "2000003", 629 "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", 630 "CounterHTOff": "0,1,2,3,4,5,6,7" 631 }, 632 { 633 "PublicDescription": "Cycles which a Uop is dispatched on port 3.", 634 "EventCode": "0xA1", 635 "Counter": "0,1,2,3", 636 "UMask": "0x30", 637 "EventName": "UOPS_DISPATCHED_PORT.PORT_3", 638 "SampleAfterValue": "2000003", 639 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", 640 "CounterHTOff": "0,1,2,3,4,5,6,7" 641 }, 642 { 643 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", 644 "EventCode": "0xA1", 645 "Counter": "0,1,2,3", 646 "UMask": "0x30", 647 "AnyThread": "1", 648 "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", 649 "SampleAfterValue": "2000003", 650 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", 651 "CounterHTOff": "0,1,2,3,4,5,6,7" 652 }, 653 { 654 "PublicDescription": "Cycles which a Uop is dispatched on port 4.", 655 "EventCode": "0xA1", 656 "Counter": "0,1,2,3", 657 "UMask": "0x40", 658 "EventName": "UOPS_DISPATCHED_PORT.PORT_4", 659 "SampleAfterValue": "2000003", 660 "BriefDescription": "Cycles per thread when uops are dispatched to port 4", 661 "CounterHTOff": "0,1,2,3,4,5,6,7" 662 }, 663 { 664 "PublicDescription": "Cycles per core when uops are dispatched to port 4.", 665 "EventCode": "0xA1", 666 "Counter": "0,1,2,3", 667 "UMask": "0x40", 668 "AnyThread": "1", 669 "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", 670 "SampleAfterValue": "2000003", 671 "BriefDescription": "Cycles per core when uops are dispatched to port 4", 672 "CounterHTOff": "0,1,2,3,4,5,6,7" 673 }, 674 { 675 "PublicDescription": "Cycles which a Uop is dispatched on port 5.", 676 "EventCode": "0xA1", 677 "Counter": "0,1,2,3", 678 "UMask": "0x80", 679 "EventName": "UOPS_DISPATCHED_PORT.PORT_5", 680 "SampleAfterValue": "2000003", 681 "BriefDescription": "Cycles per thread when uops are dispatched to port 5", 682 "CounterHTOff": "0,1,2,3,4,5,6,7" 683 }, 684 { 685 "PublicDescription": "Cycles per core when uops are dispatched to port 5.", 686 "EventCode": "0xA1", 687 "Counter": "0,1,2,3", 688 "UMask": "0x80", 689 "AnyThread": "1", 690 "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", 691 "SampleAfterValue": "2000003", 692 "BriefDescription": "Cycles per core when uops are dispatched to port 5", 693 "CounterHTOff": "0,1,2,3,4,5,6,7" 694 }, 695 { 696 "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", 697 "EventCode": "0xA2", 698 "Counter": "0,1,2,3", 699 "UMask": "0x1", 700 "EventName": "RESOURCE_STALLS.ANY", 701 "SampleAfterValue": "2000003", 702 "BriefDescription": "Resource-related stall cycles", 703 "CounterHTOff": "0,1,2,3,4,5,6,7" 704 }, 705 { 706 "EventCode": "0xA2", 707 "Counter": "0,1,2,3", 708 "UMask": "0x4", 709 "EventName": "RESOURCE_STALLS.RS", 710 "SampleAfterValue": "2000003", 711 "BriefDescription": "Cycles stalled due to no eligible RS entry available.", 712 "CounterHTOff": "0,1,2,3,4,5,6,7" 713 }, 714 { 715 "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", 716 "EventCode": "0xA2", 717 "Counter": "0,1,2,3", 718 "UMask": "0x8", 719 "EventName": "RESOURCE_STALLS.SB", 720 "SampleAfterValue": "2000003", 721 "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 722 "CounterHTOff": "0,1,2,3,4,5,6,7" 723 }, 724 { 725 "EventCode": "0xA2", 726 "Counter": "0,1,2,3", 727 "UMask": "0x10", 728 "EventName": "RESOURCE_STALLS.ROB", 729 "SampleAfterValue": "2000003", 730 "BriefDescription": "Cycles stalled due to re-order buffer full.", 731 "CounterHTOff": "0,1,2,3,4,5,6,7" 732 }, 733 { 734 "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", 735 "EventCode": "0xA3", 736 "Counter": "0,1,2,3", 737 "UMask": "0x1", 738 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", 739 "SampleAfterValue": "2000003", 740 "BriefDescription": "Cycles with pending L2 cache miss loads.", 741 "CounterMask": "1", 742 "CounterHTOff": "0,1,2,3,4,5,6,7" 743 }, 744 { 745 "EventCode": "0xA3", 746 "Counter": "0,1,2,3", 747 "UMask": "0x1", 748 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 749 "SampleAfterValue": "2000003", 750 "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", 751 "CounterMask": "1", 752 "CounterHTOff": "0,1,2,3,4,5,6,7" 753 }, 754 { 755 "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", 756 "EventCode": "0xA3", 757 "Counter": "0,1,2,3", 758 "UMask": "0x2", 759 "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", 760 "SampleAfterValue": "2000003", 761 "BriefDescription": "Cycles with pending memory loads.", 762 "CounterMask": "2", 763 "CounterHTOff": "0,1,2,3" 764 }, 765 { 766 "EventCode": "0xA3", 767 "Counter": "0,1,2,3", 768 "UMask": "0x2", 769 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 770 "SampleAfterValue": "2000003", 771 "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 772 "CounterMask": "2", 773 "CounterHTOff": "0,1,2,3" 774 }, 775 { 776 "PublicDescription": "Total execution stalls.", 777 "EventCode": "0xA3", 778 "Counter": "0,1,2,3", 779 "UMask": "0x4", 780 "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", 781 "SampleAfterValue": "2000003", 782 "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", 783 "CounterMask": "4", 784 "CounterHTOff": "0,1,2,3" 785 }, 786 { 787 "EventCode": "0xA3", 788 "Counter": "0,1,2,3", 789 "UMask": "0x4", 790 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 791 "SampleAfterValue": "2000003", 792 "BriefDescription": "Total execution stalls.", 793 "CounterMask": "4", 794 "CounterHTOff": "0,1,2,3" 795 }, 796 { 797 "PublicDescription": "Number of loads missed L2.", 798 "EventCode": "0xA3", 799 "Counter": "0,1,2,3", 800 "UMask": "0x5", 801 "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", 802 "SampleAfterValue": "2000003", 803 "BriefDescription": "Execution stalls due to L2 cache misses.", 804 "CounterMask": "5", 805 "CounterHTOff": "0,1,2,3" 806 }, 807 { 808 "EventCode": "0xA3", 809 "Counter": "0,1,2,3", 810 "UMask": "0x5", 811 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 812 "SampleAfterValue": "2000003", 813 "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", 814 "CounterMask": "5", 815 "CounterHTOff": "0,1,2,3" 816 }, 817 { 818 "EventCode": "0xA3", 819 "Counter": "0,1,2,3", 820 "UMask": "0x6", 821 "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", 822 "SampleAfterValue": "2000003", 823 "BriefDescription": "Execution stalls due to memory subsystem.", 824 "CounterMask": "6", 825 "CounterHTOff": "0,1,2,3" 826 }, 827 { 828 "EventCode": "0xA3", 829 "Counter": "0,1,2,3", 830 "UMask": "0x6", 831 "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", 832 "SampleAfterValue": "2000003", 833 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 834 "CounterMask": "6", 835 "CounterHTOff": "0,1,2,3" 836 }, 837 { 838 "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", 839 "EventCode": "0xA3", 840 "Counter": "2", 841 "UMask": "0x8", 842 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", 843 "SampleAfterValue": "2000003", 844 "BriefDescription": "Cycles with pending L1 cache miss loads.", 845 "CounterMask": "8", 846 "CounterHTOff": "2" 847 }, 848 { 849 "EventCode": "0xA3", 850 "Counter": "2", 851 "UMask": "0x8", 852 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 853 "SampleAfterValue": "2000003", 854 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 855 "CounterMask": "8", 856 "CounterHTOff": "2" 857 }, 858 { 859 "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", 860 "EventCode": "0xA3", 861 "Counter": "2", 862 "UMask": "0xc", 863 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", 864 "SampleAfterValue": "2000003", 865 "BriefDescription": "Execution stalls due to L1 data cache misses", 866 "CounterMask": "12", 867 "CounterHTOff": "2" 868 }, 869 { 870 "EventCode": "0xA3", 871 "Counter": "2", 872 "UMask": "0xc", 873 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 874 "SampleAfterValue": "2000003", 875 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 876 "CounterMask": "12", 877 "CounterHTOff": "2" 878 }, 879 { 880 "EventCode": "0xA8", 881 "Counter": "0,1,2,3", 882 "UMask": "0x1", 883 "EventName": "LSD.UOPS", 884 "SampleAfterValue": "2000003", 885 "BriefDescription": "Number of Uops delivered by the LSD.", 886 "CounterHTOff": "0,1,2,3,4,5,6,7" 887 }, 888 { 889 "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 890 "EventCode": "0xA8", 891 "Counter": "0,1,2,3", 892 "UMask": "0x1", 893 "EventName": "LSD.CYCLES_ACTIVE", 894 "SampleAfterValue": "2000003", 895 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", 896 "CounterMask": "1", 897 "CounterHTOff": "0,1,2,3,4,5,6,7" 898 }, 899 { 900 "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 901 "EventCode": "0xA8", 902 "Counter": "0,1,2,3", 903 "UMask": "0x1", 904 "EventName": "LSD.CYCLES_4_UOPS", 905 "SampleAfterValue": "2000003", 906 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", 907 "CounterMask": "4", 908 "CounterHTOff": "0,1,2,3,4,5,6,7" 909 }, 910 { 911 "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", 912 "EventCode": "0xB1", 913 "Counter": "0,1,2,3", 914 "UMask": "0x1", 915 "EventName": "UOPS_EXECUTED.THREAD", 916 "SampleAfterValue": "2000003", 917 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 918 "CounterHTOff": "0,1,2,3,4,5,6,7" 919 }, 920 { 921 "EventCode": "0xB1", 922 "Invert": "1", 923 "Counter": "0,1,2,3", 924 "UMask": "0x1", 925 "EventName": "UOPS_EXECUTED.STALL_CYCLES", 926 "SampleAfterValue": "2000003", 927 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 928 "CounterMask": "1", 929 "CounterHTOff": "0,1,2,3" 930 }, 931 { 932 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 933 "EventCode": "0xB1", 934 "Counter": "0,1,2,3", 935 "UMask": "0x1", 936 "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", 937 "SampleAfterValue": "2000003", 938 "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 939 "CounterMask": "1", 940 "CounterHTOff": "0,1,2,3,4,5,6,7" 941 }, 942 { 943 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 944 "EventCode": "0xB1", 945 "Counter": "0,1,2,3", 946 "UMask": "0x1", 947 "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", 948 "SampleAfterValue": "2000003", 949 "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 950 "CounterMask": "2", 951 "CounterHTOff": "0,1,2,3,4,5,6,7" 952 }, 953 { 954 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 955 "EventCode": "0xB1", 956 "Counter": "0,1,2,3", 957 "UMask": "0x1", 958 "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", 959 "SampleAfterValue": "2000003", 960 "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 961 "CounterMask": "3", 962 "CounterHTOff": "0,1,2,3,4,5,6,7" 963 }, 964 { 965 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 966 "EventCode": "0xB1", 967 "Counter": "0,1,2,3", 968 "UMask": "0x1", 969 "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", 970 "SampleAfterValue": "2000003", 971 "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 972 "CounterMask": "4", 973 "CounterHTOff": "0,1,2,3,4,5,6,7" 974 }, 975 { 976 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", 977 "EventCode": "0xB1", 978 "Counter": "0,1,2,3", 979 "UMask": "0x2", 980 "EventName": "UOPS_EXECUTED.CORE", 981 "SampleAfterValue": "2000003", 982 "BriefDescription": "Number of uops executed on the core.", 983 "CounterHTOff": "0,1,2,3,4,5,6,7" 984 }, 985 { 986 "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 987 "EventCode": "0xB1", 988 "Counter": "0,1,2,3", 989 "UMask": "0x2", 990 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 991 "SampleAfterValue": "2000003", 992 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", 993 "CounterMask": "1", 994 "CounterHTOff": "0,1,2,3,4,5,6,7" 995 }, 996 { 997 "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 998 "EventCode": "0xB1", 999 "Counter": "0,1,2,3", 1000 "UMask": "0x2", 1001 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 1002 "SampleAfterValue": "2000003", 1003 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", 1004 "CounterMask": "2", 1005 "CounterHTOff": "0,1,2,3,4,5,6,7" 1006 }, 1007 { 1008 "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 1009 "EventCode": "0xB1", 1010 "Counter": "0,1,2,3", 1011 "UMask": "0x2", 1012 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 1013 "SampleAfterValue": "2000003", 1014 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", 1015 "CounterMask": "3", 1016 "CounterHTOff": "0,1,2,3,4,5,6,7" 1017 }, 1018 { 1019 "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 1020 "EventCode": "0xB1", 1021 "Counter": "0,1,2,3", 1022 "UMask": "0x2", 1023 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 1024 "SampleAfterValue": "2000003", 1025 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", 1026 "CounterMask": "4", 1027 "CounterHTOff": "0,1,2,3,4,5,6,7" 1028 }, 1029 { 1030 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", 1031 "EventCode": "0xB1", 1032 "Invert": "1", 1033 "Counter": "0,1,2,3", 1034 "UMask": "0x2", 1035 "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", 1036 "SampleAfterValue": "2000003", 1037 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", 1038 "CounterHTOff": "0,1,2,3,4,5,6,7" 1039 }, 1040 { 1041 "PublicDescription": "Number of instructions at retirement.", 1042 "EventCode": "0xC0", 1043 "Counter": "0,1,2,3", 1044 "UMask": "0x0", 1045 "EventName": "INST_RETIRED.ANY_P", 1046 "SampleAfterValue": "2000003", 1047 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 1048 "CounterHTOff": "0,1,2,3,4,5,6,7" 1049 }, 1050 { 1051 "PEBS": "2", 1052 "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", 1053 "EventCode": "0xC0", 1054 "Counter": "1", 1055 "UMask": "0x1", 1056 "EventName": "INST_RETIRED.PREC_DIST", 1057 "SampleAfterValue": "2000003", 1058 "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", 1059 "CounterHTOff": "1" 1060 }, 1061 { 1062 "EventCode": "0xC1", 1063 "Counter": "0,1,2,3", 1064 "UMask": "0x80", 1065 "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", 1066 "SampleAfterValue": "100003", 1067 "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", 1068 "CounterHTOff": "0,1,2,3,4,5,6,7" 1069 }, 1070 { 1071 "PEBS": "1", 1072 "EventCode": "0xC2", 1073 "Counter": "0,1,2,3", 1074 "UMask": "0x1", 1075 "EventName": "UOPS_RETIRED.ALL", 1076 "SampleAfterValue": "2000003", 1077 "BriefDescription": "Retired uops.", 1078 "CounterHTOff": "0,1,2,3,4,5,6,7" 1079 }, 1080 { 1081 "EventCode": "0xC2", 1082 "Invert": "1", 1083 "Counter": "0,1,2,3", 1084 "UMask": "0x1", 1085 "EventName": "UOPS_RETIRED.STALL_CYCLES", 1086 "SampleAfterValue": "2000003", 1087 "BriefDescription": "Cycles without actually retired uops.", 1088 "CounterMask": "1", 1089 "CounterHTOff": "0,1,2,3" 1090 }, 1091 { 1092 "EventCode": "0xC2", 1093 "Invert": "1", 1094 "Counter": "0,1,2,3", 1095 "UMask": "0x1", 1096 "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 1097 "SampleAfterValue": "2000003", 1098 "BriefDescription": "Cycles with less than 10 actually retired uops.", 1099 "CounterMask": "10", 1100 "CounterHTOff": "0,1,2,3" 1101 }, 1102 { 1103 "EventCode": "0xC2", 1104 "Invert": "1", 1105 "Counter": "0,1,2,3", 1106 "UMask": "0x1", 1107 "AnyThread": "1", 1108 "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", 1109 "SampleAfterValue": "2000003", 1110 "BriefDescription": "Cycles without actually retired uops.", 1111 "CounterMask": "1", 1112 "CounterHTOff": "0,1,2,3" 1113 }, 1114 { 1115 "PEBS": "1", 1116 "EventCode": "0xC2", 1117 "Counter": "0,1,2,3", 1118 "UMask": "0x2", 1119 "EventName": "UOPS_RETIRED.RETIRE_SLOTS", 1120 "SampleAfterValue": "2000003", 1121 "BriefDescription": "Retirement slots used.", 1122 "CounterHTOff": "0,1,2,3,4,5,6,7" 1123 }, 1124 { 1125 "EventCode": "0xC3", 1126 "Counter": "0,1,2,3", 1127 "UMask": "0x1", 1128 "EdgeDetect": "1", 1129 "EventName": "MACHINE_CLEARS.COUNT", 1130 "SampleAfterValue": "100003", 1131 "BriefDescription": "Number of machine clears (nukes) of any type.", 1132 "CounterMask": "1", 1133 "CounterHTOff": "0,1,2,3,4,5,6,7" 1134 }, 1135 { 1136 "PublicDescription": "Number of self-modifying-code machine clears detected.", 1137 "EventCode": "0xC3", 1138 "Counter": "0,1,2,3", 1139 "UMask": "0x4", 1140 "EventName": "MACHINE_CLEARS.SMC", 1141 "SampleAfterValue": "100003", 1142 "BriefDescription": "Self-modifying code (SMC) detected.", 1143 "CounterHTOff": "0,1,2,3,4,5,6,7" 1144 }, 1145 { 1146 "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", 1147 "EventCode": "0xC3", 1148 "Counter": "0,1,2,3", 1149 "UMask": "0x20", 1150 "EventName": "MACHINE_CLEARS.MASKMOV", 1151 "SampleAfterValue": "100003", 1152 "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", 1153 "CounterHTOff": "0,1,2,3,4,5,6,7" 1154 }, 1155 { 1156 "PublicDescription": "Branch instructions at retirement.", 1157 "EventCode": "0xC4", 1158 "Counter": "0,1,2,3", 1159 "UMask": "0x0", 1160 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 1161 "SampleAfterValue": "400009", 1162 "BriefDescription": "All (macro) branch instructions retired.", 1163 "CounterHTOff": "0,1,2,3,4,5,6,7" 1164 }, 1165 { 1166 "PEBS": "1", 1167 "EventCode": "0xC4", 1168 "Counter": "0,1,2,3", 1169 "UMask": "0x1", 1170 "EventName": "BR_INST_RETIRED.CONDITIONAL", 1171 "SampleAfterValue": "400009", 1172 "BriefDescription": "Conditional branch instructions retired.", 1173 "CounterHTOff": "0,1,2,3,4,5,6,7" 1174 }, 1175 { 1176 "PEBS": "1", 1177 "EventCode": "0xC4", 1178 "Counter": "0,1,2,3", 1179 "UMask": "0x2", 1180 "EventName": "BR_INST_RETIRED.NEAR_CALL", 1181 "SampleAfterValue": "100007", 1182 "BriefDescription": "Direct and indirect near call instructions retired.", 1183 "CounterHTOff": "0,1,2,3,4,5,6,7" 1184 }, 1185 { 1186 "PEBS": "1", 1187 "EventCode": "0xC4", 1188 "Counter": "0,1,2,3", 1189 "UMask": "0x2", 1190 "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", 1191 "SampleAfterValue": "100007", 1192 "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", 1193 "CounterHTOff": "0,1,2,3,4,5,6,7" 1194 }, 1195 { 1196 "PEBS": "2", 1197 "EventCode": "0xC4", 1198 "Counter": "0,1,2,3", 1199 "UMask": "0x4", 1200 "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", 1201 "SampleAfterValue": "400009", 1202 "BriefDescription": "All (macro) branch instructions retired.", 1203 "CounterHTOff": "0,1,2,3" 1204 }, 1205 { 1206 "PEBS": "1", 1207 "EventCode": "0xC4", 1208 "Counter": "0,1,2,3", 1209 "UMask": "0x8", 1210 "EventName": "BR_INST_RETIRED.NEAR_RETURN", 1211 "SampleAfterValue": "100007", 1212 "BriefDescription": "Return instructions retired.", 1213 "CounterHTOff": "0,1,2,3,4,5,6,7" 1214 }, 1215 { 1216 "PublicDescription": "Counts the number of not taken branch instructions retired.", 1217 "EventCode": "0xC4", 1218 "Counter": "0,1,2,3", 1219 "UMask": "0x10", 1220 "EventName": "BR_INST_RETIRED.NOT_TAKEN", 1221 "SampleAfterValue": "400009", 1222 "BriefDescription": "Not taken branch instructions retired.", 1223 "CounterHTOff": "0,1,2,3,4,5,6,7" 1224 }, 1225 { 1226 "PEBS": "1", 1227 "EventCode": "0xC4", 1228 "Counter": "0,1,2,3", 1229 "UMask": "0x20", 1230 "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 1231 "SampleAfterValue": "400009", 1232 "BriefDescription": "Taken branch instructions retired.", 1233 "CounterHTOff": "0,1,2,3,4,5,6,7" 1234 }, 1235 { 1236 "PublicDescription": "Number of far branches retired.", 1237 "EventCode": "0xC4", 1238 "Counter": "0,1,2,3", 1239 "UMask": "0x40", 1240 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 1241 "SampleAfterValue": "100007", 1242 "BriefDescription": "Far branch instructions retired.", 1243 "CounterHTOff": "0,1,2,3,4,5,6,7" 1244 }, 1245 { 1246 "PublicDescription": "Mispredicted branch instructions at retirement.", 1247 "EventCode": "0xC5", 1248 "Counter": "0,1,2,3", 1249 "UMask": "0x0", 1250 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 1251 "SampleAfterValue": "400009", 1252 "BriefDescription": "All mispredicted macro branch instructions retired.", 1253 "CounterHTOff": "0,1,2,3,4,5,6,7" 1254 }, 1255 { 1256 "PEBS": "1", 1257 "EventCode": "0xC5", 1258 "Counter": "0,1,2,3", 1259 "UMask": "0x1", 1260 "EventName": "BR_MISP_RETIRED.CONDITIONAL", 1261 "SampleAfterValue": "400009", 1262 "BriefDescription": "Mispredicted conditional branch instructions retired.", 1263 "CounterHTOff": "0,1,2,3,4,5,6,7" 1264 }, 1265 { 1266 "PEBS": "2", 1267 "EventCode": "0xC5", 1268 "Counter": "0,1,2,3", 1269 "UMask": "0x4", 1270 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", 1271 "SampleAfterValue": "400009", 1272 "BriefDescription": "Mispredicted macro branch instructions retired.", 1273 "CounterHTOff": "0,1,2,3" 1274 }, 1275 { 1276 "PEBS": "1", 1277 "EventCode": "0xC5", 1278 "Counter": "0,1,2,3", 1279 "UMask": "0x20", 1280 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 1281 "SampleAfterValue": "400009", 1282 "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", 1283 "CounterHTOff": "0,1,2,3,4,5,6,7" 1284 }, 1285 { 1286 "PublicDescription": "Count cases of saving new LBR records by hardware.", 1287 "EventCode": "0xCC", 1288 "Counter": "0,1,2,3", 1289 "UMask": "0x20", 1290 "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", 1291 "SampleAfterValue": "2000003", 1292 "BriefDescription": "Count cases of saving new LBR", 1293 "CounterHTOff": "0,1,2,3,4,5,6,7" 1294 }, 1295 { 1296 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 1297 "EventCode": "0xE6", 1298 "Counter": "0,1,2,3", 1299 "UMask": "0x1f", 1300 "EventName": "BACLEARS.ANY", 1301 "SampleAfterValue": "100003", 1302 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 1303 "CounterHTOff": "0,1,2,3,4,5,6,7" 1304 } 1305]