1[ 2 { 3 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 4 "EventCode": "0x05", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "MISALIGN_MEM_REF.LOADS", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", 14 "EventCode": "0x05", 15 "Counter": "0,1,2,3", 16 "UMask": "0x2", 17 "EventName": "MISALIGN_MEM_REF.STORES", 18 "SampleAfterValue": "2000003", 19 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "EventCode": "0xBE", 24 "Counter": "0,1,2,3", 25 "UMask": "0x1", 26 "EventName": "PAGE_WALKS.LLC_MISS", 27 "SampleAfterValue": "100003", 28 "BriefDescription": "Number of any page walk that had a miss in LLC.", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "EventCode": "0xC3", 33 "Counter": "0,1,2,3", 34 "UMask": "0x2", 35 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 36 "SampleAfterValue": "100003", 37 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 38 "CounterHTOff": "0,1,2,3,4,5,6,7" 39 }, 40 { 41 "PEBS": "2", 42 "PublicDescription": "Loads with latency value being above 4.", 43 "EventCode": "0xCD", 44 "MSRValue": "0x4", 45 "Counter": "3", 46 "UMask": "0x1", 47 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 48 "MSRIndex": "0x3F6", 49 "SampleAfterValue": "100003", 50 "BriefDescription": "Loads with latency value being above 4", 51 "TakenAlone": "1", 52 "CounterHTOff": "3" 53 }, 54 { 55 "PEBS": "2", 56 "PublicDescription": "Loads with latency value being above 8.", 57 "EventCode": "0xCD", 58 "MSRValue": "0x8", 59 "Counter": "3", 60 "UMask": "0x1", 61 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 62 "MSRIndex": "0x3F6", 63 "SampleAfterValue": "50021", 64 "BriefDescription": "Loads with latency value being above 8", 65 "TakenAlone": "1", 66 "CounterHTOff": "3" 67 }, 68 { 69 "PEBS": "2", 70 "PublicDescription": "Loads with latency value being above 16.", 71 "EventCode": "0xCD", 72 "MSRValue": "0x10", 73 "Counter": "3", 74 "UMask": "0x1", 75 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 76 "MSRIndex": "0x3F6", 77 "SampleAfterValue": "20011", 78 "BriefDescription": "Loads with latency value being above 16", 79 "TakenAlone": "1", 80 "CounterHTOff": "3" 81 }, 82 { 83 "PEBS": "2", 84 "PublicDescription": "Loads with latency value being above 32.", 85 "EventCode": "0xCD", 86 "MSRValue": "0x20", 87 "Counter": "3", 88 "UMask": "0x1", 89 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 90 "MSRIndex": "0x3F6", 91 "SampleAfterValue": "100007", 92 "BriefDescription": "Loads with latency value being above 32", 93 "TakenAlone": "1", 94 "CounterHTOff": "3" 95 }, 96 { 97 "PEBS": "2", 98 "PublicDescription": "Loads with latency value being above 64.", 99 "EventCode": "0xCD", 100 "MSRValue": "0x40", 101 "Counter": "3", 102 "UMask": "0x1", 103 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 104 "MSRIndex": "0x3F6", 105 "SampleAfterValue": "2003", 106 "BriefDescription": "Loads with latency value being above 64", 107 "TakenAlone": "1", 108 "CounterHTOff": "3" 109 }, 110 { 111 "PEBS": "2", 112 "PublicDescription": "Loads with latency value being above 128.", 113 "EventCode": "0xCD", 114 "MSRValue": "0x80", 115 "Counter": "3", 116 "UMask": "0x1", 117 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 118 "MSRIndex": "0x3F6", 119 "SampleAfterValue": "1009", 120 "BriefDescription": "Loads with latency value being above 128", 121 "TakenAlone": "1", 122 "CounterHTOff": "3" 123 }, 124 { 125 "PEBS": "2", 126 "PublicDescription": "Loads with latency value being above 256.", 127 "EventCode": "0xCD", 128 "MSRValue": "0x100", 129 "Counter": "3", 130 "UMask": "0x1", 131 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 132 "MSRIndex": "0x3F6", 133 "SampleAfterValue": "503", 134 "BriefDescription": "Loads with latency value being above 256", 135 "TakenAlone": "1", 136 "CounterHTOff": "3" 137 }, 138 { 139 "PEBS": "2", 140 "PublicDescription": "Loads with latency value being above 512.", 141 "EventCode": "0xCD", 142 "MSRValue": "0x200", 143 "Counter": "3", 144 "UMask": "0x1", 145 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 146 "MSRIndex": "0x3F6", 147 "SampleAfterValue": "101", 148 "BriefDescription": "Loads with latency value being above 512", 149 "TakenAlone": "1", 150 "CounterHTOff": "3" 151 }, 152 { 153 "PEBS": "2", 154 "EventCode": "0xCD", 155 "Counter": "3", 156 "UMask": "0x2", 157 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 158 "SampleAfterValue": "2000003", 159 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", 160 "PRECISE_STORE": "1", 161 "TakenAlone": "1", 162 "CounterHTOff": "3" 163 }, 164 { 165 "EventCode": "0xB7, 0xBB", 166 "MSRValue": "0x300400244", 167 "Counter": "0,1,2,3", 168 "UMask": "0x1", 169 "Offcore": "1", 170 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 171 "MSRIndex": "0x1a6,0x1a7", 172 "SampleAfterValue": "100003", 173 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", 174 "CounterHTOff": "0,1,2,3" 175 }, 176 { 177 "EventCode": "0xB7, 0xBB", 178 "MSRValue": "0x300400091", 179 "Counter": "0,1,2,3", 180 "UMask": "0x1", 181 "Offcore": "1", 182 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 183 "MSRIndex": "0x1a6,0x1a7", 184 "SampleAfterValue": "100003", 185 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", 186 "CounterHTOff": "0,1,2,3" 187 }, 188 { 189 "EventCode": "0xB7, 0xBB", 190 "MSRValue": "0x3004003f7", 191 "Counter": "0,1,2,3", 192 "UMask": "0x1", 193 "Offcore": "1", 194 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", 195 "MSRIndex": "0x1a6,0x1a7", 196 "SampleAfterValue": "100003", 197 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", 198 "CounterHTOff": "0,1,2,3" 199 }, 200 { 201 "EventCode": "0xB7, 0xBB", 202 "MSRValue": "0x300400004", 203 "Counter": "0,1,2,3", 204 "UMask": "0x1", 205 "Offcore": "1", 206 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", 207 "MSRIndex": "0x1a6,0x1a7", 208 "SampleAfterValue": "100003", 209 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", 210 "CounterHTOff": "0,1,2,3" 211 }, 212 { 213 "EventCode": "0xB7, 0xBB", 214 "MSRValue": "0x300400001", 215 "Counter": "0,1,2,3", 216 "UMask": "0x1", 217 "Offcore": "1", 218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", 219 "MSRIndex": "0x1a6,0x1a7", 220 "SampleAfterValue": "100003", 221 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", 222 "CounterHTOff": "0,1,2,3" 223 }, 224 { 225 "EventCode": "0xB7, 0xBB", 226 "MSRValue": "0x6004001b3", 227 "Counter": "0,1,2,3", 228 "UMask": "0x1", 229 "Offcore": "1", 230 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", 231 "MSRIndex": "0x1a6,0x1a7", 232 "SampleAfterValue": "100003", 233 "BriefDescription": "Counts LLC replacements", 234 "CounterHTOff": "0,1,2,3" 235 } 236]