1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x51", 7 "EventName": "L1D.REPLACEMENT", 8 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EventCode": "0x48", 18 "EventName": "L1D_PEND_MISS.FB_FULL", 19 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 20 "SampleAfterValue": "2000003", 21 "UMask": "0x2" 22 }, 23 { 24 "BriefDescription": "L1D miss oustandings duration in cycles", 25 "Counter": "2", 26 "CounterHTOff": "2", 27 "EventCode": "0x48", 28 "EventName": "L1D_PEND_MISS.PENDING", 29 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x1" 32 }, 33 { 34 "BriefDescription": "Cycles with L1D load Misses outstanding.", 35 "Counter": "2", 36 "CounterHTOff": "2", 37 "CounterMask": "1", 38 "EventCode": "0x48", 39 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x1" 42 }, 43 { 44 "AnyThread": "1", 45 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 46 "Counter": "2", 47 "CounterHTOff": "2", 48 "CounterMask": "1", 49 "EventCode": "0x48", 50 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 51 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 52 "SampleAfterValue": "2000003", 53 "UMask": "0x1" 54 }, 55 { 56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 57 "Counter": "0,1,2,3", 58 "CounterHTOff": "0,1,2,3,4,5,6,7", 59 "EventCode": "0x28", 60 "EventName": "L2_L1D_WB_RQSTS.ALL", 61 "SampleAfterValue": "200003", 62 "UMask": "0xf" 63 }, 64 { 65 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 66 "Counter": "0,1,2,3", 67 "CounterHTOff": "0,1,2,3,4,5,6,7", 68 "EventCode": "0x28", 69 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 70 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 71 "SampleAfterValue": "200003", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 76 "Counter": "0,1,2,3", 77 "CounterHTOff": "0,1,2,3,4,5,6,7", 78 "EventCode": "0x28", 79 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 80 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 81 "SampleAfterValue": "200003", 82 "UMask": "0x8" 83 }, 84 { 85 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", 86 "Counter": "0,1,2,3", 87 "CounterHTOff": "0,1,2,3,4,5,6,7", 88 "EventCode": "0x28", 89 "EventName": "L2_L1D_WB_RQSTS.MISS", 90 "PublicDescription": "Not rejected writebacks that missed LLC.", 91 "SampleAfterValue": "200003", 92 "UMask": "0x1" 93 }, 94 { 95 "BriefDescription": "L2 cache lines filling L2", 96 "Counter": "0,1,2,3", 97 "CounterHTOff": "0,1,2,3,4,5,6,7", 98 "EventCode": "0xF1", 99 "EventName": "L2_LINES_IN.ALL", 100 "PublicDescription": "L2 cache lines filling L2.", 101 "SampleAfterValue": "100003", 102 "UMask": "0x7" 103 }, 104 { 105 "BriefDescription": "L2 cache lines in E state filling L2", 106 "Counter": "0,1,2,3", 107 "CounterHTOff": "0,1,2,3,4,5,6,7", 108 "EventCode": "0xF1", 109 "EventName": "L2_LINES_IN.E", 110 "PublicDescription": "L2 cache lines in E state filling L2.", 111 "SampleAfterValue": "100003", 112 "UMask": "0x4" 113 }, 114 { 115 "BriefDescription": "L2 cache lines in I state filling L2", 116 "Counter": "0,1,2,3", 117 "CounterHTOff": "0,1,2,3,4,5,6,7", 118 "EventCode": "0xF1", 119 "EventName": "L2_LINES_IN.I", 120 "PublicDescription": "L2 cache lines in I state filling L2.", 121 "SampleAfterValue": "100003", 122 "UMask": "0x1" 123 }, 124 { 125 "BriefDescription": "L2 cache lines in S state filling L2", 126 "Counter": "0,1,2,3", 127 "CounterHTOff": "0,1,2,3,4,5,6,7", 128 "EventCode": "0xF1", 129 "EventName": "L2_LINES_IN.S", 130 "PublicDescription": "L2 cache lines in S state filling L2.", 131 "SampleAfterValue": "100003", 132 "UMask": "0x2" 133 }, 134 { 135 "BriefDescription": "Clean L2 cache lines evicted by demand", 136 "Counter": "0,1,2,3", 137 "CounterHTOff": "0,1,2,3,4,5,6,7", 138 "EventCode": "0xF2", 139 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 140 "PublicDescription": "Clean L2 cache lines evicted by demand.", 141 "SampleAfterValue": "100003", 142 "UMask": "0x1" 143 }, 144 { 145 "BriefDescription": "Dirty L2 cache lines evicted by demand", 146 "Counter": "0,1,2,3", 147 "CounterHTOff": "0,1,2,3,4,5,6,7", 148 "EventCode": "0xF2", 149 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 150 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 151 "SampleAfterValue": "100003", 152 "UMask": "0x2" 153 }, 154 { 155 "BriefDescription": "Dirty L2 cache lines filling the L2", 156 "Counter": "0,1,2,3", 157 "CounterHTOff": "0,1,2,3,4,5,6,7", 158 "EventCode": "0xF2", 159 "EventName": "L2_LINES_OUT.DIRTY_ALL", 160 "PublicDescription": "Dirty L2 cache lines filling the L2.", 161 "SampleAfterValue": "100003", 162 "UMask": "0xa" 163 }, 164 { 165 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3,4,5,6,7", 168 "EventCode": "0xF2", 169 "EventName": "L2_LINES_OUT.PF_CLEAN", 170 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", 171 "SampleAfterValue": "100003", 172 "UMask": "0x4" 173 }, 174 { 175 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", 176 "Counter": "0,1,2,3", 177 "CounterHTOff": "0,1,2,3,4,5,6,7", 178 "EventCode": "0xF2", 179 "EventName": "L2_LINES_OUT.PF_DIRTY", 180 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", 181 "SampleAfterValue": "100003", 182 "UMask": "0x8" 183 }, 184 { 185 "BriefDescription": "L2 code requests", 186 "Counter": "0,1,2,3", 187 "CounterHTOff": "0,1,2,3,4,5,6,7", 188 "EventCode": "0x24", 189 "EventName": "L2_RQSTS.ALL_CODE_RD", 190 "PublicDescription": "Counts all L2 code requests.", 191 "SampleAfterValue": "200003", 192 "UMask": "0x30" 193 }, 194 { 195 "BriefDescription": "Demand Data Read requests", 196 "Counter": "0,1,2,3", 197 "CounterHTOff": "0,1,2,3,4,5,6,7", 198 "EventCode": "0x24", 199 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 200 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 201 "SampleAfterValue": "200003", 202 "UMask": "0x3" 203 }, 204 { 205 "BriefDescription": "Requests from L2 hardware prefetchers", 206 "Counter": "0,1,2,3", 207 "CounterHTOff": "0,1,2,3,4,5,6,7", 208 "EventCode": "0x24", 209 "EventName": "L2_RQSTS.ALL_PF", 210 "PublicDescription": "Counts all L2 HW prefetcher requests.", 211 "SampleAfterValue": "200003", 212 "UMask": "0xc0" 213 }, 214 { 215 "BriefDescription": "RFO requests to L2 cache", 216 "Counter": "0,1,2,3", 217 "CounterHTOff": "0,1,2,3,4,5,6,7", 218 "EventCode": "0x24", 219 "EventName": "L2_RQSTS.ALL_RFO", 220 "PublicDescription": "Counts all L2 store RFO requests.", 221 "SampleAfterValue": "200003", 222 "UMask": "0xc" 223 }, 224 { 225 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 226 "Counter": "0,1,2,3", 227 "CounterHTOff": "0,1,2,3,4,5,6,7", 228 "EventCode": "0x24", 229 "EventName": "L2_RQSTS.CODE_RD_HIT", 230 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 231 "SampleAfterValue": "200003", 232 "UMask": "0x10" 233 }, 234 { 235 "BriefDescription": "L2 cache misses when fetching instructions", 236 "Counter": "0,1,2,3", 237 "CounterHTOff": "0,1,2,3,4,5,6,7", 238 "EventCode": "0x24", 239 "EventName": "L2_RQSTS.CODE_RD_MISS", 240 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 241 "SampleAfterValue": "200003", 242 "UMask": "0x20" 243 }, 244 { 245 "BriefDescription": "Demand Data Read requests that hit L2 cache", 246 "Counter": "0,1,2,3", 247 "CounterHTOff": "0,1,2,3,4,5,6,7", 248 "EventCode": "0x24", 249 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 250 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 251 "SampleAfterValue": "200003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3,4,5,6,7", 258 "EventCode": "0x24", 259 "EventName": "L2_RQSTS.PF_HIT", 260 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 261 "SampleAfterValue": "200003", 262 "UMask": "0x40" 263 }, 264 { 265 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", 266 "Counter": "0,1,2,3", 267 "CounterHTOff": "0,1,2,3,4,5,6,7", 268 "EventCode": "0x24", 269 "EventName": "L2_RQSTS.PF_MISS", 270 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 271 "SampleAfterValue": "200003", 272 "UMask": "0x80" 273 }, 274 { 275 "BriefDescription": "RFO requests that hit L2 cache", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3,4,5,6,7", 278 "EventCode": "0x24", 279 "EventName": "L2_RQSTS.RFO_HIT", 280 "PublicDescription": "RFO requests that hit L2 cache.", 281 "SampleAfterValue": "200003", 282 "UMask": "0x4" 283 }, 284 { 285 "BriefDescription": "RFO requests that miss L2 cache", 286 "Counter": "0,1,2,3", 287 "CounterHTOff": "0,1,2,3,4,5,6,7", 288 "EventCode": "0x24", 289 "EventName": "L2_RQSTS.RFO_MISS", 290 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 291 "SampleAfterValue": "200003", 292 "UMask": "0x8" 293 }, 294 { 295 "BriefDescription": "RFOs that access cache lines in any state", 296 "Counter": "0,1,2,3", 297 "CounterHTOff": "0,1,2,3,4,5,6,7", 298 "EventCode": "0x27", 299 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 300 "PublicDescription": "RFOs that access cache lines in any state.", 301 "SampleAfterValue": "200003", 302 "UMask": "0xf" 303 }, 304 { 305 "BriefDescription": "RFOs that hit cache lines in M state", 306 "Counter": "0,1,2,3", 307 "CounterHTOff": "0,1,2,3,4,5,6,7", 308 "EventCode": "0x27", 309 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 310 "PublicDescription": "RFOs that hit cache lines in M state.", 311 "SampleAfterValue": "200003", 312 "UMask": "0x8" 313 }, 314 { 315 "BriefDescription": "RFOs that miss cache lines", 316 "Counter": "0,1,2,3", 317 "CounterHTOff": "0,1,2,3,4,5,6,7", 318 "EventCode": "0x27", 319 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 320 "PublicDescription": "RFOs that miss cache lines.", 321 "SampleAfterValue": "200003", 322 "UMask": "0x1" 323 }, 324 { 325 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", 326 "Counter": "0,1,2,3", 327 "CounterHTOff": "0,1,2,3,4,5,6,7", 328 "EventCode": "0xF0", 329 "EventName": "L2_TRANS.ALL_PF", 330 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", 331 "SampleAfterValue": "200003", 332 "UMask": "0x8" 333 }, 334 { 335 "BriefDescription": "Transactions accessing L2 pipe", 336 "Counter": "0,1,2,3", 337 "CounterHTOff": "0,1,2,3,4,5,6,7", 338 "EventCode": "0xF0", 339 "EventName": "L2_TRANS.ALL_REQUESTS", 340 "PublicDescription": "Transactions accessing L2 pipe.", 341 "SampleAfterValue": "200003", 342 "UMask": "0x80" 343 }, 344 { 345 "BriefDescription": "L2 cache accesses when fetching instructions", 346 "Counter": "0,1,2,3", 347 "CounterHTOff": "0,1,2,3,4,5,6,7", 348 "EventCode": "0xF0", 349 "EventName": "L2_TRANS.CODE_RD", 350 "PublicDescription": "L2 cache accesses when fetching instructions.", 351 "SampleAfterValue": "200003", 352 "UMask": "0x4" 353 }, 354 { 355 "BriefDescription": "Demand Data Read requests that access L2 cache", 356 "Counter": "0,1,2,3", 357 "CounterHTOff": "0,1,2,3,4,5,6,7", 358 "EventCode": "0xF0", 359 "EventName": "L2_TRANS.DEMAND_DATA_RD", 360 "PublicDescription": "Demand Data Read requests that access L2 cache.", 361 "SampleAfterValue": "200003", 362 "UMask": "0x1" 363 }, 364 { 365 "BriefDescription": "L1D writebacks that access L2 cache", 366 "Counter": "0,1,2,3", 367 "CounterHTOff": "0,1,2,3,4,5,6,7", 368 "EventCode": "0xF0", 369 "EventName": "L2_TRANS.L1D_WB", 370 "PublicDescription": "L1D writebacks that access L2 cache.", 371 "SampleAfterValue": "200003", 372 "UMask": "0x10" 373 }, 374 { 375 "BriefDescription": "L2 fill requests that access L2 cache", 376 "Counter": "0,1,2,3", 377 "CounterHTOff": "0,1,2,3,4,5,6,7", 378 "EventCode": "0xF0", 379 "EventName": "L2_TRANS.L2_FILL", 380 "PublicDescription": "L2 fill requests that access L2 cache.", 381 "SampleAfterValue": "200003", 382 "UMask": "0x20" 383 }, 384 { 385 "BriefDescription": "L2 writebacks that access L2 cache", 386 "Counter": "0,1,2,3", 387 "CounterHTOff": "0,1,2,3,4,5,6,7", 388 "EventCode": "0xF0", 389 "EventName": "L2_TRANS.L2_WB", 390 "PublicDescription": "L2 writebacks that access L2 cache.", 391 "SampleAfterValue": "200003", 392 "UMask": "0x40" 393 }, 394 { 395 "BriefDescription": "RFO requests that access L2 cache", 396 "Counter": "0,1,2,3", 397 "CounterHTOff": "0,1,2,3,4,5,6,7", 398 "EventCode": "0xF0", 399 "EventName": "L2_TRANS.RFO", 400 "PublicDescription": "RFO requests that access L2 cache.", 401 "SampleAfterValue": "200003", 402 "UMask": "0x2" 403 }, 404 { 405 "BriefDescription": "Cycles when L1D is locked", 406 "Counter": "0,1,2,3", 407 "CounterHTOff": "0,1,2,3,4,5,6,7", 408 "EventCode": "0x63", 409 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 410 "PublicDescription": "Cycles in which the L1D is locked.", 411 "SampleAfterValue": "2000003", 412 "UMask": "0x2" 413 }, 414 { 415 "BriefDescription": "Core-originated cacheable demand requests missed LLC", 416 "Counter": "0,1,2,3", 417 "CounterHTOff": "0,1,2,3,4,5,6,7", 418 "EventCode": "0x2E", 419 "EventName": "LONGEST_LAT_CACHE.MISS", 420 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 421 "SampleAfterValue": "100003", 422 "UMask": "0x41" 423 }, 424 { 425 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", 426 "Counter": "0,1,2,3", 427 "CounterHTOff": "0,1,2,3,4,5,6,7", 428 "EventCode": "0x2E", 429 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 430 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 431 "SampleAfterValue": "100003", 432 "UMask": "0x4f" 433 }, 434 { 435 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", 436 "Counter": "0,1,2,3", 437 "CounterHTOff": "0,1,2,3", 438 "EventCode": "0xD2", 439 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 440 "PEBS": "1", 441 "SampleAfterValue": "20011", 442 "UMask": "0x2" 443 }, 444 { 445 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", 446 "Counter": "0,1,2,3", 447 "CounterHTOff": "0,1,2,3", 448 "EventCode": "0xD2", 449 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 450 "PEBS": "1", 451 "SampleAfterValue": "20011", 452 "UMask": "0x4" 453 }, 454 { 455 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", 456 "Counter": "0,1,2,3", 457 "CounterHTOff": "0,1,2,3", 458 "EventCode": "0xD2", 459 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 460 "PEBS": "1", 461 "SampleAfterValue": "20011", 462 "UMask": "0x1" 463 }, 464 { 465 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", 466 "Counter": "0,1,2,3", 467 "CounterHTOff": "0,1,2,3", 468 "EventCode": "0xD2", 469 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 470 "PEBS": "1", 471 "SampleAfterValue": "100003", 472 "UMask": "0x8" 473 }, 474 { 475 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", 476 "Counter": "0,1,2,3", 477 "CounterHTOff": "0,1,2,3", 478 "EventCode": "0xD3", 479 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 480 "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", 481 "SampleAfterValue": "100007", 482 "UMask": "0x1" 483 }, 484 { 485 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 486 "Counter": "0,1,2,3", 487 "CounterHTOff": "0,1,2,3", 488 "EventCode": "0xD1", 489 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 490 "PEBS": "1", 491 "SampleAfterValue": "100003", 492 "UMask": "0x40" 493 }, 494 { 495 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 496 "Counter": "0,1,2,3", 497 "CounterHTOff": "0,1,2,3", 498 "EventCode": "0xD1", 499 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 500 "PEBS": "1", 501 "SampleAfterValue": "2000003", 502 "UMask": "0x1" 503 }, 504 { 505 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", 506 "Counter": "0,1,2,3", 507 "CounterHTOff": "0,1,2,3", 508 "EventCode": "0xD1", 509 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 510 "PEBS": "1", 511 "SampleAfterValue": "100003", 512 "UMask": "0x8" 513 }, 514 { 515 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 516 "Counter": "0,1,2,3", 517 "CounterHTOff": "0,1,2,3", 518 "EventCode": "0xD1", 519 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 520 "PEBS": "1", 521 "SampleAfterValue": "100003", 522 "UMask": "0x2" 523 }, 524 { 525 "BriefDescription": "Retired load uops with L2 cache misses as data sources.", 526 "Counter": "0,1,2,3", 527 "CounterHTOff": "0,1,2,3", 528 "EventCode": "0xD1", 529 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 530 "PEBS": "1", 531 "SampleAfterValue": "50021", 532 "UMask": "0x10" 533 }, 534 { 535 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", 536 "Counter": "0,1,2,3", 537 "CounterHTOff": "0,1,2,3", 538 "EventCode": "0xD1", 539 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 540 "PEBS": "1", 541 "SampleAfterValue": "50021", 542 "UMask": "0x4" 543 }, 544 { 545 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 546 "Counter": "0,1,2,3", 547 "CounterHTOff": "0,1,2,3", 548 "EventCode": "0xD1", 549 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 550 "PEBS": "1", 551 "SampleAfterValue": "100007", 552 "UMask": "0x20" 553 }, 554 { 555 "BriefDescription": "All retired load uops. (Precise Event)", 556 "Counter": "0,1,2,3", 557 "CounterHTOff": "0,1,2,3", 558 "EventCode": "0xD0", 559 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 560 "PEBS": "1", 561 "SampleAfterValue": "2000003", 562 "UMask": "0x81" 563 }, 564 { 565 "BriefDescription": "All retired store uops. (Precise Event)", 566 "Counter": "0,1,2,3", 567 "CounterHTOff": "0,1,2,3", 568 "EventCode": "0xD0", 569 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 570 "PEBS": "1", 571 "SampleAfterValue": "2000003", 572 "UMask": "0x82" 573 }, 574 { 575 "BriefDescription": "Retired load uops with locked access. (Precise Event)", 576 "Counter": "0,1,2,3", 577 "CounterHTOff": "0,1,2,3", 578 "EventCode": "0xD0", 579 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 580 "PEBS": "1", 581 "SampleAfterValue": "100007", 582 "UMask": "0x21" 583 }, 584 { 585 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", 586 "Counter": "0,1,2,3", 587 "CounterHTOff": "0,1,2,3", 588 "EventCode": "0xD0", 589 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 590 "PEBS": "1", 591 "SampleAfterValue": "100003", 592 "UMask": "0x41" 593 }, 594 { 595 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", 596 "Counter": "0,1,2,3", 597 "CounterHTOff": "0,1,2,3", 598 "EventCode": "0xD0", 599 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 600 "PEBS": "1", 601 "SampleAfterValue": "100003", 602 "UMask": "0x42" 603 }, 604 { 605 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", 606 "Counter": "0,1,2,3", 607 "CounterHTOff": "0,1,2,3", 608 "EventCode": "0xD0", 609 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 610 "PEBS": "1", 611 "SampleAfterValue": "100003", 612 "UMask": "0x11" 613 }, 614 { 615 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", 616 "Counter": "0,1,2,3", 617 "CounterHTOff": "0,1,2,3", 618 "EventCode": "0xD0", 619 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 620 "PEBS": "1", 621 "SampleAfterValue": "100003", 622 "UMask": "0x12" 623 }, 624 { 625 "BriefDescription": "Demand and prefetch data reads", 626 "Counter": "0,1,2,3", 627 "CounterHTOff": "0,1,2,3,4,5,6,7", 628 "EventCode": "0xB0", 629 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 630 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 631 "SampleAfterValue": "100003", 632 "UMask": "0x8" 633 }, 634 { 635 "BriefDescription": "Cacheable and noncachaeble code read requests", 636 "Counter": "0,1,2,3", 637 "CounterHTOff": "0,1,2,3,4,5,6,7", 638 "EventCode": "0xB0", 639 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 640 "PublicDescription": "Demand code read requests sent to uncore.", 641 "SampleAfterValue": "100003", 642 "UMask": "0x2" 643 }, 644 { 645 "BriefDescription": "Demand Data Read requests sent to uncore", 646 "Counter": "0,1,2,3", 647 "CounterHTOff": "0,1,2,3,4,5,6,7", 648 "EventCode": "0xB0", 649 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 650 "PublicDescription": "Demand data read requests sent to uncore.", 651 "SampleAfterValue": "100003", 652 "UMask": "0x1" 653 }, 654 { 655 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 656 "Counter": "0,1,2,3", 657 "CounterHTOff": "0,1,2,3,4,5,6,7", 658 "EventCode": "0xB0", 659 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 660 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 661 "SampleAfterValue": "100003", 662 "UMask": "0x4" 663 }, 664 { 665 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", 666 "Counter": "0,1,2,3", 667 "CounterHTOff": "0,1,2,3,4,5,6,7", 668 "EventCode": "0xB2", 669 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 670 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", 671 "SampleAfterValue": "2000003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 676 "Counter": "0,1,2,3", 677 "CounterHTOff": "0,1,2,3,4,5,6,7", 678 "EventCode": "0x60", 679 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 680 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 681 "SampleAfterValue": "2000003", 682 "UMask": "0x8" 683 }, 684 { 685 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 686 "Counter": "0,1,2,3", 687 "CounterHTOff": "0,1,2,3,4,5,6,7", 688 "CounterMask": "1", 689 "EventCode": "0x60", 690 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 691 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 692 "SampleAfterValue": "2000003", 693 "UMask": "0x8" 694 }, 695 { 696 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 697 "Counter": "0,1,2,3", 698 "CounterHTOff": "0,1,2,3,4,5,6,7", 699 "CounterMask": "1", 700 "EventCode": "0x60", 701 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 702 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 703 "SampleAfterValue": "2000003", 704 "UMask": "0x2" 705 }, 706 { 707 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 708 "Counter": "0,1,2,3", 709 "CounterHTOff": "0,1,2,3,4,5,6,7", 710 "CounterMask": "1", 711 "EventCode": "0x60", 712 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 713 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 714 "SampleAfterValue": "2000003", 715 "UMask": "0x1" 716 }, 717 { 718 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 719 "Counter": "0,1,2,3", 720 "CounterHTOff": "0,1,2,3,4,5,6,7", 721 "CounterMask": "1", 722 "EventCode": "0x60", 723 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 724 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 725 "SampleAfterValue": "2000003", 726 "UMask": "0x4" 727 }, 728 { 729 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 730 "Counter": "0,1,2,3", 731 "CounterHTOff": "0,1,2,3,4,5,6,7", 732 "EventCode": "0x60", 733 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 734 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 735 "SampleAfterValue": "2000003", 736 "UMask": "0x2" 737 }, 738 { 739 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 740 "Counter": "0,1,2,3", 741 "CounterHTOff": "0,1,2,3,4,5,6,7", 742 "EventCode": "0x60", 743 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 744 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 745 "SampleAfterValue": "2000003", 746 "UMask": "0x1" 747 }, 748 { 749 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", 750 "Counter": "0,1,2,3", 751 "CounterHTOff": "0,1,2,3,4,5,6,7", 752 "CounterMask": "6", 753 "EventCode": "0x60", 754 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 755 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 756 "SampleAfterValue": "2000003", 757 "UMask": "0x1" 758 }, 759 { 760 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 761 "Counter": "0,1,2,3", 762 "CounterHTOff": "0,1,2,3,4,5,6,7", 763 "EventCode": "0x60", 764 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 765 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 766 "SampleAfterValue": "2000003", 767 "UMask": "0x4" 768 }, 769 { 770 "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", 771 "Counter": "0,1,2,3", 772 "CounterHTOff": "0,1,2,3", 773 "EventCode": "0xB7, 0xBB", 774 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", 775 "MSRIndex": "0x1a6,0x1a7", 776 "MSRValue": "0x3f803c0244", 777 "Offcore": "1", 778 "SampleAfterValue": "100003", 779 "UMask": "0x1" 780 }, 781 { 782 "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 783 "Counter": "0,1,2,3", 784 "CounterHTOff": "0,1,2,3", 785 "EventCode": "0xB7, 0xBB", 786 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 787 "MSRIndex": "0x1a6,0x1a7", 788 "MSRValue": "0x1003c0244", 789 "Offcore": "1", 790 "SampleAfterValue": "100003", 791 "UMask": "0x1" 792 }, 793 { 794 "BriefDescription": "Counts all demand & prefetch data reads", 795 "Counter": "0,1,2,3", 796 "CounterHTOff": "0,1,2,3", 797 "EventCode": "0xB7, 0xBB", 798 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", 799 "MSRIndex": "0x1a6,0x1a7", 800 "MSRValue": "0x000105B3", 801 "Offcore": "1", 802 "SampleAfterValue": "100003", 803 "UMask": "0x1" 804 }, 805 { 806 "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", 807 "Counter": "0,1,2,3", 808 "CounterHTOff": "0,1,2,3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x3f803c0091", 813 "Offcore": "1", 814 "SampleAfterValue": "100003", 815 "UMask": "0x1" 816 }, 817 { 818 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 819 "Counter": "0,1,2,3", 820 "CounterHTOff": "0,1,2,3", 821 "EventCode": "0xB7, 0xBB", 822 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 823 "MSRIndex": "0x1a6,0x1a7", 824 "MSRValue": "0x10003c0091", 825 "Offcore": "1", 826 "SampleAfterValue": "100003", 827 "UMask": "0x1" 828 }, 829 { 830 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 831 "Counter": "0,1,2,3", 832 "CounterHTOff": "0,1,2,3", 833 "EventCode": "0xB7, 0xBB", 834 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 835 "MSRIndex": "0x1a6,0x1a7", 836 "MSRValue": "0x4003c0091", 837 "Offcore": "1", 838 "SampleAfterValue": "100003", 839 "UMask": "0x1" 840 }, 841 { 842 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 843 "Counter": "0,1,2,3", 844 "CounterHTOff": "0,1,2,3", 845 "EventCode": "0xB7, 0xBB", 846 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 847 "MSRIndex": "0x1a6,0x1a7", 848 "MSRValue": "0x1003c0091", 849 "Offcore": "1", 850 "SampleAfterValue": "100003", 851 "UMask": "0x1" 852 }, 853 { 854 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", 855 "Counter": "0,1,2,3", 856 "CounterHTOff": "0,1,2,3", 857 "EventCode": "0xB7, 0xBB", 858 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", 859 "MSRIndex": "0x1a6,0x1a7", 860 "MSRValue": "0x000107F7", 861 "Offcore": "1", 862 "SampleAfterValue": "100003", 863 "UMask": "0x1" 864 }, 865 { 866 "BriefDescription": "Counts all demand & prefetch prefetch RFOs", 867 "Counter": "0,1,2,3", 868 "CounterHTOff": "0,1,2,3", 869 "EventCode": "0xB7, 0xBB", 870 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", 871 "MSRIndex": "0x1a6,0x1a7", 872 "MSRValue": "0x00010122", 873 "Offcore": "1", 874 "SampleAfterValue": "100003", 875 "UMask": "0x1" 876 }, 877 { 878 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", 879 "Counter": "0,1,2,3", 880 "CounterHTOff": "0,1,2,3", 881 "EventCode": "0xB7, 0xBB", 882 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", 883 "MSRIndex": "0x1a6,0x1a7", 884 "MSRValue": "0x3f803c0122", 885 "Offcore": "1", 886 "SampleAfterValue": "100003", 887 "UMask": "0x1" 888 }, 889 { 890 "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 891 "Counter": "0,1,2,3", 892 "CounterHTOff": "0,1,2,3", 893 "EventCode": "0xB7, 0xBB", 894 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", 895 "MSRIndex": "0x1a6,0x1a7", 896 "MSRValue": "0x1003c0122", 897 "Offcore": "1", 898 "SampleAfterValue": "100003", 899 "UMask": "0x1" 900 }, 901 { 902 "BriefDescription": "Counts all writebacks from the core to the LLC", 903 "Counter": "0,1,2,3", 904 "CounterHTOff": "0,1,2,3", 905 "EventCode": "0xB7, 0xBB", 906 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 907 "MSRIndex": "0x1a6,0x1a7", 908 "MSRValue": "0x10008", 909 "Offcore": "1", 910 "SampleAfterValue": "100003", 911 "UMask": "0x1" 912 }, 913 { 914 "BriefDescription": "Counts all demand code reads", 915 "Counter": "0,1,2,3", 916 "CounterHTOff": "0,1,2,3", 917 "EventCode": "0xB7, 0xBB", 918 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", 919 "MSRIndex": "0x1a6,0x1a7", 920 "MSRValue": "0x00010004", 921 "Offcore": "1", 922 "SampleAfterValue": "100003", 923 "UMask": "0x1" 924 }, 925 { 926 "BriefDescription": "Counts all demand code reads that hit in the LLC", 927 "Counter": "0,1,2,3", 928 "CounterHTOff": "0,1,2,3", 929 "EventCode": "0xB7, 0xBB", 930 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 931 "MSRIndex": "0x1a6,0x1a7", 932 "MSRValue": "0x3f803c0004", 933 "Offcore": "1", 934 "SampleAfterValue": "100003", 935 "UMask": "0x1" 936 }, 937 { 938 "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 939 "Counter": "0,1,2,3", 940 "CounterHTOff": "0,1,2,3", 941 "EventCode": "0xB7, 0xBB", 942 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 943 "MSRIndex": "0x1a6,0x1a7", 944 "MSRValue": "0x1003c0004", 945 "Offcore": "1", 946 "SampleAfterValue": "100003", 947 "UMask": "0x1" 948 }, 949 { 950 "BriefDescription": "Counts all demand data reads", 951 "Counter": "0,1,2,3", 952 "CounterHTOff": "0,1,2,3", 953 "EventCode": "0xB7, 0xBB", 954 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", 955 "MSRIndex": "0x1a6,0x1a7", 956 "MSRValue": "0x00010001", 957 "Offcore": "1", 958 "SampleAfterValue": "100003", 959 "UMask": "0x1" 960 }, 961 { 962 "BriefDescription": "Counts all demand data reads that hit in the LLC", 963 "Counter": "0,1,2,3", 964 "CounterHTOff": "0,1,2,3", 965 "EventCode": "0xB7, 0xBB", 966 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 967 "MSRIndex": "0x1a6,0x1a7", 968 "MSRValue": "0x3f803c0001", 969 "Offcore": "1", 970 "SampleAfterValue": "100003", 971 "UMask": "0x1" 972 }, 973 { 974 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 975 "Counter": "0,1,2,3", 976 "CounterHTOff": "0,1,2,3", 977 "EventCode": "0xB7, 0xBB", 978 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 979 "MSRIndex": "0x1a6,0x1a7", 980 "MSRValue": "0x10003c0001", 981 "Offcore": "1", 982 "SampleAfterValue": "100003", 983 "UMask": "0x1" 984 }, 985 { 986 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 987 "Counter": "0,1,2,3", 988 "CounterHTOff": "0,1,2,3", 989 "EventCode": "0xB7, 0xBB", 990 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 991 "MSRIndex": "0x1a6,0x1a7", 992 "MSRValue": "0x4003c0001", 993 "Offcore": "1", 994 "SampleAfterValue": "100003", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3", 1001 "EventCode": "0xB7, 0xBB", 1002 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "MSRValue": "0x1003c0001", 1005 "Offcore": "1", 1006 "SampleAfterValue": "100003", 1007 "UMask": "0x1" 1008 }, 1009 { 1010 "BriefDescription": "Counts all demand rfo's", 1011 "Counter": "0,1,2,3", 1012 "CounterHTOff": "0,1,2,3", 1013 "EventCode": "0xB7, 0xBB", 1014 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", 1015 "MSRIndex": "0x1a6,0x1a7", 1016 "MSRValue": "0x00010002", 1017 "Offcore": "1", 1018 "SampleAfterValue": "100003", 1019 "UMask": "0x1" 1020 }, 1021 { 1022 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", 1023 "Counter": "0,1,2,3", 1024 "CounterHTOff": "0,1,2,3", 1025 "EventCode": "0xB7, 0xBB", 1026 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "MSRValue": "0x3f803c0002", 1029 "Offcore": "1", 1030 "SampleAfterValue": "100003", 1031 "UMask": "0x1" 1032 }, 1033 { 1034 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1035 "Counter": "0,1,2,3", 1036 "CounterHTOff": "0,1,2,3", 1037 "EventCode": "0xB7, 0xBB", 1038 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 1039 "MSRIndex": "0x1a6,0x1a7", 1040 "MSRValue": "0x10003c0002", 1041 "Offcore": "1", 1042 "SampleAfterValue": "100003", 1043 "UMask": "0x1" 1044 }, 1045 { 1046 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1047 "Counter": "0,1,2,3", 1048 "CounterHTOff": "0,1,2,3", 1049 "EventCode": "0xB7, 0xBB", 1050 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", 1051 "MSRIndex": "0x1a6,0x1a7", 1052 "MSRValue": "0x1003c0002", 1053 "Offcore": "1", 1054 "SampleAfterValue": "100003", 1055 "UMask": "0x1" 1056 }, 1057 { 1058 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", 1059 "Counter": "0,1,2,3", 1060 "CounterHTOff": "0,1,2,3", 1061 "EventCode": "0xB7, 0xBB", 1062 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "MSRValue": "0x18000", 1065 "Offcore": "1", 1066 "SampleAfterValue": "100003", 1067 "UMask": "0x1" 1068 }, 1069 { 1070 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", 1071 "Counter": "0,1,2,3", 1072 "CounterHTOff": "0,1,2,3", 1073 "EventCode": "0xB7, 0xBB", 1074 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1075 "MSRIndex": "0x1a6,0x1a7", 1076 "MSRValue": "0x10400", 1077 "Offcore": "1", 1078 "SampleAfterValue": "100003", 1079 "UMask": "0x1" 1080 }, 1081 { 1082 "BriefDescription": "Counts non-temporal stores", 1083 "Counter": "0,1,2,3", 1084 "CounterHTOff": "0,1,2,3", 1085 "EventCode": "0xB7, 0xBB", 1086 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1087 "MSRIndex": "0x1a6,0x1a7", 1088 "MSRValue": "0x10800", 1089 "Offcore": "1", 1090 "SampleAfterValue": "100003", 1091 "UMask": "0x1" 1092 }, 1093 { 1094 "BriefDescription": "Split locks in SQ", 1095 "Counter": "0,1,2,3", 1096 "CounterHTOff": "0,1,2,3,4,5,6,7", 1097 "EventCode": "0xF4", 1098 "EventName": "SQ_MISC.SPLIT_LOCK", 1099 "SampleAfterValue": "100003", 1100 "UMask": "0x10" 1101 } 1102]