1[ 2 { 3 "CollectPEBSRecord": "2", 4 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 5 "EventCode": "0x54", 6 "Counter": "0,1,2,3", 7 "UMask": "0x1", 8 "PEBScounters": "0,1,2,3", 9 "EventName": "TX_MEM.ABORT_CONFLICT", 10 "SampleAfterValue": "2000003", 11 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address" 12 }, 13 { 14 "CollectPEBSRecord": "2", 15 "PublicDescription": "Speculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writes.", 16 "EventCode": "0x54", 17 "Counter": "0,1,2,3", 18 "UMask": "0x2", 19 "PEBScounters": "0,1,2,3", 20 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 21 "SampleAfterValue": "2000003", 22 "BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation for transactional writes." 23 }, 24 { 25 "CollectPEBSRecord": "2", 26 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 27 "EventCode": "0x54", 28 "Counter": "0,1,2,3", 29 "UMask": "0x4", 30 "PEBScounters": "0,1,2,3", 31 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 32 "SampleAfterValue": "100003", 33 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer" 34 }, 35 { 36 "CollectPEBSRecord": "2", 37 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 38 "EventCode": "0x54", 39 "Counter": "0,1,2,3", 40 "UMask": "0x8", 41 "PEBScounters": "0,1,2,3", 42 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 43 "SampleAfterValue": "2000003", 44 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero." 45 }, 46 { 47 "CollectPEBSRecord": "2", 48 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 49 "EventCode": "0x54", 50 "Counter": "0,1,2,3", 51 "UMask": "0x10", 52 "PEBScounters": "0,1,2,3", 53 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 54 "SampleAfterValue": "2000003", 55 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer" 56 }, 57 { 58 "CollectPEBSRecord": "2", 59 "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 60 "EventCode": "0x54", 61 "Counter": "0,1,2,3", 62 "UMask": "0x20", 63 "PEBScounters": "0,1,2,3", 64 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 65 "SampleAfterValue": "2000003", 66 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer." 67 }, 68 { 69 "CollectPEBSRecord": "2", 70 "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", 71 "EventCode": "0x54", 72 "Counter": "0,1,2,3", 73 "UMask": "0x40", 74 "PEBScounters": "0,1,2,3", 75 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 76 "SampleAfterValue": "2000003", 77 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero." 78 }, 79 { 80 "CollectPEBSRecord": "2", 81 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 82 "EventCode": "0x5d", 83 "Counter": "0,1,2,3,4,5,6,7", 84 "UMask": "0x2", 85 "PEBScounters": "0,1,2,3,4,5,6,7", 86 "EventName": "TX_EXEC.MISC2", 87 "SampleAfterValue": "2000003", 88 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region" 89 }, 90 { 91 "CollectPEBSRecord": "2", 92 "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 93 "EventCode": "0x5d", 94 "Counter": "0,1,2,3,4,5,6,7", 95 "UMask": "0x4", 96 "PEBScounters": "0,1,2,3,4,5,6,7", 97 "EventName": "TX_EXEC.MISC3", 98 "SampleAfterValue": "2000003", 99 "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded" 100 }, 101 { 102 "CollectPEBSRecord": "2", 103 "EventCode": "0xA3", 104 "Counter": "0,1,2,3", 105 "UMask": "0x2", 106 "PEBScounters": "0,1,2,3", 107 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 108 "SampleAfterValue": "2000003", 109 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 110 "CounterMask": "2" 111 }, 112 { 113 "CollectPEBSRecord": "2", 114 "EventCode": "0xA3", 115 "Counter": "0,1,2,3", 116 "UMask": "0x6", 117 "PEBScounters": "0,1,2,3", 118 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 119 "SampleAfterValue": "2000003", 120 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 121 "CounterMask": "6" 122 }, 123 { 124 "CollectPEBSRecord": "2", 125 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 126 "EventCode": "0xB0", 127 "Counter": "0,1,2,3", 128 "UMask": "0x10", 129 "PEBScounters": "0,1,2,3", 130 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 131 "SampleAfterValue": "100003", 132 "BriefDescription": "Demand Data Read requests who miss L3 cache" 133 }, 134 { 135 "CollectPEBSRecord": "2", 136 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 137 "EventCode": "0xc3", 138 "Counter": "0,1,2,3,4,5,6,7", 139 "UMask": "0x2", 140 "PEBScounters": "0,1,2,3,4,5,6,7", 141 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 142 "SampleAfterValue": "100003", 143 "BriefDescription": "Number of machine clears due to memory ordering conflicts." 144 }, 145 { 146 "CollectPEBSRecord": "2", 147 "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", 148 "EventCode": "0xC8", 149 "Counter": "0,1,2,3,4,5,6,7", 150 "UMask": "0x1", 151 "PEBScounters": "0,1,2,3,4,5,6,7", 152 "EventName": "HLE_RETIRED.START", 153 "SampleAfterValue": "2000003", 154 "BriefDescription": "Number of times an HLE execution started." 155 }, 156 { 157 "CollectPEBSRecord": "2", 158 "PublicDescription": "Counts the number of times HLE commit succeeded.", 159 "EventCode": "0xC8", 160 "Counter": "0,1,2,3,4,5,6,7", 161 "UMask": "0x2", 162 "PEBScounters": "0,1,2,3,4,5,6,7", 163 "EventName": "HLE_RETIRED.COMMIT", 164 "SampleAfterValue": "2000003", 165 "BriefDescription": "Number of times an HLE execution successfully committed", 166 "Data_LA": "1" 167 }, 168 { 169 "CollectPEBSRecord": "2", 170 "PublicDescription": "Counts the number of times HLE abort was triggered.", 171 "EventCode": "0xc8", 172 "Counter": "0,1,2,3,4,5,6,7", 173 "UMask": "0x4", 174 "PEBScounters": "0,1,2,3,4,5,6,7", 175 "EventName": "HLE_RETIRED.ABORTED", 176 "SampleAfterValue": "2000003", 177 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)." 178 }, 179 { 180 "CollectPEBSRecord": "2", 181 "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 182 "EventCode": "0xC8", 183 "Counter": "0,1,2,3,4,5,6,7", 184 "UMask": "0x8", 185 "PEBScounters": "0,1,2,3,4,5,6,7", 186 "EventName": "HLE_RETIRED.ABORTED_MEM", 187 "SampleAfterValue": "2000003", 188 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)." 189 }, 190 { 191 "CollectPEBSRecord": "2", 192 "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 193 "EventCode": "0xC8", 194 "Counter": "0,1,2,3,4,5,6,7", 195 "UMask": "0x20", 196 "PEBScounters": "0,1,2,3,4,5,6,7", 197 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 198 "SampleAfterValue": "2000003", 199 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)." 200 }, 201 { 202 "CollectPEBSRecord": "2", 203 "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 204 "EventCode": "0xC8", 205 "Counter": "0,1,2,3,4,5,6,7", 206 "UMask": "0x80", 207 "PEBScounters": "0,1,2,3,4,5,6,7", 208 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 209 "SampleAfterValue": "2000003", 210 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts)." 211 }, 212 { 213 "CollectPEBSRecord": "2", 214 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 215 "EventCode": "0xC9", 216 "Counter": "0,1,2,3,4,5,6,7", 217 "UMask": "0x1", 218 "PEBScounters": "0,1,2,3,4,5,6,7", 219 "EventName": "RTM_RETIRED.START", 220 "SampleAfterValue": "2000003", 221 "BriefDescription": "Number of times an RTM execution started." 222 }, 223 { 224 "CollectPEBSRecord": "2", 225 "PublicDescription": "Counts the number of times RTM commit succeeded.", 226 "EventCode": "0xC9", 227 "Counter": "0,1,2,3,4,5,6,7", 228 "UMask": "0x2", 229 "PEBScounters": "0,1,2,3,4,5,6,7", 230 "EventName": "RTM_RETIRED.COMMIT", 231 "SampleAfterValue": "2000003", 232 "BriefDescription": "Number of times an RTM execution successfully committed" 233 }, 234 { 235 "CollectPEBSRecord": "2", 236 "PublicDescription": "Counts the number of times RTM abort was triggered.", 237 "EventCode": "0xc9", 238 "Counter": "0,1,2,3,4,5,6,7", 239 "UMask": "0x4", 240 "PEBScounters": "0,1,2,3,4,5,6,7", 241 "EventName": "RTM_RETIRED.ABORTED", 242 "SampleAfterValue": "2000003", 243 "BriefDescription": "Number of times an RTM execution aborted.", 244 "Data_LA": "1" 245 }, 246 { 247 "CollectPEBSRecord": "2", 248 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 249 "EventCode": "0xC9", 250 "Counter": "0,1,2,3,4,5,6,7", 251 "UMask": "0x8", 252 "PEBScounters": "0,1,2,3,4,5,6,7", 253 "EventName": "RTM_RETIRED.ABORTED_MEM", 254 "SampleAfterValue": "2000003", 255 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)" 256 }, 257 { 258 "CollectPEBSRecord": "2", 259 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 260 "EventCode": "0xC9", 261 "Counter": "0,1,2,3,4,5,6,7", 262 "UMask": "0x20", 263 "PEBScounters": "0,1,2,3,4,5,6,7", 264 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 265 "SampleAfterValue": "2000003", 266 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions" 267 }, 268 { 269 "CollectPEBSRecord": "2", 270 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 271 "EventCode": "0xC9", 272 "Counter": "0,1,2,3,4,5,6,7", 273 "UMask": "0x40", 274 "PEBScounters": "0,1,2,3,4,5,6,7", 275 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 276 "SampleAfterValue": "2000003", 277 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type" 278 }, 279 { 280 "CollectPEBSRecord": "2", 281 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 282 "EventCode": "0xC9", 283 "Counter": "0,1,2,3,4,5,6,7", 284 "UMask": "0x80", 285 "PEBScounters": "0,1,2,3,4,5,6,7", 286 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 287 "SampleAfterValue": "2000003", 288 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)" 289 }, 290 { 291 "PEBS": "2", 292 "CollectPEBSRecord": "2", 293 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 294 "EventCode": "0xcd", 295 "MSRValue": "0x4", 296 "Counter": "0,1,2,3,4,5,6,7", 297 "UMask": "0x1", 298 "PEBScounters": "0,1,2,3,4,5,6,7", 299 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 300 "MSRIndex": "0x3F6", 301 "SampleAfterValue": "100003", 302 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 303 "TakenAlone": "1" 304 }, 305 { 306 "PEBS": "2", 307 "CollectPEBSRecord": "2", 308 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 309 "EventCode": "0xcd", 310 "MSRValue": "0x8", 311 "Counter": "0,1,2,3,4,5,6,7", 312 "UMask": "0x1", 313 "PEBScounters": "0,1,2,3,4,5,6,7", 314 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 315 "MSRIndex": "0x3F6", 316 "SampleAfterValue": "50021", 317 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 318 "TakenAlone": "1" 319 }, 320 { 321 "PEBS": "2", 322 "CollectPEBSRecord": "2", 323 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 324 "EventCode": "0xcd", 325 "MSRValue": "0x10", 326 "Counter": "0,1,2,3,4,5,6,7", 327 "UMask": "0x1", 328 "PEBScounters": "0,1,2,3,4,5,6,7", 329 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 330 "MSRIndex": "0x3F6", 331 "SampleAfterValue": "20011", 332 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 333 "TakenAlone": "1" 334 }, 335 { 336 "PEBS": "2", 337 "CollectPEBSRecord": "2", 338 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 339 "EventCode": "0xcd", 340 "MSRValue": "0x20", 341 "Counter": "0,1,2,3,4,5,6,7", 342 "UMask": "0x1", 343 "PEBScounters": "0,1,2,3,4,5,6,7", 344 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 345 "MSRIndex": "0x3F6", 346 "SampleAfterValue": "100007", 347 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 348 "TakenAlone": "1" 349 }, 350 { 351 "PEBS": "2", 352 "CollectPEBSRecord": "2", 353 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 354 "EventCode": "0xcd", 355 "MSRValue": "0x40", 356 "Counter": "0,1,2,3,4,5,6,7", 357 "UMask": "0x1", 358 "PEBScounters": "0,1,2,3,4,5,6,7", 359 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 360 "MSRIndex": "0x3F6", 361 "SampleAfterValue": "2003", 362 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 363 "TakenAlone": "1" 364 }, 365 { 366 "PEBS": "2", 367 "CollectPEBSRecord": "2", 368 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 369 "EventCode": "0xcd", 370 "MSRValue": "0x80", 371 "Counter": "0,1,2,3,4,5,6,7", 372 "UMask": "0x1", 373 "PEBScounters": "0,1,2,3,4,5,6,7", 374 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 375 "MSRIndex": "0x3F6", 376 "SampleAfterValue": "1009", 377 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 378 "TakenAlone": "1" 379 }, 380 { 381 "PEBS": "2", 382 "CollectPEBSRecord": "2", 383 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 384 "EventCode": "0xcd", 385 "MSRValue": "0x100", 386 "Counter": "0,1,2,3,4,5,6,7", 387 "UMask": "0x1", 388 "PEBScounters": "0,1,2,3,4,5,6,7", 389 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 390 "MSRIndex": "0x3F6", 391 "SampleAfterValue": "503", 392 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 393 "TakenAlone": "1" 394 }, 395 { 396 "PEBS": "2", 397 "CollectPEBSRecord": "2", 398 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 399 "EventCode": "0xcd", 400 "MSRValue": "0x200", 401 "Counter": "0,1,2,3,4,5,6,7", 402 "UMask": "0x1", 403 "PEBScounters": "0,1,2,3,4,5,6,7", 404 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 405 "MSRIndex": "0x3F6", 406 "SampleAfterValue": "101", 407 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 408 "TakenAlone": "1" 409 } 410]