xref: /freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/other.json (revision 18054d0220cfc8df9c9568c437bd6fbb59d53c3c) 
1959826caSMatt Macy[
2959826caSMatt Macy    {
3959826caSMatt Macy        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
4959826caSMatt Macy        "Counter": "0,1,2,3",
5*18054d02SAlexander Motin        "CounterHTOff": "0,1,2,3,4,5,6,7",
6*18054d02SAlexander Motin        "EventCode": "0x5C",
7959826caSMatt Macy        "EventName": "CPL_CYCLES.RING0",
8959826caSMatt Macy        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
9959826caSMatt Macy        "SampleAfterValue": "2000003",
10*18054d02SAlexander Motin        "UMask": "0x1"
11959826caSMatt Macy    },
12959826caSMatt Macy    {
13959826caSMatt Macy        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
14959826caSMatt Macy        "Counter": "0,1,2,3",
15*18054d02SAlexander Motin        "CounterHTOff": "0,1,2,3,4,5,6,7",
16959826caSMatt Macy        "CounterMask": "1",
17*18054d02SAlexander Motin        "EdgeDetect": "1",
18*18054d02SAlexander Motin        "EventCode": "0x5C",
19*18054d02SAlexander Motin        "EventName": "CPL_CYCLES.RING0_TRANS",
20959826caSMatt Macy        "SampleAfterValue": "100003",
21*18054d02SAlexander Motin        "UMask": "0x1"
22959826caSMatt Macy    },
23959826caSMatt Macy    {
24959826caSMatt Macy        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
25959826caSMatt Macy        "Counter": "0,1,2,3",
26*18054d02SAlexander Motin        "CounterHTOff": "0,1,2,3,4,5,6,7",
27*18054d02SAlexander Motin        "EventCode": "0x5C",
28959826caSMatt Macy        "EventName": "CPL_CYCLES.RING123",
29959826caSMatt Macy        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
30959826caSMatt Macy        "SampleAfterValue": "2000003",
31*18054d02SAlexander Motin        "UMask": "0x2"
32959826caSMatt Macy    },
33959826caSMatt Macy    {
34959826caSMatt Macy        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
35959826caSMatt Macy        "Counter": "0,1,2,3",
36*18054d02SAlexander Motin        "CounterHTOff": "0,1,2,3,4,5,6,7",
37*18054d02SAlexander Motin        "EventCode": "0x63",
38959826caSMatt Macy        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
39959826caSMatt Macy        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
40959826caSMatt Macy        "SampleAfterValue": "2000003",
41*18054d02SAlexander Motin        "UMask": "0x1"
42959826caSMatt Macy    }
43959826caSMatt Macy]