1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x51", 7 "EventName": "L1D.REPLACEMENT", 8 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EventCode": "0x48", 18 "EventName": "L1D_PEND_MISS.FB_FULL", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x2" 21 }, 22 { 23 "BriefDescription": "L1D miss oustandings duration in cycles", 24 "Counter": "2", 25 "CounterHTOff": "2", 26 "EventCode": "0x48", 27 "EventName": "L1D_PEND_MISS.PENDING", 28 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "Cycles with L1D load Misses outstanding.", 34 "Counter": "2", 35 "CounterHTOff": "2", 36 "CounterMask": "1", 37 "EventCode": "0x48", 38 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x1" 41 }, 42 { 43 "AnyThread": "1", 44 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 45 "Counter": "2", 46 "CounterHTOff": "2", 47 "CounterMask": "1", 48 "EventCode": "0x48", 49 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0x48", 58 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x2" 61 }, 62 { 63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0x27", 67 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 69 "SampleAfterValue": "200003", 70 "UMask": "0x50" 71 }, 72 { 73 "BriefDescription": "L2 cache lines filling L2", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "EventCode": "0xF1", 77 "EventName": "L2_LINES_IN.ALL", 78 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 79 "SampleAfterValue": "100003", 80 "UMask": "0x7" 81 }, 82 { 83 "BriefDescription": "L2 cache lines in E state filling L2", 84 "Counter": "0,1,2,3", 85 "CounterHTOff": "0,1,2,3,4,5,6,7", 86 "EventCode": "0xF1", 87 "EventName": "L2_LINES_IN.E", 88 "PublicDescription": "L2 cache lines in E state filling L2.", 89 "SampleAfterValue": "100003", 90 "UMask": "0x4" 91 }, 92 { 93 "BriefDescription": "L2 cache lines in I state filling L2", 94 "Counter": "0,1,2,3", 95 "CounterHTOff": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xF1", 97 "EventName": "L2_LINES_IN.I", 98 "PublicDescription": "L2 cache lines in I state filling L2.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "L2 cache lines in S state filling L2", 104 "Counter": "0,1,2,3", 105 "CounterHTOff": "0,1,2,3,4,5,6,7", 106 "EventCode": "0xF1", 107 "EventName": "L2_LINES_IN.S", 108 "PublicDescription": "L2 cache lines in S state filling L2.", 109 "SampleAfterValue": "100003", 110 "UMask": "0x2" 111 }, 112 { 113 "BriefDescription": "Clean L2 cache lines evicted by demand", 114 "Counter": "0,1,2,3", 115 "CounterHTOff": "0,1,2,3,4,5,6,7", 116 "EventCode": "0xF2", 117 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 118 "PublicDescription": "Clean L2 cache lines evicted by demand.", 119 "SampleAfterValue": "100003", 120 "UMask": "0x5" 121 }, 122 { 123 "BriefDescription": "Dirty L2 cache lines evicted by demand", 124 "Counter": "0,1,2,3", 125 "CounterHTOff": "0,1,2,3,4,5,6,7", 126 "EventCode": "0xF2", 127 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 128 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 129 "SampleAfterValue": "100003", 130 "UMask": "0x6" 131 }, 132 { 133 "BriefDescription": "L2 code requests", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3,4,5,6,7", 136 "EventCode": "0x24", 137 "EventName": "L2_RQSTS.ALL_CODE_RD", 138 "PublicDescription": "Counts all L2 code requests.", 139 "SampleAfterValue": "200003", 140 "UMask": "0xe4" 141 }, 142 { 143 "BriefDescription": "Demand Data Read requests", 144 "Counter": "0,1,2,3", 145 "CounterHTOff": "0,1,2,3,4,5,6,7", 146 "Errata": "HSD78, HSM80", 147 "EventCode": "0x24", 148 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 150 "SampleAfterValue": "200003", 151 "UMask": "0xe1" 152 }, 153 { 154 "BriefDescription": "Demand requests that miss L2 cache", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "Errata": "HSD78, HSM80", 158 "EventCode": "0x24", 159 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 160 "PublicDescription": "Demand requests that miss L2 cache.", 161 "SampleAfterValue": "200003", 162 "UMask": "0x27" 163 }, 164 { 165 "BriefDescription": "Demand requests to L2 cache", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3,4,5,6,7", 168 "Errata": "HSD78, HSM80", 169 "EventCode": "0x24", 170 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 171 "PublicDescription": "Demand requests to L2 cache.", 172 "SampleAfterValue": "200003", 173 "UMask": "0xe7" 174 }, 175 { 176 "BriefDescription": "Requests from L2 hardware prefetchers", 177 "Counter": "0,1,2,3", 178 "CounterHTOff": "0,1,2,3,4,5,6,7", 179 "EventCode": "0x24", 180 "EventName": "L2_RQSTS.ALL_PF", 181 "PublicDescription": "Counts all L2 HW prefetcher requests.", 182 "SampleAfterValue": "200003", 183 "UMask": "0xf8" 184 }, 185 { 186 "BriefDescription": "RFO requests to L2 cache", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3,4,5,6,7", 189 "EventCode": "0x24", 190 "EventName": "L2_RQSTS.ALL_RFO", 191 "PublicDescription": "Counts all L2 store RFO requests.", 192 "SampleAfterValue": "200003", 193 "UMask": "0xe2" 194 }, 195 { 196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 197 "Counter": "0,1,2,3", 198 "CounterHTOff": "0,1,2,3,4,5,6,7", 199 "EventCode": "0x24", 200 "EventName": "L2_RQSTS.CODE_RD_HIT", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 202 "SampleAfterValue": "200003", 203 "UMask": "0xc4" 204 }, 205 { 206 "BriefDescription": "L2 cache misses when fetching instructions", 207 "Counter": "0,1,2,3", 208 "CounterHTOff": "0,1,2,3,4,5,6,7", 209 "EventCode": "0x24", 210 "EventName": "L2_RQSTS.CODE_RD_MISS", 211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 212 "SampleAfterValue": "200003", 213 "UMask": "0x24" 214 }, 215 { 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3,4,5,6,7", 219 "Errata": "HSD78, HSM80", 220 "EventCode": "0x24", 221 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 222 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 223 "SampleAfterValue": "200003", 224 "UMask": "0xc1" 225 }, 226 { 227 "BriefDescription": "Demand Data Read miss L2, no rejects", 228 "Counter": "0,1,2,3", 229 "CounterHTOff": "0,1,2,3,4,5,6,7", 230 "Errata": "HSD78, HSM80", 231 "EventCode": "0x24", 232 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 233 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 234 "SampleAfterValue": "200003", 235 "UMask": "0x21" 236 }, 237 { 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 239 "Counter": "0,1,2,3", 240 "CounterHTOff": "0,1,2,3,4,5,6,7", 241 "EventCode": "0x24", 242 "EventName": "L2_RQSTS.L2_PF_HIT", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 244 "SampleAfterValue": "200003", 245 "UMask": "0xd0" 246 }, 247 { 248 "BriefDescription": "L2 prefetch requests that miss L2 cache", 249 "Counter": "0,1,2,3", 250 "CounterHTOff": "0,1,2,3,4,5,6,7", 251 "EventCode": "0x24", 252 "EventName": "L2_RQSTS.L2_PF_MISS", 253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 254 "SampleAfterValue": "200003", 255 "UMask": "0x30" 256 }, 257 { 258 "BriefDescription": "All requests that miss L2 cache", 259 "Counter": "0,1,2,3", 260 "CounterHTOff": "0,1,2,3,4,5,6,7", 261 "Errata": "HSD78, HSM80", 262 "EventCode": "0x24", 263 "EventName": "L2_RQSTS.MISS", 264 "PublicDescription": "All requests that missed L2.", 265 "SampleAfterValue": "200003", 266 "UMask": "0x3f" 267 }, 268 { 269 "BriefDescription": "All L2 requests", 270 "Counter": "0,1,2,3", 271 "CounterHTOff": "0,1,2,3,4,5,6,7", 272 "Errata": "HSD78, HSM80", 273 "EventCode": "0x24", 274 "EventName": "L2_RQSTS.REFERENCES", 275 "PublicDescription": "All requests to L2 cache.", 276 "SampleAfterValue": "200003", 277 "UMask": "0xff" 278 }, 279 { 280 "BriefDescription": "RFO requests that hit L2 cache", 281 "Counter": "0,1,2,3", 282 "CounterHTOff": "0,1,2,3,4,5,6,7", 283 "EventCode": "0x24", 284 "EventName": "L2_RQSTS.RFO_HIT", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 286 "SampleAfterValue": "200003", 287 "UMask": "0xc2" 288 }, 289 { 290 "BriefDescription": "RFO requests that miss L2 cache", 291 "Counter": "0,1,2,3", 292 "CounterHTOff": "0,1,2,3,4,5,6,7", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.RFO_MISS", 295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 296 "SampleAfterValue": "200003", 297 "UMask": "0x22" 298 }, 299 { 300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 301 "Counter": "0,1,2,3", 302 "CounterHTOff": "0,1,2,3,4,5,6,7", 303 "EventCode": "0xf0", 304 "EventName": "L2_TRANS.ALL_PF", 305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 306 "SampleAfterValue": "200003", 307 "UMask": "0x8" 308 }, 309 { 310 "BriefDescription": "Transactions accessing L2 pipe", 311 "Counter": "0,1,2,3", 312 "CounterHTOff": "0,1,2,3,4,5,6,7", 313 "EventCode": "0xf0", 314 "EventName": "L2_TRANS.ALL_REQUESTS", 315 "PublicDescription": "Transactions accessing L2 pipe.", 316 "SampleAfterValue": "200003", 317 "UMask": "0x80" 318 }, 319 { 320 "BriefDescription": "L2 cache accesses when fetching instructions", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3,4,5,6,7", 323 "EventCode": "0xf0", 324 "EventName": "L2_TRANS.CODE_RD", 325 "PublicDescription": "L2 cache accesses when fetching instructions.", 326 "SampleAfterValue": "200003", 327 "UMask": "0x4" 328 }, 329 { 330 "BriefDescription": "Demand Data Read requests that access L2 cache", 331 "Counter": "0,1,2,3", 332 "CounterHTOff": "0,1,2,3,4,5,6,7", 333 "EventCode": "0xf0", 334 "EventName": "L2_TRANS.DEMAND_DATA_RD", 335 "PublicDescription": "Demand data read requests that access L2 cache.", 336 "SampleAfterValue": "200003", 337 "UMask": "0x1" 338 }, 339 { 340 "BriefDescription": "L1D writebacks that access L2 cache", 341 "Counter": "0,1,2,3", 342 "CounterHTOff": "0,1,2,3,4,5,6,7", 343 "EventCode": "0xf0", 344 "EventName": "L2_TRANS.L1D_WB", 345 "PublicDescription": "L1D writebacks that access L2 cache.", 346 "SampleAfterValue": "200003", 347 "UMask": "0x10" 348 }, 349 { 350 "BriefDescription": "L2 fill requests that access L2 cache", 351 "Counter": "0,1,2,3", 352 "CounterHTOff": "0,1,2,3,4,5,6,7", 353 "EventCode": "0xf0", 354 "EventName": "L2_TRANS.L2_FILL", 355 "PublicDescription": "L2 fill requests that access L2 cache.", 356 "SampleAfterValue": "200003", 357 "UMask": "0x20" 358 }, 359 { 360 "BriefDescription": "L2 writebacks that access L2 cache", 361 "Counter": "0,1,2,3", 362 "CounterHTOff": "0,1,2,3,4,5,6,7", 363 "EventCode": "0xf0", 364 "EventName": "L2_TRANS.L2_WB", 365 "PublicDescription": "L2 writebacks that access L2 cache.", 366 "SampleAfterValue": "200003", 367 "UMask": "0x40" 368 }, 369 { 370 "BriefDescription": "RFO requests that access L2 cache", 371 "Counter": "0,1,2,3", 372 "CounterHTOff": "0,1,2,3,4,5,6,7", 373 "EventCode": "0xf0", 374 "EventName": "L2_TRANS.RFO", 375 "PublicDescription": "RFO requests that access L2 cache.", 376 "SampleAfterValue": "200003", 377 "UMask": "0x2" 378 }, 379 { 380 "BriefDescription": "Cycles when L1D is locked", 381 "Counter": "0,1,2,3", 382 "CounterHTOff": "0,1,2,3,4,5,6,7", 383 "EventCode": "0x63", 384 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 385 "PublicDescription": "Cycles in which the L1D is locked.", 386 "SampleAfterValue": "2000003", 387 "UMask": "0x2" 388 }, 389 { 390 "BriefDescription": "Core-originated cacheable demand requests missed L3", 391 "Counter": "0,1,2,3", 392 "CounterHTOff": "0,1,2,3,4,5,6,7", 393 "EventCode": "0x2E", 394 "EventName": "LONGEST_LAT_CACHE.MISS", 395 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 396 "SampleAfterValue": "100003", 397 "UMask": "0x41" 398 }, 399 { 400 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 401 "Counter": "0,1,2,3", 402 "CounterHTOff": "0,1,2,3,4,5,6,7", 403 "EventCode": "0x2E", 404 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 405 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 406 "SampleAfterValue": "100003", 407 "UMask": "0x4f" 408 }, 409 { 410 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", 411 "Counter": "0,1,2,3", 412 "CounterHTOff": "0,1,2,3", 413 "Data_LA": "1", 414 "Errata": "HSD29, HSD25, HSM26, HSM30", 415 "EventCode": "0xD2", 416 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 417 "PEBS": "1", 418 "SampleAfterValue": "20011", 419 "UMask": "0x2" 420 }, 421 { 422 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", 423 "Counter": "0,1,2,3", 424 "CounterHTOff": "0,1,2,3", 425 "Data_LA": "1", 426 "Errata": "HSD29, HSD25, HSM26, HSM30", 427 "EventCode": "0xD2", 428 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 429 "PEBS": "1", 430 "SampleAfterValue": "20011", 431 "UMask": "0x4" 432 }, 433 { 434 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 435 "Counter": "0,1,2,3", 436 "CounterHTOff": "0,1,2,3", 437 "Data_LA": "1", 438 "Errata": "HSD29, HSD25, HSM26, HSM30", 439 "EventCode": "0xD2", 440 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 441 "PEBS": "1", 442 "SampleAfterValue": "20011", 443 "UMask": "0x1" 444 }, 445 { 446 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 447 "Counter": "0,1,2,3", 448 "CounterHTOff": "0,1,2,3", 449 "Data_LA": "1", 450 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 451 "EventCode": "0xD2", 452 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 453 "PEBS": "1", 454 "SampleAfterValue": "100003", 455 "UMask": "0x8" 456 }, 457 { 458 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 459 "Counter": "0,1,2,3", 460 "CounterHTOff": "0,1,2,3", 461 "Data_LA": "1", 462 "Errata": "HSD74, HSD29, HSD25, HSM30", 463 "EventCode": "0xD3", 464 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 465 "PEBS": "1", 466 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", 467 "SampleAfterValue": "100003", 468 "UMask": "0x1" 469 }, 470 { 471 "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", 472 "Counter": "0,1,2,3", 473 "CounterHTOff": "0,1,2,3", 474 "Data_LA": "1", 475 "Errata": "HSD29, HSM30", 476 "EventCode": "0xD3", 477 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", 478 "PEBS": "1", 479 "SampleAfterValue": "100003", 480 "UMask": "0x4" 481 }, 482 { 483 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", 484 "Counter": "0,1,2,3", 485 "CounterHTOff": "0,1,2,3", 486 "Data_LA": "1", 487 "Errata": "HSM30", 488 "EventCode": "0xD3", 489 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", 490 "PEBS": "1", 491 "SampleAfterValue": "100003", 492 "UMask": "0x20" 493 }, 494 { 495 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", 496 "Counter": "0,1,2,3", 497 "CounterHTOff": "0,1,2,3", 498 "Data_LA": "1", 499 "Errata": "HSM30", 500 "EventCode": "0xD3", 501 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", 502 "PEBS": "1", 503 "SampleAfterValue": "100003", 504 "UMask": "0x10" 505 }, 506 { 507 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 508 "Counter": "0,1,2,3", 509 "CounterHTOff": "0,1,2,3", 510 "Data_LA": "1", 511 "Errata": "HSM30", 512 "EventCode": "0xD1", 513 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 514 "PEBS": "1", 515 "SampleAfterValue": "100003", 516 "UMask": "0x40" 517 }, 518 { 519 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 520 "Counter": "0,1,2,3", 521 "CounterHTOff": "0,1,2,3", 522 "Data_LA": "1", 523 "Errata": "HSD29, HSM30", 524 "EventCode": "0xD1", 525 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 526 "PEBS": "1", 527 "SampleAfterValue": "2000003", 528 "UMask": "0x1" 529 }, 530 { 531 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 532 "Counter": "0,1,2,3", 533 "CounterHTOff": "0,1,2,3", 534 "Data_LA": "1", 535 "Errata": "HSM30", 536 "EventCode": "0xD1", 537 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 538 "PEBS": "1", 539 "PublicDescription": "Retired load uops missed L1 cache as data sources.", 540 "SampleAfterValue": "100003", 541 "UMask": "0x8" 542 }, 543 { 544 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 545 "Counter": "0,1,2,3", 546 "CounterHTOff": "0,1,2,3", 547 "Data_LA": "1", 548 "Errata": "HSD76, HSD29, HSM30", 549 "EventCode": "0xD1", 550 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 551 "PEBS": "1", 552 "SampleAfterValue": "100003", 553 "UMask": "0x2" 554 }, 555 { 556 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 557 "Counter": "0,1,2,3", 558 "CounterHTOff": "0,1,2,3", 559 "Data_LA": "1", 560 "Errata": "HSD29, HSM30", 561 "EventCode": "0xD1", 562 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 563 "PEBS": "1", 564 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", 565 "SampleAfterValue": "50021", 566 "UMask": "0x10" 567 }, 568 { 569 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", 570 "Counter": "0,1,2,3", 571 "CounterHTOff": "0,1,2,3", 572 "Data_LA": "1", 573 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 574 "EventCode": "0xD1", 575 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 576 "PEBS": "1", 577 "PublicDescription": "Retired load uops with L3 cache hits as data sources.", 578 "SampleAfterValue": "50021", 579 "UMask": "0x4" 580 }, 581 { 582 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3", 585 "Data_LA": "1", 586 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 587 "EventCode": "0xD1", 588 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 589 "PEBS": "1", 590 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", 591 "SampleAfterValue": "100003", 592 "UMask": "0x20" 593 }, 594 { 595 "BriefDescription": "All retired load uops.", 596 "Counter": "0,1,2,3", 597 "CounterHTOff": "0,1,2,3", 598 "Data_LA": "1", 599 "Errata": "HSD29, HSM30", 600 "EventCode": "0xD0", 601 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 602 "PEBS": "1", 603 "SampleAfterValue": "2000003", 604 "UMask": "0x81" 605 }, 606 { 607 "BriefDescription": "All retired store uops.", 608 "Counter": "0,1,2,3", 609 "CounterHTOff": "0,1,2,3", 610 "Data_LA": "1", 611 "Errata": "HSD29, HSM30", 612 "EventCode": "0xD0", 613 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 614 "L1_Hit_Indication": "1", 615 "PEBS": "1", 616 "SampleAfterValue": "2000003", 617 "UMask": "0x82" 618 }, 619 { 620 "BriefDescription": "Retired load uops with locked access.", 621 "Counter": "0,1,2,3", 622 "CounterHTOff": "0,1,2,3", 623 "Data_LA": "1", 624 "Errata": "HSD76, HSD29, HSM30", 625 "EventCode": "0xD0", 626 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 627 "PEBS": "1", 628 "SampleAfterValue": "100003", 629 "UMask": "0x21" 630 }, 631 { 632 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 633 "Counter": "0,1,2,3", 634 "CounterHTOff": "0,1,2,3", 635 "Data_LA": "1", 636 "Errata": "HSD29, HSM30", 637 "EventCode": "0xD0", 638 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 639 "PEBS": "1", 640 "SampleAfterValue": "100003", 641 "UMask": "0x41" 642 }, 643 { 644 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 645 "Counter": "0,1,2,3", 646 "CounterHTOff": "0,1,2,3", 647 "Data_LA": "1", 648 "Errata": "HSD29, HSM30", 649 "EventCode": "0xD0", 650 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 651 "L1_Hit_Indication": "1", 652 "PEBS": "1", 653 "SampleAfterValue": "100003", 654 "UMask": "0x42" 655 }, 656 { 657 "BriefDescription": "Retired load uops that miss the STLB.", 658 "Counter": "0,1,2,3", 659 "CounterHTOff": "0,1,2,3", 660 "Data_LA": "1", 661 "Errata": "HSD29, HSM30", 662 "EventCode": "0xD0", 663 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 664 "PEBS": "1", 665 "SampleAfterValue": "100003", 666 "UMask": "0x11" 667 }, 668 { 669 "BriefDescription": "Retired store uops that miss the STLB.", 670 "Counter": "0,1,2,3", 671 "CounterHTOff": "0,1,2,3", 672 "Data_LA": "1", 673 "Errata": "HSD29, HSM30", 674 "EventCode": "0xD0", 675 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 676 "L1_Hit_Indication": "1", 677 "PEBS": "1", 678 "SampleAfterValue": "100003", 679 "UMask": "0x12" 680 }, 681 { 682 "BriefDescription": "Demand and prefetch data reads", 683 "Counter": "0,1,2,3", 684 "CounterHTOff": "0,1,2,3,4,5,6,7", 685 "EventCode": "0xB0", 686 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 687 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 688 "SampleAfterValue": "100003", 689 "UMask": "0x8" 690 }, 691 { 692 "BriefDescription": "Cacheable and noncachaeble code read requests", 693 "Counter": "0,1,2,3", 694 "CounterHTOff": "0,1,2,3,4,5,6,7", 695 "EventCode": "0xB0", 696 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 697 "PublicDescription": "Demand code read requests sent to uncore.", 698 "SampleAfterValue": "100003", 699 "UMask": "0x2" 700 }, 701 { 702 "BriefDescription": "Demand Data Read requests sent to uncore", 703 "Counter": "0,1,2,3", 704 "CounterHTOff": "0,1,2,3,4,5,6,7", 705 "Errata": "HSD78, HSM80", 706 "EventCode": "0xb0", 707 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 708 "PublicDescription": "Demand data read requests sent to uncore.", 709 "SampleAfterValue": "100003", 710 "UMask": "0x1" 711 }, 712 { 713 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 714 "Counter": "0,1,2,3", 715 "CounterHTOff": "0,1,2,3,4,5,6,7", 716 "EventCode": "0xB0", 717 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 718 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 719 "SampleAfterValue": "100003", 720 "UMask": "0x4" 721 }, 722 { 723 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 724 "Counter": "0,1,2,3", 725 "CounterHTOff": "0,1,2,3,4,5,6,7", 726 "EventCode": "0xb2", 727 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 728 "SampleAfterValue": "2000003", 729 "UMask": "0x1" 730 }, 731 { 732 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 733 "Counter": "0,1,2,3", 734 "CounterHTOff": "0,1,2,3,4,5,6,7", 735 "Errata": "HSD62, HSD61, HSM63", 736 "EventCode": "0x60", 737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 738 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 739 "SampleAfterValue": "2000003", 740 "UMask": "0x8" 741 }, 742 { 743 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 744 "Counter": "0,1,2,3", 745 "CounterHTOff": "0,1,2,3,4,5,6,7", 746 "CounterMask": "1", 747 "Errata": "HSD62, HSD61, HSM63", 748 "EventCode": "0x60", 749 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 750 "SampleAfterValue": "2000003", 751 "UMask": "0x8" 752 }, 753 { 754 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 755 "Counter": "0,1,2,3", 756 "CounterHTOff": "0,1,2,3,4,5,6,7", 757 "CounterMask": "1", 758 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 759 "EventCode": "0x60", 760 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 761 "SampleAfterValue": "2000003", 762 "UMask": "0x1" 763 }, 764 { 765 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 766 "Counter": "0,1,2,3", 767 "CounterHTOff": "0,1,2,3,4,5,6,7", 768 "CounterMask": "1", 769 "Errata": "HSD62, HSD61, HSM63", 770 "EventCode": "0x60", 771 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 772 "SampleAfterValue": "2000003", 773 "UMask": "0x4" 774 }, 775 { 776 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 777 "Counter": "0,1,2,3", 778 "CounterHTOff": "0,1,2,3,4,5,6,7", 779 "Errata": "HSD62, HSD61, HSM63", 780 "EventCode": "0x60", 781 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 782 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 783 "SampleAfterValue": "2000003", 784 "UMask": "0x2" 785 }, 786 { 787 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 788 "Counter": "0,1,2,3", 789 "CounterHTOff": "0,1,2,3,4,5,6,7", 790 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 791 "EventCode": "0x60", 792 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 793 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 794 "SampleAfterValue": "2000003", 795 "UMask": "0x1" 796 }, 797 { 798 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 799 "Counter": "0,1,2,3", 800 "CounterHTOff": "0,1,2,3,4,5,6,7", 801 "CounterMask": "6", 802 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 803 "EventCode": "0x60", 804 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 805 "SampleAfterValue": "2000003", 806 "UMask": "0x1" 807 }, 808 { 809 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 810 "Counter": "0,1,2,3", 811 "CounterHTOff": "0,1,2,3,4,5,6,7", 812 "Errata": "HSD62, HSD61, HSM63", 813 "EventCode": "0x60", 814 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 815 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 816 "SampleAfterValue": "2000003", 817 "UMask": "0x4" 818 }, 819 { 820 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 821 "Counter": "0,1,2,3", 822 "CounterHTOff": "0,1,2,3", 823 "EventCode": "0xB7, 0xBB", 824 "EventName": "OFFCORE_RESPONSE", 825 "SampleAfterValue": "100003", 826 "UMask": "0x1" 827 }, 828 { 829 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 830 "Counter": "0,1,2,3", 831 "CounterHTOff": "0,1,2,3", 832 "EventCode": "0xB7, 0xBB", 833 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 834 "MSRIndex": "0x1a6,0x1a7", 835 "MSRValue": "0x04003C0244", 836 "Offcore": "1", 837 "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 838 "SampleAfterValue": "100003", 839 "UMask": "0x1" 840 }, 841 { 842 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 843 "Counter": "0,1,2,3", 844 "CounterHTOff": "0,1,2,3", 845 "EventCode": "0xB7, 0xBB", 846 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 847 "MSRIndex": "0x1a6,0x1a7", 848 "MSRValue": "0x10003C0091", 849 "Offcore": "1", 850 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 856 "Counter": "0,1,2,3", 857 "CounterHTOff": "0,1,2,3", 858 "EventCode": "0xB7, 0xBB", 859 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 860 "MSRIndex": "0x1a6,0x1a7", 861 "MSRValue": "0x04003C0091", 862 "Offcore": "1", 863 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 864 "SampleAfterValue": "100003", 865 "UMask": "0x1" 866 }, 867 { 868 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 869 "Counter": "0,1,2,3", 870 "CounterHTOff": "0,1,2,3", 871 "EventCode": "0xB7, 0xBB", 872 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 873 "MSRIndex": "0x1a6,0x1a7", 874 "MSRValue": "0x10003C07F7", 875 "Offcore": "1", 876 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 877 "SampleAfterValue": "100003", 878 "UMask": "0x1" 879 }, 880 { 881 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 882 "Counter": "0,1,2,3", 883 "CounterHTOff": "0,1,2,3", 884 "EventCode": "0xB7, 0xBB", 885 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 886 "MSRIndex": "0x1a6,0x1a7", 887 "MSRValue": "0x04003C07F7", 888 "Offcore": "1", 889 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 890 "SampleAfterValue": "100003", 891 "UMask": "0x1" 892 }, 893 { 894 "BriefDescription": "Counts all requests hit in the L3", 895 "Counter": "0,1,2,3", 896 "CounterHTOff": "0,1,2,3", 897 "EventCode": "0xB7, 0xBB", 898 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0x3F803C8FFF", 901 "Offcore": "1", 902 "PublicDescription": "Counts all requests hit in the L3", 903 "SampleAfterValue": "100003", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 908 "Counter": "0,1,2,3", 909 "CounterHTOff": "0,1,2,3", 910 "EventCode": "0xB7, 0xBB", 911 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", 912 "MSRIndex": "0x1a6,0x1a7", 913 "MSRValue": "0x10003C0122", 914 "Offcore": "1", 915 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 916 "SampleAfterValue": "100003", 917 "UMask": "0x1" 918 }, 919 { 920 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 921 "Counter": "0,1,2,3", 922 "CounterHTOff": "0,1,2,3", 923 "EventCode": "0xB7, 0xBB", 924 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 925 "MSRIndex": "0x1a6,0x1a7", 926 "MSRValue": "0x04003C0122", 927 "Offcore": "1", 928 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 929 "SampleAfterValue": "100003", 930 "UMask": "0x1" 931 }, 932 { 933 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 934 "Counter": "0,1,2,3", 935 "CounterHTOff": "0,1,2,3", 936 "EventCode": "0xB7, 0xBB", 937 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", 938 "MSRIndex": "0x1a6,0x1a7", 939 "MSRValue": "0x10003C0004", 940 "Offcore": "1", 941 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 942 "SampleAfterValue": "100003", 943 "UMask": "0x1" 944 }, 945 { 946 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 947 "Counter": "0,1,2,3", 948 "CounterHTOff": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0x04003C0004", 953 "Offcore": "1", 954 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 955 "SampleAfterValue": "100003", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 960 "Counter": "0,1,2,3", 961 "CounterHTOff": "0,1,2,3", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x10003C0001", 966 "Offcore": "1", 967 "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 968 "SampleAfterValue": "100003", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 973 "Counter": "0,1,2,3", 974 "CounterHTOff": "0,1,2,3", 975 "EventCode": "0xB7, 0xBB", 976 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 977 "MSRIndex": "0x1a6,0x1a7", 978 "MSRValue": "0x04003C0001", 979 "Offcore": "1", 980 "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 981 "SampleAfterValue": "100003", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 986 "Counter": "0,1,2,3", 987 "CounterHTOff": "0,1,2,3", 988 "EventCode": "0xB7, 0xBB", 989 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 990 "MSRIndex": "0x1a6,0x1a7", 991 "MSRValue": "0x10003C0002", 992 "Offcore": "1", 993 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 994 "SampleAfterValue": "100003", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3", 1001 "EventCode": "0xB7, 0xBB", 1002 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "MSRValue": "0x04003C0002", 1005 "Offcore": "1", 1006 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1007 "SampleAfterValue": "100003", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 1012 "Counter": "0,1,2,3", 1013 "CounterHTOff": "0,1,2,3", 1014 "EventCode": "0xB7, 0xBB", 1015 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x3F803C0040", 1018 "Offcore": "1", 1019 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 1020 "SampleAfterValue": "100003", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 1025 "Counter": "0,1,2,3", 1026 "CounterHTOff": "0,1,2,3", 1027 "EventCode": "0xB7, 0xBB", 1028 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 1029 "MSRIndex": "0x1a6,0x1a7", 1030 "MSRValue": "0x3F803C0010", 1031 "Offcore": "1", 1032 "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 1033 "SampleAfterValue": "100003", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 1038 "Counter": "0,1,2,3", 1039 "CounterHTOff": "0,1,2,3", 1040 "EventCode": "0xB7, 0xBB", 1041 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "MSRValue": "0x3F803C0020", 1044 "Offcore": "1", 1045 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 1046 "SampleAfterValue": "100003", 1047 "UMask": "0x1" 1048 }, 1049 { 1050 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 1051 "Counter": "0,1,2,3", 1052 "CounterHTOff": "0,1,2,3", 1053 "EventCode": "0xB7, 0xBB", 1054 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 1055 "MSRIndex": "0x1a6,0x1a7", 1056 "MSRValue": "0x3F803C0200", 1057 "Offcore": "1", 1058 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 1059 "SampleAfterValue": "100003", 1060 "UMask": "0x1" 1061 }, 1062 { 1063 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 1064 "Counter": "0,1,2,3", 1065 "CounterHTOff": "0,1,2,3", 1066 "EventCode": "0xB7, 0xBB", 1067 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 1068 "MSRIndex": "0x1a6,0x1a7", 1069 "MSRValue": "0x3F803C0080", 1070 "Offcore": "1", 1071 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 1072 "SampleAfterValue": "100003", 1073 "UMask": "0x1" 1074 }, 1075 { 1076 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 1077 "Counter": "0,1,2,3", 1078 "CounterHTOff": "0,1,2,3", 1079 "EventCode": "0xB7, 0xBB", 1080 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", 1081 "MSRIndex": "0x1a6,0x1a7", 1082 "MSRValue": "0x3F803C0100", 1083 "Offcore": "1", 1084 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 1085 "SampleAfterValue": "100003", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "Split locks in SQ", 1090 "Counter": "0,1,2,3", 1091 "CounterHTOff": "0,1,2,3,4,5,6,7", 1092 "EventCode": "0xf4", 1093 "EventName": "SQ_MISC.SPLIT_LOCK", 1094 "SampleAfterValue": "100003", 1095 "UMask": "0x10" 1096 } 1097]