1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x51", 7 "EventName": "L1D.REPLACEMENT", 8 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EventCode": "0x48", 18 "EventName": "L1D_PEND_MISS.FB_FULL", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x2" 21 }, 22 { 23 "BriefDescription": "L1D miss oustandings duration in cycles", 24 "Counter": "2", 25 "CounterHTOff": "2", 26 "EventCode": "0x48", 27 "EventName": "L1D_PEND_MISS.PENDING", 28 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "Cycles with L1D load Misses outstanding.", 34 "Counter": "2", 35 "CounterHTOff": "2", 36 "CounterMask": "1", 37 "EventCode": "0x48", 38 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x1" 41 }, 42 { 43 "AnyThread": "1", 44 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 45 "Counter": "2", 46 "CounterHTOff": "2", 47 "CounterMask": "1", 48 "EventCode": "0x48", 49 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0x48", 58 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x2" 61 }, 62 { 63 "BriefDescription": "Not rejected writebacks that hit L2 cache", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0x27", 67 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 68 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 69 "SampleAfterValue": "200003", 70 "UMask": "0x50" 71 }, 72 { 73 "BriefDescription": "L2 cache lines filling L2", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "EventCode": "0xF1", 77 "EventName": "L2_LINES_IN.ALL", 78 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 79 "SampleAfterValue": "100003", 80 "UMask": "0x7" 81 }, 82 { 83 "BriefDescription": "L2 cache lines in E state filling L2", 84 "Counter": "0,1,2,3", 85 "CounterHTOff": "0,1,2,3,4,5,6,7", 86 "EventCode": "0xF1", 87 "EventName": "L2_LINES_IN.E", 88 "PublicDescription": "L2 cache lines in E state filling L2.", 89 "SampleAfterValue": "100003", 90 "UMask": "0x4" 91 }, 92 { 93 "BriefDescription": "L2 cache lines in I state filling L2", 94 "Counter": "0,1,2,3", 95 "CounterHTOff": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xF1", 97 "EventName": "L2_LINES_IN.I", 98 "PublicDescription": "L2 cache lines in I state filling L2.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "L2 cache lines in S state filling L2", 104 "Counter": "0,1,2,3", 105 "CounterHTOff": "0,1,2,3,4,5,6,7", 106 "EventCode": "0xF1", 107 "EventName": "L2_LINES_IN.S", 108 "PublicDescription": "L2 cache lines in S state filling L2.", 109 "SampleAfterValue": "100003", 110 "UMask": "0x2" 111 }, 112 { 113 "BriefDescription": "Clean L2 cache lines evicted by demand", 114 "Counter": "0,1,2,3", 115 "CounterHTOff": "0,1,2,3,4,5,6,7", 116 "EventCode": "0xF2", 117 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 118 "PublicDescription": "Clean L2 cache lines evicted by demand.", 119 "SampleAfterValue": "100003", 120 "UMask": "0x5" 121 }, 122 { 123 "BriefDescription": "Dirty L2 cache lines evicted by demand", 124 "Counter": "0,1,2,3", 125 "CounterHTOff": "0,1,2,3,4,5,6,7", 126 "EventCode": "0xF2", 127 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 128 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 129 "SampleAfterValue": "100003", 130 "UMask": "0x6" 131 }, 132 { 133 "BriefDescription": "L2 code requests", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3,4,5,6,7", 136 "EventCode": "0x24", 137 "EventName": "L2_RQSTS.ALL_CODE_RD", 138 "PublicDescription": "Counts all L2 code requests.", 139 "SampleAfterValue": "200003", 140 "UMask": "0xe4" 141 }, 142 { 143 "BriefDescription": "Demand Data Read requests", 144 "Counter": "0,1,2,3", 145 "CounterHTOff": "0,1,2,3,4,5,6,7", 146 "Errata": "HSD78, HSM80", 147 "EventCode": "0x24", 148 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 150 "SampleAfterValue": "200003", 151 "UMask": "0xe1" 152 }, 153 { 154 "BriefDescription": "Demand requests that miss L2 cache", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "Errata": "HSD78, HSM80", 158 "EventCode": "0x24", 159 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 160 "PublicDescription": "Demand requests that miss L2 cache.", 161 "SampleAfterValue": "200003", 162 "UMask": "0x27" 163 }, 164 { 165 "BriefDescription": "Demand requests to L2 cache", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3,4,5,6,7", 168 "Errata": "HSD78, HSM80", 169 "EventCode": "0x24", 170 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 171 "PublicDescription": "Demand requests to L2 cache.", 172 "SampleAfterValue": "200003", 173 "UMask": "0xe7" 174 }, 175 { 176 "BriefDescription": "Requests from L2 hardware prefetchers", 177 "Counter": "0,1,2,3", 178 "CounterHTOff": "0,1,2,3,4,5,6,7", 179 "EventCode": "0x24", 180 "EventName": "L2_RQSTS.ALL_PF", 181 "PublicDescription": "Counts all L2 HW prefetcher requests.", 182 "SampleAfterValue": "200003", 183 "UMask": "0xf8" 184 }, 185 { 186 "BriefDescription": "RFO requests to L2 cache", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3,4,5,6,7", 189 "EventCode": "0x24", 190 "EventName": "L2_RQSTS.ALL_RFO", 191 "PublicDescription": "Counts all L2 store RFO requests.", 192 "SampleAfterValue": "200003", 193 "UMask": "0xe2" 194 }, 195 { 196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 197 "Counter": "0,1,2,3", 198 "CounterHTOff": "0,1,2,3,4,5,6,7", 199 "EventCode": "0x24", 200 "EventName": "L2_RQSTS.CODE_RD_HIT", 201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 202 "SampleAfterValue": "200003", 203 "UMask": "0xc4" 204 }, 205 { 206 "BriefDescription": "L2 cache misses when fetching instructions", 207 "Counter": "0,1,2,3", 208 "CounterHTOff": "0,1,2,3,4,5,6,7", 209 "EventCode": "0x24", 210 "EventName": "L2_RQSTS.CODE_RD_MISS", 211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 212 "SampleAfterValue": "200003", 213 "UMask": "0x24" 214 }, 215 { 216 "BriefDescription": "Demand Data Read requests that hit L2 cache", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3,4,5,6,7", 219 "Errata": "HSD78, HSM80", 220 "EventCode": "0x24", 221 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 222 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", 223 "SampleAfterValue": "200003", 224 "UMask": "0xc1" 225 }, 226 { 227 "BriefDescription": "Demand Data Read miss L2, no rejects", 228 "Counter": "0,1,2,3", 229 "CounterHTOff": "0,1,2,3,4,5,6,7", 230 "Errata": "HSD78, HSM80", 231 "EventCode": "0x24", 232 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 233 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 234 "SampleAfterValue": "200003", 235 "UMask": "0x21" 236 }, 237 { 238 "BriefDescription": "L2 prefetch requests that hit L2 cache", 239 "Counter": "0,1,2,3", 240 "CounterHTOff": "0,1,2,3,4,5,6,7", 241 "EventCode": "0x24", 242 "EventName": "L2_RQSTS.L2_PF_HIT", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 244 "SampleAfterValue": "200003", 245 "UMask": "0xd0" 246 }, 247 { 248 "BriefDescription": "L2 prefetch requests that miss L2 cache", 249 "Counter": "0,1,2,3", 250 "CounterHTOff": "0,1,2,3,4,5,6,7", 251 "EventCode": "0x24", 252 "EventName": "L2_RQSTS.L2_PF_MISS", 253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 254 "SampleAfterValue": "200003", 255 "UMask": "0x30" 256 }, 257 { 258 "BriefDescription": "All requests that miss L2 cache", 259 "Counter": "0,1,2,3", 260 "CounterHTOff": "0,1,2,3,4,5,6,7", 261 "Errata": "HSD78, HSM80", 262 "EventCode": "0x24", 263 "EventName": "L2_RQSTS.MISS", 264 "PublicDescription": "All requests that missed L2.", 265 "SampleAfterValue": "200003", 266 "UMask": "0x3f" 267 }, 268 { 269 "BriefDescription": "All L2 requests", 270 "Counter": "0,1,2,3", 271 "CounterHTOff": "0,1,2,3,4,5,6,7", 272 "Errata": "HSD78, HSM80", 273 "EventCode": "0x24", 274 "EventName": "L2_RQSTS.REFERENCES", 275 "PublicDescription": "All requests to L2 cache.", 276 "SampleAfterValue": "200003", 277 "UMask": "0xff" 278 }, 279 { 280 "BriefDescription": "RFO requests that hit L2 cache", 281 "Counter": "0,1,2,3", 282 "CounterHTOff": "0,1,2,3,4,5,6,7", 283 "EventCode": "0x24", 284 "EventName": "L2_RQSTS.RFO_HIT", 285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 286 "SampleAfterValue": "200003", 287 "UMask": "0xc2" 288 }, 289 { 290 "BriefDescription": "RFO requests that miss L2 cache", 291 "Counter": "0,1,2,3", 292 "CounterHTOff": "0,1,2,3,4,5,6,7", 293 "EventCode": "0x24", 294 "EventName": "L2_RQSTS.RFO_MISS", 295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 296 "SampleAfterValue": "200003", 297 "UMask": "0x22" 298 }, 299 { 300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 301 "Counter": "0,1,2,3", 302 "CounterHTOff": "0,1,2,3,4,5,6,7", 303 "EventCode": "0xf0", 304 "EventName": "L2_TRANS.ALL_PF", 305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 306 "SampleAfterValue": "200003", 307 "UMask": "0x8" 308 }, 309 { 310 "BriefDescription": "Transactions accessing L2 pipe", 311 "Counter": "0,1,2,3", 312 "CounterHTOff": "0,1,2,3,4,5,6,7", 313 "EventCode": "0xf0", 314 "EventName": "L2_TRANS.ALL_REQUESTS", 315 "PublicDescription": "Transactions accessing L2 pipe.", 316 "SampleAfterValue": "200003", 317 "UMask": "0x80" 318 }, 319 { 320 "BriefDescription": "L2 cache accesses when fetching instructions", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3,4,5,6,7", 323 "EventCode": "0xf0", 324 "EventName": "L2_TRANS.CODE_RD", 325 "PublicDescription": "L2 cache accesses when fetching instructions.", 326 "SampleAfterValue": "200003", 327 "UMask": "0x4" 328 }, 329 { 330 "BriefDescription": "Demand Data Read requests that access L2 cache", 331 "Counter": "0,1,2,3", 332 "CounterHTOff": "0,1,2,3,4,5,6,7", 333 "EventCode": "0xf0", 334 "EventName": "L2_TRANS.DEMAND_DATA_RD", 335 "PublicDescription": "Demand data read requests that access L2 cache.", 336 "SampleAfterValue": "200003", 337 "UMask": "0x1" 338 }, 339 { 340 "BriefDescription": "L1D writebacks that access L2 cache", 341 "Counter": "0,1,2,3", 342 "CounterHTOff": "0,1,2,3,4,5,6,7", 343 "EventCode": "0xf0", 344 "EventName": "L2_TRANS.L1D_WB", 345 "PublicDescription": "L1D writebacks that access L2 cache.", 346 "SampleAfterValue": "200003", 347 "UMask": "0x10" 348 }, 349 { 350 "BriefDescription": "L2 fill requests that access L2 cache", 351 "Counter": "0,1,2,3", 352 "CounterHTOff": "0,1,2,3,4,5,6,7", 353 "EventCode": "0xf0", 354 "EventName": "L2_TRANS.L2_FILL", 355 "PublicDescription": "L2 fill requests that access L2 cache.", 356 "SampleAfterValue": "200003", 357 "UMask": "0x20" 358 }, 359 { 360 "BriefDescription": "L2 writebacks that access L2 cache", 361 "Counter": "0,1,2,3", 362 "CounterHTOff": "0,1,2,3,4,5,6,7", 363 "EventCode": "0xf0", 364 "EventName": "L2_TRANS.L2_WB", 365 "PublicDescription": "L2 writebacks that access L2 cache.", 366 "SampleAfterValue": "200003", 367 "UMask": "0x40" 368 }, 369 { 370 "BriefDescription": "RFO requests that access L2 cache", 371 "Counter": "0,1,2,3", 372 "CounterHTOff": "0,1,2,3,4,5,6,7", 373 "EventCode": "0xf0", 374 "EventName": "L2_TRANS.RFO", 375 "PublicDescription": "RFO requests that access L2 cache.", 376 "SampleAfterValue": "200003", 377 "UMask": "0x2" 378 }, 379 { 380 "BriefDescription": "Cycles when L1D is locked", 381 "Counter": "0,1,2,3", 382 "CounterHTOff": "0,1,2,3,4,5,6,7", 383 "EventCode": "0x63", 384 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 385 "PublicDescription": "Cycles in which the L1D is locked.", 386 "SampleAfterValue": "2000003", 387 "UMask": "0x2" 388 }, 389 { 390 "BriefDescription": "Core-originated cacheable demand requests missed L3", 391 "Counter": "0,1,2,3", 392 "CounterHTOff": "0,1,2,3,4,5,6,7", 393 "EventCode": "0x2E", 394 "EventName": "LONGEST_LAT_CACHE.MISS", 395 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 396 "SampleAfterValue": "100003", 397 "UMask": "0x41" 398 }, 399 { 400 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 401 "Counter": "0,1,2,3", 402 "CounterHTOff": "0,1,2,3,4,5,6,7", 403 "EventCode": "0x2E", 404 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 405 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 406 "SampleAfterValue": "100003", 407 "UMask": "0x4f" 408 }, 409 { 410 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", 411 "Counter": "0,1,2,3", 412 "CounterHTOff": "0,1,2,3", 413 "Data_LA": "1", 414 "Errata": "HSD29, HSD25, HSM26, HSM30", 415 "EventCode": "0xD2", 416 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 417 "PEBS": "1", 418 "SampleAfterValue": "20011", 419 "UMask": "0x2" 420 }, 421 { 422 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", 423 "Counter": "0,1,2,3", 424 "CounterHTOff": "0,1,2,3", 425 "Data_LA": "1", 426 "Errata": "HSD29, HSD25, HSM26, HSM30", 427 "EventCode": "0xD2", 428 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 429 "PEBS": "1", 430 "SampleAfterValue": "20011", 431 "UMask": "0x4" 432 }, 433 { 434 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 435 "Counter": "0,1,2,3", 436 "CounterHTOff": "0,1,2,3", 437 "Data_LA": "1", 438 "Errata": "HSD29, HSD25, HSM26, HSM30", 439 "EventCode": "0xD2", 440 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 441 "PEBS": "1", 442 "SampleAfterValue": "20011", 443 "UMask": "0x1" 444 }, 445 { 446 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 447 "Counter": "0,1,2,3", 448 "CounterHTOff": "0,1,2,3", 449 "Data_LA": "1", 450 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 451 "EventCode": "0xD2", 452 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 453 "PEBS": "1", 454 "SampleAfterValue": "100003", 455 "UMask": "0x8" 456 }, 457 { 458 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 459 "Counter": "0,1,2,3", 460 "CounterHTOff": "0,1,2,3", 461 "Data_LA": "1", 462 "Errata": "HSD74, HSD29, HSD25, HSM30", 463 "EventCode": "0xD3", 464 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 465 "PEBS": "1", 466 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", 467 "SampleAfterValue": "100003", 468 "UMask": "0x1" 469 }, 470 { 471 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 472 "Counter": "0,1,2,3", 473 "CounterHTOff": "0,1,2,3", 474 "Data_LA": "1", 475 "Errata": "HSM30", 476 "EventCode": "0xD1", 477 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 478 "PEBS": "1", 479 "SampleAfterValue": "100003", 480 "UMask": "0x40" 481 }, 482 { 483 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 484 "Counter": "0,1,2,3", 485 "CounterHTOff": "0,1,2,3", 486 "Data_LA": "1", 487 "Errata": "HSD29, HSM30", 488 "EventCode": "0xD1", 489 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 490 "PEBS": "1", 491 "SampleAfterValue": "2000003", 492 "UMask": "0x1" 493 }, 494 { 495 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 496 "Counter": "0,1,2,3", 497 "CounterHTOff": "0,1,2,3", 498 "Data_LA": "1", 499 "Errata": "HSM30", 500 "EventCode": "0xD1", 501 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 502 "PEBS": "1", 503 "PublicDescription": "Retired load uops missed L1 cache as data sources.", 504 "SampleAfterValue": "100003", 505 "UMask": "0x8" 506 }, 507 { 508 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 509 "Counter": "0,1,2,3", 510 "CounterHTOff": "0,1,2,3", 511 "Data_LA": "1", 512 "Errata": "HSD76, HSD29, HSM30", 513 "EventCode": "0xD1", 514 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 515 "PEBS": "1", 516 "SampleAfterValue": "100003", 517 "UMask": "0x2" 518 }, 519 { 520 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 521 "Counter": "0,1,2,3", 522 "CounterHTOff": "0,1,2,3", 523 "Data_LA": "1", 524 "Errata": "HSD29, HSM30", 525 "EventCode": "0xD1", 526 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 527 "PEBS": "1", 528 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", 529 "SampleAfterValue": "50021", 530 "UMask": "0x10" 531 }, 532 { 533 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", 534 "Counter": "0,1,2,3", 535 "CounterHTOff": "0,1,2,3", 536 "Data_LA": "1", 537 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 538 "EventCode": "0xD1", 539 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 540 "PEBS": "1", 541 "PublicDescription": "Retired load uops with L3 cache hits as data sources.", 542 "SampleAfterValue": "50021", 543 "UMask": "0x4" 544 }, 545 { 546 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 547 "Counter": "0,1,2,3", 548 "CounterHTOff": "0,1,2,3", 549 "Data_LA": "1", 550 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 551 "EventCode": "0xD1", 552 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 553 "PEBS": "1", 554 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", 555 "SampleAfterValue": "100003", 556 "UMask": "0x20" 557 }, 558 { 559 "BriefDescription": "All retired load uops.", 560 "Counter": "0,1,2,3", 561 "CounterHTOff": "0,1,2,3", 562 "Data_LA": "1", 563 "Errata": "HSD29, HSM30", 564 "EventCode": "0xD0", 565 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 566 "PEBS": "1", 567 "SampleAfterValue": "2000003", 568 "UMask": "0x81" 569 }, 570 { 571 "BriefDescription": "All retired store uops.", 572 "Counter": "0,1,2,3", 573 "CounterHTOff": "0,1,2,3", 574 "Data_LA": "1", 575 "Errata": "HSD29, HSM30", 576 "EventCode": "0xD0", 577 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 578 "L1_Hit_Indication": "1", 579 "PEBS": "1", 580 "SampleAfterValue": "2000003", 581 "UMask": "0x82" 582 }, 583 { 584 "BriefDescription": "Retired load uops with locked access.", 585 "Counter": "0,1,2,3", 586 "CounterHTOff": "0,1,2,3", 587 "Data_LA": "1", 588 "Errata": "HSD76, HSD29, HSM30", 589 "EventCode": "0xD0", 590 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 591 "PEBS": "1", 592 "SampleAfterValue": "100003", 593 "UMask": "0x21" 594 }, 595 { 596 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 597 "Counter": "0,1,2,3", 598 "CounterHTOff": "0,1,2,3", 599 "Data_LA": "1", 600 "Errata": "HSD29, HSM30", 601 "EventCode": "0xD0", 602 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 603 "PEBS": "1", 604 "SampleAfterValue": "100003", 605 "UMask": "0x41" 606 }, 607 { 608 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 609 "Counter": "0,1,2,3", 610 "CounterHTOff": "0,1,2,3", 611 "Data_LA": "1", 612 "Errata": "HSD29, HSM30", 613 "EventCode": "0xD0", 614 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 615 "L1_Hit_Indication": "1", 616 "PEBS": "1", 617 "SampleAfterValue": "100003", 618 "UMask": "0x42" 619 }, 620 { 621 "BriefDescription": "Retired load uops that miss the STLB.", 622 "Counter": "0,1,2,3", 623 "CounterHTOff": "0,1,2,3", 624 "Data_LA": "1", 625 "Errata": "HSD29, HSM30", 626 "EventCode": "0xD0", 627 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 628 "PEBS": "1", 629 "SampleAfterValue": "100003", 630 "UMask": "0x11" 631 }, 632 { 633 "BriefDescription": "Retired store uops that miss the STLB.", 634 "Counter": "0,1,2,3", 635 "CounterHTOff": "0,1,2,3", 636 "Data_LA": "1", 637 "Errata": "HSD29, HSM30", 638 "EventCode": "0xD0", 639 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 640 "L1_Hit_Indication": "1", 641 "PEBS": "1", 642 "SampleAfterValue": "100003", 643 "UMask": "0x12" 644 }, 645 { 646 "BriefDescription": "Demand and prefetch data reads", 647 "Counter": "0,1,2,3", 648 "CounterHTOff": "0,1,2,3,4,5,6,7", 649 "EventCode": "0xB0", 650 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 651 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 652 "SampleAfterValue": "100003", 653 "UMask": "0x8" 654 }, 655 { 656 "BriefDescription": "Cacheable and noncachaeble code read requests", 657 "Counter": "0,1,2,3", 658 "CounterHTOff": "0,1,2,3,4,5,6,7", 659 "EventCode": "0xB0", 660 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 661 "PublicDescription": "Demand code read requests sent to uncore.", 662 "SampleAfterValue": "100003", 663 "UMask": "0x2" 664 }, 665 { 666 "BriefDescription": "Demand Data Read requests sent to uncore", 667 "Counter": "0,1,2,3", 668 "CounterHTOff": "0,1,2,3,4,5,6,7", 669 "Errata": "HSD78, HSM80", 670 "EventCode": "0xb0", 671 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 672 "PublicDescription": "Demand data read requests sent to uncore.", 673 "SampleAfterValue": "100003", 674 "UMask": "0x1" 675 }, 676 { 677 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 678 "Counter": "0,1,2,3", 679 "CounterHTOff": "0,1,2,3,4,5,6,7", 680 "EventCode": "0xB0", 681 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 682 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 683 "SampleAfterValue": "100003", 684 "UMask": "0x4" 685 }, 686 { 687 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 688 "Counter": "0,1,2,3", 689 "CounterHTOff": "0,1,2,3,4,5,6,7", 690 "EventCode": "0xb2", 691 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 692 "SampleAfterValue": "2000003", 693 "UMask": "0x1" 694 }, 695 { 696 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 697 "Counter": "0,1,2,3", 698 "CounterHTOff": "0,1,2,3,4,5,6,7", 699 "Errata": "HSD62, HSD61, HSM63", 700 "EventCode": "0x60", 701 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 702 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 703 "SampleAfterValue": "2000003", 704 "UMask": "0x8" 705 }, 706 { 707 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 708 "Counter": "0,1,2,3", 709 "CounterHTOff": "0,1,2,3,4,5,6,7", 710 "CounterMask": "1", 711 "Errata": "HSD62, HSD61, HSM63", 712 "EventCode": "0x60", 713 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 714 "SampleAfterValue": "2000003", 715 "UMask": "0x8" 716 }, 717 { 718 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 719 "Counter": "0,1,2,3", 720 "CounterHTOff": "0,1,2,3,4,5,6,7", 721 "CounterMask": "1", 722 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 723 "EventCode": "0x60", 724 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 725 "SampleAfterValue": "2000003", 726 "UMask": "0x1" 727 }, 728 { 729 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 730 "Counter": "0,1,2,3", 731 "CounterHTOff": "0,1,2,3,4,5,6,7", 732 "CounterMask": "1", 733 "Errata": "HSD62, HSD61, HSM63", 734 "EventCode": "0x60", 735 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 736 "SampleAfterValue": "2000003", 737 "UMask": "0x4" 738 }, 739 { 740 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 741 "Counter": "0,1,2,3", 742 "CounterHTOff": "0,1,2,3,4,5,6,7", 743 "Errata": "HSD62, HSD61, HSM63", 744 "EventCode": "0x60", 745 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 746 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 747 "SampleAfterValue": "2000003", 748 "UMask": "0x2" 749 }, 750 { 751 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 752 "Counter": "0,1,2,3", 753 "CounterHTOff": "0,1,2,3,4,5,6,7", 754 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 755 "EventCode": "0x60", 756 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 757 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 758 "SampleAfterValue": "2000003", 759 "UMask": "0x1" 760 }, 761 { 762 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 763 "Counter": "0,1,2,3", 764 "CounterHTOff": "0,1,2,3,4,5,6,7", 765 "CounterMask": "6", 766 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", 767 "EventCode": "0x60", 768 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 769 "SampleAfterValue": "2000003", 770 "UMask": "0x1" 771 }, 772 { 773 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 774 "Counter": "0,1,2,3", 775 "CounterHTOff": "0,1,2,3,4,5,6,7", 776 "Errata": "HSD62, HSD61, HSM63", 777 "EventCode": "0x60", 778 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 779 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 780 "SampleAfterValue": "2000003", 781 "UMask": "0x4" 782 }, 783 { 784 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 785 "Counter": "0,1,2,3", 786 "CounterHTOff": "0,1,2,3", 787 "EventCode": "0xB7, 0xBB", 788 "EventName": "OFFCORE_RESPONSE", 789 "SampleAfterValue": "100003", 790 "UMask": "0x1" 791 }, 792 { 793 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 794 "Counter": "0,1,2,3", 795 "CounterHTOff": "0,1,2,3", 796 "EventCode": "0xB7, 0xBB", 797 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 798 "MSRIndex": "0x1a6,0x1a7", 799 "MSRValue": "0x04003C0244", 800 "Offcore": "1", 801 "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 802 "SampleAfterValue": "100003", 803 "UMask": "0x1" 804 }, 805 { 806 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 807 "Counter": "0,1,2,3", 808 "CounterHTOff": "0,1,2,3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x10003C0091", 813 "Offcore": "1", 814 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 815 "SampleAfterValue": "100003", 816 "UMask": "0x1" 817 }, 818 { 819 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 820 "Counter": "0,1,2,3", 821 "CounterHTOff": "0,1,2,3", 822 "EventCode": "0xB7, 0xBB", 823 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 824 "MSRIndex": "0x1a6,0x1a7", 825 "MSRValue": "0x04003C0091", 826 "Offcore": "1", 827 "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 828 "SampleAfterValue": "100003", 829 "UMask": "0x1" 830 }, 831 { 832 "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 833 "Counter": "0,1,2,3", 834 "CounterHTOff": "0,1,2,3", 835 "EventCode": "0xB7, 0xBB", 836 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", 837 "MSRIndex": "0x1a6,0x1a7", 838 "MSRValue": "0x10003C07F7", 839 "Offcore": "1", 840 "PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 841 "SampleAfterValue": "100003", 842 "UMask": "0x1" 843 }, 844 { 845 "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 846 "Counter": "0,1,2,3", 847 "CounterHTOff": "0,1,2,3", 848 "EventCode": "0xB7, 0xBB", 849 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 850 "MSRIndex": "0x1a6,0x1a7", 851 "MSRValue": "0x04003C07F7", 852 "Offcore": "1", 853 "PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 854 "SampleAfterValue": "100003", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Counts all requests hit in the L3", 859 "Counter": "0,1,2,3", 860 "CounterHTOff": "0,1,2,3", 861 "EventCode": "0xB7, 0xBB", 862 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", 863 "MSRIndex": "0x1a6,0x1a7", 864 "MSRValue": "0x3F803C8FFF", 865 "Offcore": "1", 866 "PublicDescription": "Counts all requests hit in the L3", 867 "SampleAfterValue": "100003", 868 "UMask": "0x1" 869 }, 870 { 871 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 872 "Counter": "0,1,2,3", 873 "CounterHTOff": "0,1,2,3", 874 "EventCode": "0xB7, 0xBB", 875 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 876 "MSRIndex": "0x1a6,0x1a7", 877 "MSRValue": "0x10003C0122", 878 "Offcore": "1", 879 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 880 "SampleAfterValue": "100003", 881 "UMask": "0x1" 882 }, 883 { 884 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 885 "Counter": "0,1,2,3", 886 "CounterHTOff": "0,1,2,3", 887 "EventCode": "0xB7, 0xBB", 888 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 889 "MSRIndex": "0x1a6,0x1a7", 890 "MSRValue": "0x04003C0122", 891 "Offcore": "1", 892 "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 893 "SampleAfterValue": "100003", 894 "UMask": "0x1" 895 }, 896 { 897 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 898 "Counter": "0,1,2,3", 899 "CounterHTOff": "0,1,2,3", 900 "EventCode": "0xB7, 0xBB", 901 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 902 "MSRIndex": "0x1a6,0x1a7", 903 "MSRValue": "0x10003C0004", 904 "Offcore": "1", 905 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 906 "SampleAfterValue": "100003", 907 "UMask": "0x1" 908 }, 909 { 910 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 911 "Counter": "0,1,2,3", 912 "CounterHTOff": "0,1,2,3", 913 "EventCode": "0xB7, 0xBB", 914 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 915 "MSRIndex": "0x1a6,0x1a7", 916 "MSRValue": "0x04003C0004", 917 "Offcore": "1", 918 "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 919 "SampleAfterValue": "100003", 920 "UMask": "0x1" 921 }, 922 { 923 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 924 "Counter": "0,1,2,3", 925 "CounterHTOff": "0,1,2,3", 926 "EventCode": "0xB7, 0xBB", 927 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 928 "MSRIndex": "0x1a6,0x1a7", 929 "MSRValue": "0x10003C0001", 930 "Offcore": "1", 931 "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 932 "SampleAfterValue": "100003", 933 "UMask": "0x1" 934 }, 935 { 936 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 937 "Counter": "0,1,2,3", 938 "CounterHTOff": "0,1,2,3", 939 "EventCode": "0xB7, 0xBB", 940 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 941 "MSRIndex": "0x1a6,0x1a7", 942 "MSRValue": "0x04003C0001", 943 "Offcore": "1", 944 "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 945 "SampleAfterValue": "100003", 946 "UMask": "0x1" 947 }, 948 { 949 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 950 "Counter": "0,1,2,3", 951 "CounterHTOff": "0,1,2,3", 952 "EventCode": "0xB7, 0xBB", 953 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 954 "MSRIndex": "0x1a6,0x1a7", 955 "MSRValue": "0x10003C0002", 956 "Offcore": "1", 957 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 958 "SampleAfterValue": "100003", 959 "UMask": "0x1" 960 }, 961 { 962 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 963 "Counter": "0,1,2,3", 964 "CounterHTOff": "0,1,2,3", 965 "EventCode": "0xB7, 0xBB", 966 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 967 "MSRIndex": "0x1a6,0x1a7", 968 "MSRValue": "0x04003C0002", 969 "Offcore": "1", 970 "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 971 "SampleAfterValue": "100003", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 976 "Counter": "0,1,2,3", 977 "CounterHTOff": "0,1,2,3", 978 "EventCode": "0xB7, 0xBB", 979 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", 980 "MSRIndex": "0x1a6,0x1a7", 981 "MSRValue": "0x3F803C0040", 982 "Offcore": "1", 983 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", 984 "SampleAfterValue": "100003", 985 "UMask": "0x1" 986 }, 987 { 988 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 989 "Counter": "0,1,2,3", 990 "CounterHTOff": "0,1,2,3", 991 "EventCode": "0xB7, 0xBB", 992 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", 993 "MSRIndex": "0x1a6,0x1a7", 994 "MSRValue": "0x3F803C0010", 995 "Offcore": "1", 996 "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", 997 "SampleAfterValue": "100003", 998 "UMask": "0x1" 999 }, 1000 { 1001 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 1002 "Counter": "0,1,2,3", 1003 "CounterHTOff": "0,1,2,3", 1004 "EventCode": "0xB7, 0xBB", 1005 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", 1006 "MSRIndex": "0x1a6,0x1a7", 1007 "MSRValue": "0x3F803C0020", 1008 "Offcore": "1", 1009 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", 1010 "SampleAfterValue": "100003", 1011 "UMask": "0x1" 1012 }, 1013 { 1014 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 1015 "Counter": "0,1,2,3", 1016 "CounterHTOff": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x3F803C0200", 1021 "Offcore": "1", 1022 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", 1023 "SampleAfterValue": "100003", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 1028 "Counter": "0,1,2,3", 1029 "CounterHTOff": "0,1,2,3", 1030 "EventCode": "0xB7, 0xBB", 1031 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", 1032 "MSRIndex": "0x1a6,0x1a7", 1033 "MSRValue": "0x3F803C0080", 1034 "Offcore": "1", 1035 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", 1036 "SampleAfterValue": "100003", 1037 "UMask": "0x1" 1038 }, 1039 { 1040 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 1041 "Counter": "0,1,2,3", 1042 "CounterHTOff": "0,1,2,3", 1043 "EventCode": "0xB7, 0xBB", 1044 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", 1045 "MSRIndex": "0x1a6,0x1a7", 1046 "MSRValue": "0x3F803C0100", 1047 "Offcore": "1", 1048 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", 1049 "SampleAfterValue": "100003", 1050 "UMask": "0x1" 1051 }, 1052 { 1053 "BriefDescription": "Split locks in SQ", 1054 "Counter": "0,1,2,3", 1055 "CounterHTOff": "0,1,2,3,4,5,6,7", 1056 "EventCode": "0xf4", 1057 "EventName": "SQ_MISC.SPLIT_LOCK", 1058 "SampleAfterValue": "100003", 1059 "UMask": "0x10" 1060 } 1061]