1959826caSMatt Macy[ 2959826caSMatt Macy { 3*18054d02SAlexander Motin "BriefDescription": "Cycles code-fetch stalled due to any reason.", 4959826caSMatt Macy "CollectPEBSRecord": "1", 5959826caSMatt Macy "Counter": "0,1,2,3", 6*18054d02SAlexander Motin "EventCode": "0x86", 7959826caSMatt Macy "EventName": "FETCH_STALL.ALL", 8959826caSMatt Macy "PDIR_COUNTER": "na", 9*18054d02SAlexander Motin "PEBScounters": "0,1,2,3", 10*18054d02SAlexander Motin "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", 11*18054d02SAlexander Motin "SampleAfterValue": "200003" 12959826caSMatt Macy }, 13959826caSMatt Macy { 14*18054d02SAlexander Motin "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.", 15959826caSMatt Macy "CollectPEBSRecord": "1", 16959826caSMatt Macy "Counter": "0,1,2,3", 17*18054d02SAlexander Motin "EventCode": "0x86", 18959826caSMatt Macy "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", 19959826caSMatt Macy "PDIR_COUNTER": "na", 20959826caSMatt Macy "PEBScounters": "0,1,2,3", 21*18054d02SAlexander Motin "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", 22959826caSMatt Macy "SampleAfterValue": "200003", 23*18054d02SAlexander Motin "UMask": "0x1" 24959826caSMatt Macy }, 25959826caSMatt Macy { 26*18054d02SAlexander Motin "BriefDescription": "Cycles hardware interrupts are masked", 27959826caSMatt Macy "CollectPEBSRecord": "2", 28959826caSMatt Macy "Counter": "0,1,2,3", 29959826caSMatt Macy "EventCode": "0xCB", 30959826caSMatt Macy "EventName": "HW_INTERRUPTS.MASKED", 31959826caSMatt Macy "PDIR_COUNTER": "na", 32*18054d02SAlexander Motin "PEBScounters": "0,1,2,3", 33*18054d02SAlexander Motin "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", 34959826caSMatt Macy "SampleAfterValue": "200003", 35*18054d02SAlexander Motin "UMask": "0x2" 36959826caSMatt Macy }, 37959826caSMatt Macy { 38*18054d02SAlexander Motin "BriefDescription": "Cycles pending interrupts are masked", 39959826caSMatt Macy "CollectPEBSRecord": "2", 40959826caSMatt Macy "Counter": "0,1,2,3", 41*18054d02SAlexander Motin "EventCode": "0xCB", 42959826caSMatt Macy "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", 43959826caSMatt Macy "PDIR_COUNTER": "na", 44*18054d02SAlexander Motin "PEBScounters": "0,1,2,3", 45*18054d02SAlexander Motin "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", 46959826caSMatt Macy "SampleAfterValue": "200003", 47*18054d02SAlexander Motin "UMask": "0x4" 48*18054d02SAlexander Motin }, 49*18054d02SAlexander Motin { 50*18054d02SAlexander Motin "BriefDescription": "Hardware interrupts received", 51*18054d02SAlexander Motin "CollectPEBSRecord": "2", 52*18054d02SAlexander Motin "Counter": "0,1,2,3", 53*18054d02SAlexander Motin "EventCode": "0xCB", 54*18054d02SAlexander Motin "EventName": "HW_INTERRUPTS.RECEIVED", 55*18054d02SAlexander Motin "PDIR_COUNTER": "na", 56*18054d02SAlexander Motin "PEBScounters": "0,1,2,3", 57*18054d02SAlexander Motin "PublicDescription": "Counts hardware interrupts received by the processor.", 58*18054d02SAlexander Motin "SampleAfterValue": "203", 59*18054d02SAlexander Motin "UMask": "0x1" 60959826caSMatt Macy } 61959826caSMatt Macy] 62