xref: /freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/other.json (revision 959826ca1bb0a42ddd624bf1803ae2957a3282f3)
1*959826caSMatt Macy[
2*959826caSMatt Macy    {
3*959826caSMatt Macy        "CollectPEBSRecord": "1",
4*959826caSMatt Macy        "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
5*959826caSMatt Macy        "EventCode": "0x86",
6*959826caSMatt Macy        "Counter": "0,1,2,3",
7*959826caSMatt Macy        "UMask": "0x0",
8*959826caSMatt Macy        "EventName": "FETCH_STALL.ALL",
9*959826caSMatt Macy        "SampleAfterValue": "200003",
10*959826caSMatt Macy        "BriefDescription": "Cycles code-fetch stalled due to any reason."
11*959826caSMatt Macy    },
12*959826caSMatt Macy    {
13*959826caSMatt Macy        "CollectPEBSRecord": "1",
14*959826caSMatt Macy        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
15*959826caSMatt Macy        "EventCode": "0x86",
16*959826caSMatt Macy        "Counter": "0,1,2,3",
17*959826caSMatt Macy        "UMask": "0x1",
18*959826caSMatt Macy        "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
19*959826caSMatt Macy        "SampleAfterValue": "200003",
20*959826caSMatt Macy        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss."
21*959826caSMatt Macy    },
22*959826caSMatt Macy    {
23*959826caSMatt Macy        "CollectPEBSRecord": "1",
24*959826caSMatt Macy        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
25*959826caSMatt Macy        "EventCode": "0xCA",
26*959826caSMatt Macy        "Counter": "0,1,2,3",
27*959826caSMatt Macy        "UMask": "0x0",
28*959826caSMatt Macy        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
29*959826caSMatt Macy        "SampleAfterValue": "200003",
30*959826caSMatt Macy        "BriefDescription": "Unfilled issue slots per cycle"
31*959826caSMatt Macy    },
32*959826caSMatt Macy    {
33*959826caSMatt Macy        "CollectPEBSRecord": "1",
34*959826caSMatt Macy        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not count.",
35*959826caSMatt Macy        "EventCode": "0xCA",
36*959826caSMatt Macy        "Counter": "0,1,2,3",
37*959826caSMatt Macy        "UMask": "0x1",
38*959826caSMatt Macy        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
39*959826caSMatt Macy        "SampleAfterValue": "200003",
40*959826caSMatt Macy        "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend"
41*959826caSMatt Macy    },
42*959826caSMatt Macy    {
43*959826caSMatt Macy        "CollectPEBSRecord": "1",
44*959826caSMatt Macy        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
45*959826caSMatt Macy        "EventCode": "0xCA",
46*959826caSMatt Macy        "Counter": "0,1,2,3",
47*959826caSMatt Macy        "UMask": "0x2",
48*959826caSMatt Macy        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
49*959826caSMatt Macy        "SampleAfterValue": "200003",
50*959826caSMatt Macy        "BriefDescription": "Unfilled issue slots per cycle to recover"
51*959826caSMatt Macy    },
52*959826caSMatt Macy    {
53*959826caSMatt Macy        "CollectPEBSRecord": "2",
54*959826caSMatt Macy        "PublicDescription": "Counts hardware interrupts received by the processor.",
55*959826caSMatt Macy        "EventCode": "0xCB",
56*959826caSMatt Macy        "Counter": "0,1,2,3",
57*959826caSMatt Macy        "UMask": "0x1",
58*959826caSMatt Macy        "EventName": "HW_INTERRUPTS.RECEIVED",
59*959826caSMatt Macy        "SampleAfterValue": "203",
60*959826caSMatt Macy        "BriefDescription": "Hardware interrupts received"
61*959826caSMatt Macy    },
62*959826caSMatt Macy    {
63*959826caSMatt Macy        "CollectPEBSRecord": "2",
64*959826caSMatt Macy        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
65*959826caSMatt Macy        "EventCode": "0xCB",
66*959826caSMatt Macy        "Counter": "0,1,2,3",
67*959826caSMatt Macy        "UMask": "0x2",
68*959826caSMatt Macy        "EventName": "HW_INTERRUPTS.MASKED",
69*959826caSMatt Macy        "SampleAfterValue": "200003",
70*959826caSMatt Macy        "BriefDescription": "Cycles hardware interrupts are masked"
71*959826caSMatt Macy    },
72*959826caSMatt Macy    {
73*959826caSMatt Macy        "CollectPEBSRecord": "2",
74*959826caSMatt Macy        "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
75*959826caSMatt Macy        "EventCode": "0xCB",
76*959826caSMatt Macy        "Counter": "0,1,2,3",
77*959826caSMatt Macy        "UMask": "0x4",
78*959826caSMatt Macy        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
79*959826caSMatt Macy        "SampleAfterValue": "200003",
80*959826caSMatt Macy        "BriefDescription": "Cycles pending interrupts are masked"
81*959826caSMatt Macy    }
82*959826caSMatt Macy]