1[ 2 { 3 "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3", 6 "EdgeDetect": "1", 7 "EventCode": "0x63", 8 "EventName": "BUS_LOCK.ALL", 9 "PDIR_COUNTER": "na", 10 "PEBScounters": "0,1,2,3", 11 "SampleAfterValue": "200003" 12 }, 13 { 14 "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3", 17 "EventCode": "0x63", 18 "EventName": "BUS_LOCK.BLOCK_CYCLES", 19 "PEBScounters": "0,1,2,3", 20 "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.", 21 "SampleAfterValue": "200003", 22 "UMask": "0x2" 23 }, 24 { 25 "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES", 26 "CollectPEBSRecord": "2", 27 "Counter": "0,1,2,3", 28 "EventCode": "0x63", 29 "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", 30 "PDIR_COUNTER": "na", 31 "PEBScounters": "0,1,2,3", 32 "SampleAfterValue": "200003", 33 "UMask": "0x2" 34 }, 35 { 36 "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES", 37 "CollectPEBSRecord": "2", 38 "Counter": "0,1,2,3", 39 "EventCode": "0x63", 40 "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", 41 "PDIR_COUNTER": "na", 42 "PEBScounters": "0,1,2,3", 43 "SampleAfterValue": "200003", 44 "UMask": "0x1" 45 }, 46 { 47 "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.", 48 "CollectPEBSRecord": "2", 49 "Counter": "0,1,2,3", 50 "EventCode": "0x63", 51 "EventName": "BUS_LOCK.LOCK_CYCLES", 52 "PEBScounters": "0,1,2,3", 53 "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.", 54 "SampleAfterValue": "200003", 55 "UMask": "0x1" 56 }, 57 { 58 "BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.", 59 "CollectPEBSRecord": "2", 60 "Counter": "0,1,2,3", 61 "EdgeDetect": "1", 62 "EventCode": "0x63", 63 "EventName": "BUS_LOCK.SELF_LOCKS", 64 "PEBScounters": "0,1,2,3", 65 "PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.", 66 "SampleAfterValue": "200003" 67 }, 68 { 69 "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT", 70 "CollectPEBSRecord": "2", 71 "Counter": "0,1,2,3", 72 "EventCode": "0x34", 73 "EventName": "C0_STALLS.LOAD_DRAM_HIT", 74 "PDIR_COUNTER": "na", 75 "PEBScounters": "0,1,2,3", 76 "SampleAfterValue": "200003", 77 "UMask": "0x4" 78 }, 79 { 80 "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT", 81 "CollectPEBSRecord": "2", 82 "Counter": "0,1,2,3", 83 "EventCode": "0x34", 84 "EventName": "C0_STALLS.LOAD_L2_HIT", 85 "PDIR_COUNTER": "na", 86 "PEBScounters": "0,1,2,3", 87 "SampleAfterValue": "200003", 88 "UMask": "0x1" 89 }, 90 { 91 "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT", 92 "CollectPEBSRecord": "2", 93 "Counter": "0,1,2,3", 94 "EventCode": "0x34", 95 "EventName": "C0_STALLS.LOAD_LLC_HIT", 96 "PDIR_COUNTER": "na", 97 "PEBScounters": "0,1,2,3", 98 "SampleAfterValue": "200003", 99 "UMask": "0x2" 100 }, 101 { 102 "BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).", 103 "CollectPEBSRecord": "2", 104 "Counter": "0,1,2,3", 105 "EventCode": "0xcb", 106 "EventName": "HW_INTERRUPTS.MASKED", 107 "PDIR_COUNTER": "na", 108 "PEBScounters": "0,1,2,3", 109 "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", 110 "SampleAfterValue": "200003", 111 "UMask": "0x2" 112 }, 113 { 114 "BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).", 115 "CollectPEBSRecord": "2", 116 "Counter": "0,1,2,3", 117 "EventCode": "0xcb", 118 "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", 119 "PDIR_COUNTER": "na", 120 "PEBScounters": "0,1,2,3", 121 "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.", 122 "SampleAfterValue": "200003", 123 "UMask": "0x4" 124 }, 125 { 126 "BriefDescription": "Counts the number of hardware interrupts received by the processor.", 127 "CollectPEBSRecord": "2", 128 "Counter": "0,1,2,3", 129 "EventCode": "0xcb", 130 "EventName": "HW_INTERRUPTS.RECEIVED", 131 "PDIR_COUNTER": "na", 132 "PEBScounters": "0,1,2,3", 133 "SampleAfterValue": "203", 134 "UMask": "0x1" 135 }, 136 { 137 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", 138 "Counter": "0,1,2,3", 139 "EventCode": "0XB7", 140 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", 141 "MSRIndex": "0x1a6,0x1a7", 142 "MSRValue": "0x10001", 143 "Offcore": "1", 144 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 145 "SampleAfterValue": "100003", 146 "UMask": "0x1" 147 }, 148 { 149 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", 150 "Counter": "0,1,2,3", 151 "EventCode": "0XB7", 152 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 153 "MSRIndex": "0x1a6,0x1a7", 154 "MSRValue": "0x10001", 155 "Offcore": "1", 156 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 157 "SampleAfterValue": "100003", 158 "UMask": "0x1" 159 }, 160 { 161 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 162 "Counter": "0,1,2,3", 163 "EventCode": "0XB7", 164 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 165 "MSRIndex": "0x1a6,0x1a7", 166 "MSRValue": "0x10002", 167 "Offcore": "1", 168 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 169 "SampleAfterValue": "100003", 170 "UMask": "0x1" 171 } 172] 173