1[ 2 { 3 "BriefDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3", 6 "EventCode": "0xc3", 7 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 8 "PDIR_COUNTER": "na", 9 "PEBScounters": "0,1,2,3", 10 "PublicDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.", 11 "SampleAfterValue": "20003", 12 "UMask": "0x2" 13 }, 14 { 15 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 16 "Counter": "0,1,2,3", 17 "EventCode": "0XB7", 18 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 19 "MSRIndex": "0x1a6,0x1a7", 20 "MSRValue": "0x2104000001", 21 "Offcore": "1", 22 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 23 "SampleAfterValue": "100003", 24 "UMask": "0x1" 25 }, 26 { 27 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 28 "Counter": "0,1,2,3", 29 "EventCode": "0XB7", 30 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 31 "MSRIndex": "0x1a6,0x1a7", 32 "MSRValue": "0x2104000001", 33 "Offcore": "1", 34 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 35 "SampleAfterValue": "100003", 36 "UMask": "0x1" 37 }, 38 { 39 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 40 "Counter": "0,1,2,3", 41 "EventCode": "0XB7", 42 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 43 "MSRIndex": "0x1a6,0x1a7", 44 "MSRValue": "0x2104000001", 45 "Offcore": "1", 46 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 47 "SampleAfterValue": "100003", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 52 "Counter": "0,1,2,3", 53 "EventCode": "0XB7", 54 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 55 "MSRIndex": "0x1a6,0x1a7", 56 "MSRValue": "0x2104000001", 57 "Offcore": "1", 58 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 59 "SampleAfterValue": "100003", 60 "UMask": "0x1" 61 }, 62 { 63 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 64 "Counter": "0,1,2,3", 65 "EventCode": "0XB7", 66 "EventName": "OCR.DEMAND_RFO.L3_MISS", 67 "MSRIndex": "0x1a6,0x1a7", 68 "MSRValue": "0x2104000002", 69 "Offcore": "1", 70 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 71 "SampleAfterValue": "100003", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 76 "Counter": "0,1,2,3", 77 "EventCode": "0XB7", 78 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 79 "MSRIndex": "0x1a6,0x1a7", 80 "MSRValue": "0x2104000002", 81 "Offcore": "1", 82 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 83 "SampleAfterValue": "100003", 84 "UMask": "0x1" 85 } 86]