1[ 2 { 3 "BriefDescription": "Far branch instructions retired.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "Errata": "SKL091", 7 "EventCode": "0xC4", 8 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 9 "PEBS": "1", 10 "PublicDescription": "This event counts far branch instructions retired.", 11 "SampleAfterValue": "100007", 12 "UMask": "0x40" 13 }, 14 { 15 "BriefDescription": "Total execution stalls.", 16 "Counter": "0,1,2,3", 17 "CounterHTOff": "0,1,2,3,4,5,6,7", 18 "CounterMask": "4", 19 "EventCode": "0xA3", 20 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 21 "SampleAfterValue": "2000003", 22 "UMask": "0x4" 23 }, 24 { 25 "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", 26 "Counter": "0,1,2,3", 27 "CounterHTOff": "0,1,2,3,4,5,6,7", 28 "EventCode": "0x0E", 29 "EventName": "UOPS_ISSUED.SLOW_LEA", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x20" 32 }, 33 { 34 "BriefDescription": "Cycles with less than 10 actually retired uops.", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "CounterMask": "10", 38 "EventCode": "0xC2", 39 "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 40 "Invert": "1", 41 "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", 42 "SampleAfterValue": "2000003", 43 "UMask": "0x2" 44 }, 45 { 46 "BriefDescription": "Thread cycles when thread is not in halt state", 47 "Counter": "0,1,2,3", 48 "CounterHTOff": "0,1,2,3,4,5,6,7", 49 "EventCode": "0x3C", 50 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 51 "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", 52 "SampleAfterValue": "2000003" 53 }, 54 { 55 "BriefDescription": "Cycles without actually retired uops.", 56 "Counter": "0,1,2,3", 57 "CounterHTOff": "0,1,2,3,4,5,6,7", 58 "CounterMask": "1", 59 "EventCode": "0xC2", 60 "EventName": "UOPS_RETIRED.STALL_CYCLES", 61 "Invert": "1", 62 "PublicDescription": "This event counts cycles without actually retired uops.", 63 "SampleAfterValue": "2000003", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", 68 "Counter": "0,1,2,3", 69 "CounterHTOff": "0,1,2,3,4,5,6,7", 70 "CounterMask": "1", 71 "EventCode": "0xB1", 72 "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", 73 "Invert": "1", 74 "SampleAfterValue": "2000003", 75 "UMask": "0x2" 76 }, 77 { 78 "AnyThread": "1", 79 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", 80 "Counter": "0,1,2,3", 81 "CounterHTOff": "0,1,2,3,4,5,6,7", 82 "EventCode": "0x0D", 83 "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", 84 "SampleAfterValue": "2000003", 85 "UMask": "0x1" 86 }, 87 { 88 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 89 "Counter": "0,1,2,3", 90 "CounterHTOff": "0,1,2,3,4,5,6,7", 91 "CounterMask": "4", 92 "EventCode": "0xA8", 93 "EventName": "LSD.CYCLES_4_UOPS", 94 "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", 95 "SampleAfterValue": "2000003", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Core cycles when the thread is not in halt state", 100 "Counter": "Fixed counter 1", 101 "CounterHTOff": "Fixed counter 1", 102 "EventName": "CPU_CLK_UNHALTED.THREAD", 103 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", 104 "SampleAfterValue": "2000003", 105 "UMask": "0x2" 106 }, 107 { 108 "AnyThread": "1", 109 "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", 110 "Counter": "0,1,2,3", 111 "CounterHTOff": "0,1,2,3,4,5,6,7", 112 "EventCode": "0x3C", 113 "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", 114 "SampleAfterValue": "25003", 115 "UMask": "0x1" 116 }, 117 { 118 "BriefDescription": "Direct and indirect near call instructions retired.", 119 "Counter": "0,1,2,3", 120 "CounterHTOff": "0,1,2,3,4,5,6,7", 121 "Errata": "SKL091", 122 "EventCode": "0xC4", 123 "EventName": "BR_INST_RETIRED.NEAR_CALL", 124 "PEBS": "1", 125 "PublicDescription": "This event counts both direct and indirect near call instructions retired.", 126 "SampleAfterValue": "100007", 127 "UMask": "0x2" 128 }, 129 { 130 "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 131 "Counter": "0,1,2,3", 132 "CounterHTOff": "0,1,2,3,4,5,6,7", 133 "CounterMask": "1", 134 "EventCode": "0x14", 135 "EventName": "ARITH.DIVIDER_ACTIVE", 136 "SampleAfterValue": "2000003", 137 "UMask": "0x1" 138 }, 139 { 140 "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 141 "Counter": "0,1,2,3", 142 "CounterHTOff": "0,1,2,3,4,5,6,7", 143 "EventCode": "0x3C", 144 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 145 "SampleAfterValue": "25003", 146 "UMask": "0x2" 147 }, 148 { 149 "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", 150 "Counter": "0,1,2,3", 151 "CounterHTOff": "0,1,2,3,4,5,6,7", 152 "EventCode": "0xC5", 153 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 154 "PEBS": "1", 155 "SampleAfterValue": "400009", 156 "UMask": "0x20" 157 }, 158 { 159 "BriefDescription": "Increments whenever there is an update to the LBR array.", 160 "Counter": "0,1,2,3", 161 "CounterHTOff": "0,1,2,3,4,5,6,7", 162 "EventCode": "0xCC", 163 "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", 164 "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", 165 "SampleAfterValue": "2000003", 166 "UMask": "0x20" 167 }, 168 { 169 "BriefDescription": "Instructions retired from execution.", 170 "Counter": "Fixed counter 0", 171 "CounterHTOff": "Fixed counter 0", 172 "EventName": "INST_RETIRED.ANY", 173 "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", 174 "SampleAfterValue": "2000003", 175 "UMask": "0x1" 176 }, 177 { 178 "BriefDescription": "Conditional branch instructions retired.", 179 "Counter": "0,1,2,3", 180 "CounterHTOff": "0,1,2,3,4,5,6,7", 181 "Errata": "SKL091", 182 "EventCode": "0xC4", 183 "EventName": "BR_INST_RETIRED.CONDITIONAL", 184 "PEBS": "1", 185 "PublicDescription": "This event counts conditional branch instructions retired.", 186 "SampleAfterValue": "400009", 187 "UMask": "0x1" 188 }, 189 { 190 "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", 191 "Counter": "0,1,2,3", 192 "CounterHTOff": "0,1,2,3,4,5,6,7", 193 "EventCode": "0x0D", 194 "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", 195 "SampleAfterValue": "2000003", 196 "UMask": "0x80" 197 }, 198 { 199 "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 200 "Counter": "0,1,2,3", 201 "CounterHTOff": "0,1,2,3,4,5,6,7", 202 "CounterMask": "1", 203 "EventCode": "0xB1", 204 "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", 205 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 206 "SampleAfterValue": "2000003", 207 "UMask": "0x1" 208 }, 209 { 210 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 211 "Counter": "0,1,2,3", 212 "CounterHTOff": "0,1,2,3,4,5,6,7", 213 "CounterMask": "1", 214 "EventCode": "0xB1", 215 "EventName": "UOPS_EXECUTED.STALL_CYCLES", 216 "Invert": "1", 217 "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", 218 "SampleAfterValue": "2000003", 219 "UMask": "0x1" 220 }, 221 { 222 "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", 223 "Counter": "0,1,2,3", 224 "CounterHTOff": "0,1,2,3,4,5,6,7", 225 "EventCode": "0xA6", 226 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", 227 "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", 228 "SampleAfterValue": "2000003", 229 "UMask": "0x10" 230 }, 231 { 232 "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", 233 "Counter": "0,1,2,3", 234 "CounterHTOff": "0,1,2,3,4,5,6,7", 235 "CounterMask": "5", 236 "EventCode": "0xA3", 237 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 238 "SampleAfterValue": "2000003", 239 "UMask": "0x5" 240 }, 241 { 242 "BriefDescription": "Mispredicted macro branch instructions retired.", 243 "Counter": "0,1,2,3", 244 "CounterHTOff": "0,1,2,3", 245 "EventCode": "0xC5", 246 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", 247 "PEBS": "2", 248 "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", 249 "SampleAfterValue": "400009", 250 "UMask": "0x4" 251 }, 252 { 253 "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 254 "Counter": "0,1,2,3", 255 "CounterHTOff": "0,1,2,3,4,5,6,7", 256 "CounterMask": "2", 257 "EventCode": "0xB1", 258 "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", 259 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 260 "SampleAfterValue": "2000003", 261 "UMask": "0x1" 262 }, 263 { 264 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 265 "Counter": "0,1,2,3", 266 "CounterHTOff": "0,1,2,3,4,5,6,7", 267 "EventCode": "0x3C", 268 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", 269 "SampleAfterValue": "25003", 270 "UMask": "0x1" 271 }, 272 { 273 "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 274 "Counter": "0,1,2,3", 275 "CounterHTOff": "0,1,2,3,4,5,6,7", 276 "EventCode": "0x3C", 277 "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 278 "SampleAfterValue": "25003", 279 "UMask": "0x2" 280 }, 281 { 282 "BriefDescription": "All (macro) branch instructions retired.", 283 "Counter": "0,1,2,3", 284 "CounterHTOff": "0,1,2,3,4,5,6,7", 285 "Errata": "SKL091", 286 "EventCode": "0xC4", 287 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 288 "PublicDescription": "Counts all (macro) branch instructions retired.", 289 "SampleAfterValue": "400009" 290 }, 291 { 292 "BriefDescription": "Cycles per thread when uops are executed in port 0", 293 "Counter": "0,1,2,3", 294 "CounterHTOff": "0,1,2,3,4,5,6,7", 295 "EventCode": "0xA1", 296 "EventName": "UOPS_DISPATCHED_PORT.PORT_0", 297 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", 298 "SampleAfterValue": "2000003", 299 "UMask": "0x1" 300 }, 301 { 302 "BriefDescription": "Cycles per thread when uops are executed in port 1", 303 "Counter": "0,1,2,3", 304 "CounterHTOff": "0,1,2,3,4,5,6,7", 305 "EventCode": "0xA1", 306 "EventName": "UOPS_DISPATCHED_PORT.PORT_1", 307 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", 308 "SampleAfterValue": "2000003", 309 "UMask": "0x2" 310 }, 311 { 312 "BriefDescription": "Cycles per thread when uops are executed in port 2", 313 "Counter": "0,1,2,3", 314 "CounterHTOff": "0,1,2,3,4,5,6,7", 315 "EventCode": "0xA1", 316 "EventName": "UOPS_DISPATCHED_PORT.PORT_2", 317 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.", 318 "SampleAfterValue": "2000003", 319 "UMask": "0x4" 320 }, 321 { 322 "BriefDescription": "Cycles per thread when uops are executed in port 3", 323 "Counter": "0,1,2,3", 324 "CounterHTOff": "0,1,2,3,4,5,6,7", 325 "EventCode": "0xA1", 326 "EventName": "UOPS_DISPATCHED_PORT.PORT_3", 327 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.", 328 "SampleAfterValue": "2000003", 329 "UMask": "0x8" 330 }, 331 { 332 "BriefDescription": "Cycles per thread when uops are executed in port 4", 333 "Counter": "0,1,2,3", 334 "CounterHTOff": "0,1,2,3,4,5,6,7", 335 "EventCode": "0xA1", 336 "EventName": "UOPS_DISPATCHED_PORT.PORT_4", 337 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.", 338 "SampleAfterValue": "2000003", 339 "UMask": "0x10" 340 }, 341 { 342 "BriefDescription": "Cycles per thread when uops are executed in port 5", 343 "Counter": "0,1,2,3", 344 "CounterHTOff": "0,1,2,3,4,5,6,7", 345 "EventCode": "0xA1", 346 "EventName": "UOPS_DISPATCHED_PORT.PORT_5", 347 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", 348 "SampleAfterValue": "2000003", 349 "UMask": "0x20" 350 }, 351 { 352 "BriefDescription": "Cycles per thread when uops are executed in port 6", 353 "Counter": "0,1,2,3", 354 "CounterHTOff": "0,1,2,3,4,5,6,7", 355 "EventCode": "0xA1", 356 "EventName": "UOPS_DISPATCHED_PORT.PORT_6", 357 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", 358 "SampleAfterValue": "2000003", 359 "UMask": "0x40" 360 }, 361 { 362 "BriefDescription": "Cycles per thread when uops are executed in port 7", 363 "Counter": "0,1,2,3", 364 "CounterHTOff": "0,1,2,3,4,5,6,7", 365 "EventCode": "0xA1", 366 "EventName": "UOPS_DISPATCHED_PORT.PORT_7", 367 "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.", 368 "SampleAfterValue": "2000003", 369 "UMask": "0x80" 370 }, 371 { 372 "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", 373 "Counter": "0,1,2,3", 374 "CounterHTOff": "0,1,2,3,4,5,6,7", 375 "EventCode": "0xA6", 376 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", 377 "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", 378 "SampleAfterValue": "2000003", 379 "UMask": "0x8" 380 }, 381 { 382 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", 383 "Counter": "0,1,2,3", 384 "CounterHTOff": "0,1,2,3,4,5,6,7", 385 "CounterMask": "1", 386 "EdgeDetect": "1", 387 "EventCode": "0x5E", 388 "EventName": "RS_EVENTS.EMPTY_END", 389 "Invert": "1", 390 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues.", 391 "SampleAfterValue": "2000003", 392 "UMask": "0x1" 393 }, 394 { 395 "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", 396 "Counter": "0,1,2,3", 397 "CounterHTOff": "0,1,2,3,4,5,6,7", 398 "CounterMask": "1", 399 "EventCode": "0x0E", 400 "EventName": "UOPS_ISSUED.STALL_CYCLES", 401 "Invert": "1", 402 "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", 403 "SampleAfterValue": "2000003", 404 "UMask": "0x1" 405 }, 406 { 407 "BriefDescription": "Number of Uops delivered by the LSD.", 408 "Counter": "0,1,2,3", 409 "CounterHTOff": "0,1,2,3,4,5,6,7", 410 "EventCode": "0xA8", 411 "EventName": "LSD.UOPS", 412 "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).", 413 "SampleAfterValue": "2000003", 414 "UMask": "0x1" 415 }, 416 { 417 "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 418 "Counter": "0,1,2,3", 419 "CounterHTOff": "0,1,2,3,4,5,6,7", 420 "EventCode": "0x87", 421 "EventName": "ILD_STALL.LCP", 422 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 423 "SampleAfterValue": "2000003", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "Taken branch instructions retired.", 428 "Counter": "0,1,2,3", 429 "CounterHTOff": "0,1,2,3,4,5,6,7", 430 "Errata": "SKL091", 431 "EventCode": "0xC4", 432 "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 433 "PEBS": "1", 434 "PublicDescription": "This event counts taken branch instructions retired.", 435 "SampleAfterValue": "400009", 436 "UMask": "0x20" 437 }, 438 { 439 "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", 440 "Counter": "0,1,2,3", 441 "CounterHTOff": "0,1,2,3,4,5,6,7", 442 "EventCode": "0x0E", 443 "EventName": "UOPS_ISSUED.ANY", 444 "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", 445 "SampleAfterValue": "2000003", 446 "UMask": "0x1" 447 }, 448 { 449 "BriefDescription": "Resource-related stall cycles", 450 "Counter": "0,1,2,3", 451 "CounterHTOff": "0,1,2,3,4,5,6,7", 452 "EventCode": "0xa2", 453 "EventName": "RESOURCE_STALLS.ANY", 454 "PublicDescription": "Counts resource-related stall cycles.", 455 "SampleAfterValue": "2000003", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 460 "Counter": "0,1,2,3", 461 "CounterHTOff": "0,1,2,3", 462 "CounterMask": "20", 463 "EventCode": "0xA3", 464 "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", 465 "SampleAfterValue": "2000003", 466 "UMask": "0x14" 467 }, 468 { 469 "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", 470 "Counter": "0,1,2,3", 471 "CounterHTOff": "0,1,2,3,4,5,6,7", 472 "EventCode": "0xA6", 473 "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 474 "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", 475 "SampleAfterValue": "2000003", 476 "UMask": "0x1" 477 }, 478 { 479 "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 480 "Counter": "0,1,2,3", 481 "CounterHTOff": "0,1,2,3,4,5,6,7", 482 "EventCode": "0xA2", 483 "EventName": "RESOURCE_STALLS.SB", 484 "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", 485 "SampleAfterValue": "2000003", 486 "UMask": "0x8" 487 }, 488 { 489 "BriefDescription": "Not taken branch instructions retired.", 490 "Counter": "0,1,2,3", 491 "CounterHTOff": "0,1,2,3,4,5,6,7", 492 "Errata": "SKL091", 493 "EventCode": "0xC4", 494 "EventName": "BR_INST_RETIRED.NOT_TAKEN", 495 "PublicDescription": "This event counts not taken branch instructions retired.", 496 "SampleAfterValue": "400009", 497 "UMask": "0x10" 498 }, 499 { 500 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 501 "Counter": "0,1,2,3", 502 "CounterHTOff": "0,1,2,3,4,5,6,7", 503 "CounterMask": "12", 504 "EventCode": "0xA3", 505 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 506 "SampleAfterValue": "2000003", 507 "UMask": "0xc" 508 }, 509 { 510 "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", 511 "Counter": "0,1,2,3", 512 "CounterHTOff": "0,1,2,3,4,5,6,7", 513 "EventCode": "0xA6", 514 "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", 515 "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", 516 "SampleAfterValue": "2000003", 517 "UMask": "0x4" 518 }, 519 { 520 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 521 "Counter": "0,1,2,3", 522 "CounterHTOff": "0,1,2,3,4,5,6,7", 523 "Errata": "SKL091, SKL044", 524 "EventCode": "0xC0", 525 "EventName": "INST_RETIRED.ANY_P", 526 "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", 527 "SampleAfterValue": "2000003" 528 }, 529 { 530 "BriefDescription": "Counts the number of x87 uops dispatched.", 531 "Counter": "0,1,2,3", 532 "CounterHTOff": "0,1,2,3,4,5,6,7", 533 "EventCode": "0xB1", 534 "EventName": "UOPS_EXECUTED.X87", 535 "PublicDescription": "Counts the number of x87 uops executed.", 536 "SampleAfterValue": "2000003", 537 "UMask": "0x10" 538 }, 539 { 540 "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", 541 "Counter": "0,1,2,3", 542 "CounterHTOff": "0,1,2,3,4,5,6,7", 543 "EventCode": "0x4C", 544 "EventName": "LOAD_HIT_PRE.SW_PF", 545 "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", 546 "SampleAfterValue": "100003", 547 "UMask": "0x1" 548 }, 549 { 550 "BriefDescription": "Mispredicted direct and indirect near call instructions retired.", 551 "Counter": "0,1,2,3", 552 "CounterHTOff": "0,1,2,3,4,5,6,7", 553 "EventCode": "0xC5", 554 "EventName": "BR_MISP_RETIRED.NEAR_CALL", 555 "PEBS": "1", 556 "PublicDescription": "Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.", 557 "SampleAfterValue": "400009", 558 "UMask": "0x2" 559 }, 560 { 561 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 562 "Counter": "0,1,2,3", 563 "CounterHTOff": "0,1,2,3,4,5,6,7", 564 "EventCode": "0xB1", 565 "EventName": "UOPS_EXECUTED.THREAD", 566 "PublicDescription": "Number of uops to be executed per-thread each cycle.", 567 "SampleAfterValue": "2000003", 568 "UMask": "0x1" 569 }, 570 { 571 "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 572 "Counter": "0,1,2,3", 573 "CounterHTOff": "0,1,2,3,4,5,6,7", 574 "CounterMask": "3", 575 "EventCode": "0xB1", 576 "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", 577 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 578 "SampleAfterValue": "2000003", 579 "UMask": "0x1" 580 }, 581 { 582 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3,4,5,6,7", 585 "CounterMask": "1", 586 "EventCode": "0xA8", 587 "EventName": "LSD.CYCLES_ACTIVE", 588 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 589 "SampleAfterValue": "2000003", 590 "UMask": "0x1" 591 }, 592 { 593 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", 594 "Counter": "0,1,2,3", 595 "CounterHTOff": "0,1,2,3,4,5,6,7", 596 "EventCode": "0x0D", 597 "EventName": "INT_MISC.RECOVERY_CYCLES", 598 "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", 599 "SampleAfterValue": "2000003", 600 "UMask": "0x1" 601 }, 602 { 603 "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 604 "Counter": "0,1,2,3", 605 "CounterHTOff": "0,1,2,3,4,5,6,7", 606 "EventCode": "0x3C", 607 "EventName": "CPU_CLK_UNHALTED.REF_XCLK", 608 "SampleAfterValue": "25003", 609 "UMask": "0x1" 610 }, 611 { 612 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 613 "Counter": "0,1,2,3", 614 "CounterHTOff": "0,1,2,3,4,5,6,7", 615 "CounterMask": "8", 616 "EventCode": "0xA3", 617 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 618 "SampleAfterValue": "2000003", 619 "UMask": "0x8" 620 }, 621 { 622 "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", 623 "Counter": "1", 624 "CounterHTOff": "1", 625 "Errata": "SKL091, SKL044", 626 "EventCode": "0xC0", 627 "EventName": "INST_RETIRED.PREC_DIST", 628 "PEBS": "2", 629 "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled.", 630 "SampleAfterValue": "2000003", 631 "UMask": "0x1" 632 }, 633 { 634 "BriefDescription": "Not taken branch instructions retired.", 635 "Counter": "0,1,2,3", 636 "CounterHTOff": "0,1,2,3,4,5,6,7", 637 "Errata": "SKL091", 638 "EventCode": "0xc4", 639 "EventName": "BR_INST_RETIRED.COND_NTAKEN", 640 "PublicDescription": "This event counts not taken branch instructions retired.", 641 "SampleAfterValue": "400009", 642 "UMask": "0x10" 643 }, 644 { 645 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 646 "Counter": "0,1,2,3", 647 "CounterHTOff": "0,1,2,3,4,5,6,7", 648 "CounterMask": "3", 649 "EventCode": "0xB1", 650 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 651 "SampleAfterValue": "2000003", 652 "UMask": "0x2" 653 }, 654 { 655 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 656 "Counter": "0,1,2,3", 657 "CounterHTOff": "0,1,2,3,4,5,6,7", 658 "CounterMask": "1", 659 "EventCode": "0xB1", 660 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 661 "SampleAfterValue": "2000003", 662 "UMask": "0x2" 663 }, 664 { 665 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 666 "Counter": "0,1,2,3", 667 "CounterHTOff": "0,1,2,3,4,5,6,7", 668 "CounterMask": "4", 669 "EventCode": "0xB1", 670 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 671 "SampleAfterValue": "2000003", 672 "UMask": "0x2" 673 }, 674 { 675 "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.", 676 "Counter": "0,1,2,3", 677 "CounterHTOff": "0,1,2,3,4,5,6,7", 678 "EventCode": "0xC1", 679 "EventName": "OTHER_ASSISTS.ANY", 680 "SampleAfterValue": "100003", 681 "UMask": "0x3f" 682 }, 683 { 684 "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.", 685 "Counter": "0,1,2,3", 686 "CounterHTOff": "0,1,2,3,4,5,6,7", 687 "EventCode": "0xA6", 688 "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", 689 "SampleAfterValue": "2000003", 690 "UMask": "0x40" 691 }, 692 { 693 "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 694 "Counter": "0,1,2,3", 695 "CounterHTOff": "0,1,2,3,4,5,6,7", 696 "CounterMask": "16", 697 "EventCode": "0xA3", 698 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 699 "SampleAfterValue": "2000003", 700 "UMask": "0x10" 701 }, 702 { 703 "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.", 704 "Counter": "0,1,2,3", 705 "CounterHTOff": "0,1,2,3,4,5,6,7", 706 "EventCode": "0xCC", 707 "EventName": "ROB_MISC_EVENTS.PAUSE_INST", 708 "SampleAfterValue": "2000003", 709 "UMask": "0x40" 710 }, 711 { 712 "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 713 "Counter": "0,1,2,3", 714 "CounterHTOff": "0,1,2,3,4,5,6,7", 715 "CounterMask": "4", 716 "EventCode": "0xB1", 717 "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", 718 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 719 "SampleAfterValue": "2000003", 720 "UMask": "0x1" 721 }, 722 { 723 "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.", 724 "Counter": "0,1,2,3", 725 "CounterHTOff": "0,1,2,3,4,5,6,7", 726 "EventCode": "0x59", 727 "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", 728 "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.", 729 "SampleAfterValue": "2000003", 730 "UMask": "0x1" 731 }, 732 { 733 "BriefDescription": "Retirement slots used.", 734 "Counter": "0,1,2,3", 735 "CounterHTOff": "0,1,2,3,4,5,6,7", 736 "EventCode": "0xC2", 737 "EventName": "UOPS_RETIRED.RETIRE_SLOTS", 738 "PublicDescription": "Counts the retirement slots used.", 739 "SampleAfterValue": "2000003", 740 "UMask": "0x2" 741 }, 742 { 743 "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", 744 "Counter": "0,1,2,3", 745 "CounterHTOff": "0,1,2,3,4,5,6,7", 746 "EventCode": "0x0E", 747 "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 748 "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", 749 "SampleAfterValue": "2000003", 750 "UMask": "0x2" 751 }, 752 { 753 "BriefDescription": "Return instructions retired.", 754 "Counter": "0,1,2,3", 755 "CounterHTOff": "0,1,2,3,4,5,6,7", 756 "Errata": "SKL091", 757 "EventCode": "0xC4", 758 "EventName": "BR_INST_RETIRED.NEAR_RETURN", 759 "PEBS": "1", 760 "PublicDescription": "This event counts return instructions retired.", 761 "SampleAfterValue": "100007", 762 "UMask": "0x8" 763 }, 764 { 765 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 766 "Counter": "0,1,2,3", 767 "CounterHTOff": "0,1,2,3,4,5,6,7", 768 "CounterMask": "2", 769 "EventCode": "0xB1", 770 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 771 "SampleAfterValue": "2000003", 772 "UMask": "0x2" 773 }, 774 { 775 "BriefDescription": "Mispredicted conditional branch instructions retired.", 776 "Counter": "0,1,2,3", 777 "CounterHTOff": "0,1,2,3,4,5,6,7", 778 "EventCode": "0xC5", 779 "EventName": "BR_MISP_RETIRED.CONDITIONAL", 780 "PEBS": "1", 781 "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", 782 "SampleAfterValue": "400009", 783 "UMask": "0x1" 784 }, 785 { 786 "BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.", 787 "Counter": "0,2,3", 788 "CounterHTOff": "0,2,3", 789 "CounterMask": "10", 790 "Errata": "SKL091, SKL044", 791 "EventCode": "0xC0", 792 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", 793 "Invert": "1", 794 "PEBS": "2", 795 "PublicDescription": "Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16)", 796 "SampleAfterValue": "2000003", 797 "UMask": "0x1" 798 }, 799 { 800 "BriefDescription": "False dependencies in MOB due to partial compare on address.", 801 "Counter": "0,1,2,3", 802 "CounterHTOff": "0,1,2,3,4,5,6,7", 803 "EventCode": "0x07", 804 "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 805 "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", 806 "SampleAfterValue": "100003", 807 "UMask": "0x1" 808 }, 809 { 810 "BriefDescription": "Number of machine clears (nukes) of any type.", 811 "Counter": "0,1,2,3", 812 "CounterHTOff": "0,1,2,3,4,5,6,7", 813 "CounterMask": "1", 814 "EdgeDetect": "1", 815 "EventCode": "0xC3", 816 "EventName": "MACHINE_CLEARS.COUNT", 817 "SampleAfterValue": "100003", 818 "UMask": "0x1" 819 }, 820 { 821 "AnyThread": "1", 822 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 823 "Counter": "Fixed counter 1", 824 "CounterHTOff": "Fixed counter 1", 825 "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", 826 "SampleAfterValue": "2000003", 827 "UMask": "0x2" 828 }, 829 { 830 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 831 "Counter": "0,1,2,3", 832 "CounterHTOff": "0,1,2,3,4,5,6,7", 833 "EventCode": "0xE6", 834 "EventName": "BACLEARS.ANY", 835 "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 836 "SampleAfterValue": "100003", 837 "UMask": "0x1" 838 }, 839 { 840 "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 841 "Counter": "0,1,2,3", 842 "CounterHTOff": "0,1,2,3,4,5,6,7", 843 "EventCode": "0x03", 844 "EventName": "LD_BLOCKS.STORE_FORWARD", 845 "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", 846 "SampleAfterValue": "100003", 847 "UMask": "0x2" 848 }, 849 { 850 "AnyThread": "1", 851 "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", 852 "Counter": "0,1,2,3", 853 "CounterHTOff": "0,1,2,3,4,5,6,7", 854 "EventCode": "0x3C", 855 "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", 856 "SampleAfterValue": "25003", 857 "UMask": "0x1" 858 }, 859 { 860 "BriefDescription": "Reference cycles when the core is not in halt state.", 861 "Counter": "Fixed counter 2", 862 "CounterHTOff": "Fixed counter 2", 863 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 864 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 865 "SampleAfterValue": "2000003", 866 "UMask": "0x3" 867 }, 868 { 869 "BriefDescription": "All mispredicted macro branch instructions retired.", 870 "Counter": "0,1,2,3", 871 "CounterHTOff": "0,1,2,3,4,5,6,7", 872 "EventCode": "0xC5", 873 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 874 "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", 875 "SampleAfterValue": "400009" 876 }, 877 { 878 "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", 879 "Counter": "0,1,2,3", 880 "CounterHTOff": "0,1,2,3,4,5,6,7", 881 "EventCode": "0x03", 882 "EventName": "LD_BLOCKS.NO_SR", 883 "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 884 "SampleAfterValue": "100003", 885 "UMask": "0x8" 886 }, 887 { 888 "BriefDescription": "Self-modifying code (SMC) detected.", 889 "Counter": "0,1,2,3", 890 "CounterHTOff": "0,1,2,3,4,5,6,7", 891 "EventCode": "0xC3", 892 "EventName": "MACHINE_CLEARS.SMC", 893 "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", 894 "SampleAfterValue": "100003", 895 "UMask": "0x4" 896 }, 897 { 898 "AnyThread": "1", 899 "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 900 "Counter": "0,1,2,3", 901 "CounterHTOff": "0,1,2,3,4,5,6,7", 902 "EventCode": "0x3C", 903 "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", 904 "SampleAfterValue": "2000003" 905 }, 906 { 907 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", 908 "Counter": "0,1,2,3", 909 "CounterHTOff": "0,1,2,3,4,5,6,7", 910 "EventCode": "0x5E", 911 "EventName": "RS_EVENTS.EMPTY_CYCLES", 912 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", 913 "SampleAfterValue": "2000003", 914 "UMask": "0x1" 915 }, 916 { 917 "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.", 918 "Counter": "0,1,2,3", 919 "CounterHTOff": "0,1,2,3,4,5,6,7", 920 "CounterMask": "1", 921 "EdgeDetect": "1", 922 "EventCode": "0x3C", 923 "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", 924 "PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", 925 "SampleAfterValue": "100007" 926 }, 927 { 928 "BriefDescription": "All (macro) branch instructions retired.", 929 "Counter": "0,1,2,3", 930 "CounterHTOff": "0,1,2,3", 931 "Errata": "SKL091", 932 "EventCode": "0xC4", 933 "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", 934 "PEBS": "2", 935 "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", 936 "SampleAfterValue": "400009", 937 "UMask": "0x4" 938 }, 939 { 940 "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", 941 "Counter": "0,1,2,3", 942 "CounterHTOff": "0,1,2,3,4,5,6,7", 943 "EventCode": "0xA6", 944 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", 945 "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", 946 "SampleAfterValue": "2000003", 947 "UMask": "0x2" 948 }, 949 { 950 "BriefDescription": "Number of uops executed on the core.", 951 "Counter": "0,1,2,3", 952 "CounterHTOff": "0,1,2,3,4,5,6,7", 953 "EventCode": "0xB1", 954 "EventName": "UOPS_EXECUTED.CORE", 955 "PublicDescription": "Number of uops executed from any thread.", 956 "SampleAfterValue": "2000003", 957 "UMask": "0x2" 958 }, 959 { 960 "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", 961 "Counter": "0,1,2,3", 962 "CounterHTOff": "0,1,2,3,4,5,6,7", 963 "CounterMask": "1", 964 "EventCode": "0xA3", 965 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 966 "SampleAfterValue": "2000003", 967 "UMask": "0x1" 968 } 969]