1[ 2 { 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "Errata": "BDM69", 7 "EventCode": "0x08", 8 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 9 "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 10 "SampleAfterValue": "100003", 11 "UMask": "0x1" 12 }, 13 { 14 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", 15 "Counter": "0,1,2,3", 16 "CounterHTOff": "0,1,2,3,4,5,6,7", 17 "EventCode": "0x08", 18 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x60" 21 }, 22 { 23 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0x08", 27 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 28 "SampleAfterValue": "2000003", 29 "UMask": "0x40" 30 }, 31 { 32 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", 33 "Counter": "0,1,2,3", 34 "CounterHTOff": "0,1,2,3,4,5,6,7", 35 "EventCode": "0x08", 36 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 37 "SampleAfterValue": "2000003", 38 "UMask": "0x20" 39 }, 40 { 41 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 42 "Counter": "0,1,2,3", 43 "CounterHTOff": "0,1,2,3,4,5,6,7", 44 "Errata": "BDM69", 45 "EventCode": "0x08", 46 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 47 "SampleAfterValue": "100003", 48 "UMask": "0xe" 49 }, 50 { 51 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 52 "Counter": "0,1,2,3", 53 "CounterHTOff": "0,1,2,3,4,5,6,7", 54 "Errata": "BDM69", 55 "EventCode": "0x08", 56 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 57 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 58 "SampleAfterValue": "2000003", 59 "UMask": "0x8" 60 }, 61 { 62 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 63 "Counter": "0,1,2,3", 64 "CounterHTOff": "0,1,2,3,4,5,6,7", 65 "Errata": "BDM69", 66 "EventCode": "0x08", 67 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 68 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 69 "SampleAfterValue": "2000003", 70 "UMask": "0x4" 71 }, 72 { 73 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "Errata": "BDM69", 77 "EventCode": "0x08", 78 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 79 "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x2" 82 }, 83 { 84 "BriefDescription": "Cycles when PMH is busy with page walks", 85 "Counter": "0,1,2,3", 86 "CounterHTOff": "0,1,2,3,4,5,6,7", 87 "Errata": "BDM69", 88 "EventCode": "0x08", 89 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 90 "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", 91 "SampleAfterValue": "2000003", 92 "UMask": "0x10" 93 }, 94 { 95 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 96 "Counter": "0,1,2,3", 97 "CounterHTOff": "0,1,2,3,4,5,6,7", 98 "Errata": "BDM69", 99 "EventCode": "0x49", 100 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 101 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 102 "SampleAfterValue": "100003", 103 "UMask": "0x1" 104 }, 105 { 106 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 107 "Counter": "0,1,2,3", 108 "CounterHTOff": "0,1,2,3,4,5,6,7", 109 "EventCode": "0x49", 110 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 111 "SampleAfterValue": "100003", 112 "UMask": "0x60" 113 }, 114 { 115 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", 116 "Counter": "0,1,2,3", 117 "CounterHTOff": "0,1,2,3,4,5,6,7", 118 "EventCode": "0x49", 119 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 120 "SampleAfterValue": "100003", 121 "UMask": "0x40" 122 }, 123 { 124 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", 125 "Counter": "0,1,2,3", 126 "CounterHTOff": "0,1,2,3,4,5,6,7", 127 "EventCode": "0x49", 128 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 129 "SampleAfterValue": "100003", 130 "UMask": "0x20" 131 }, 132 { 133 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", 134 "Counter": "0,1,2,3", 135 "CounterHTOff": "0,1,2,3,4,5,6,7", 136 "Errata": "BDM69", 137 "EventCode": "0x49", 138 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 139 "SampleAfterValue": "100003", 140 "UMask": "0xe" 141 }, 142 { 143 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", 144 "Counter": "0,1,2,3", 145 "CounterHTOff": "0,1,2,3,4,5,6,7", 146 "Errata": "BDM69", 147 "EventCode": "0x49", 148 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 149 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 150 "SampleAfterValue": "100003", 151 "UMask": "0x8" 152 }, 153 { 154 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "Errata": "BDM69", 158 "EventCode": "0x49", 159 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 160 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 161 "SampleAfterValue": "100003", 162 "UMask": "0x4" 163 }, 164 { 165 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 166 "Counter": "0,1,2,3", 167 "CounterHTOff": "0,1,2,3,4,5,6,7", 168 "Errata": "BDM69", 169 "EventCode": "0x49", 170 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 171 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 172 "SampleAfterValue": "100003", 173 "UMask": "0x2" 174 }, 175 { 176 "BriefDescription": "Cycles when PMH is busy with page walks", 177 "Counter": "0,1,2,3", 178 "CounterHTOff": "0,1,2,3,4,5,6,7", 179 "Errata": "BDM69", 180 "EventCode": "0x49", 181 "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 182 "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", 183 "SampleAfterValue": "100003", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "Cycle count for an Extended Page table walk.", 188 "Counter": "0,1,2,3", 189 "CounterHTOff": "0,1,2,3,4,5,6,7", 190 "EventCode": "0x4F", 191 "EventName": "EPT.WALK_CYCLES", 192 "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", 193 "SampleAfterValue": "2000003", 194 "UMask": "0x10" 195 }, 196 { 197 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 198 "Counter": "0,1,2,3", 199 "CounterHTOff": "0,1,2,3,4,5,6,7", 200 "EventCode": "0xAE", 201 "EventName": "ITLB.ITLB_FLUSH", 202 "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", 203 "SampleAfterValue": "100007", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Misses at all ITLB levels that cause page walks", 208 "Counter": "0,1,2,3", 209 "CounterHTOff": "0,1,2,3,4,5,6,7", 210 "Errata": "BDM69", 211 "EventCode": "0x85", 212 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 213 "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", 214 "SampleAfterValue": "100003", 215 "UMask": "0x1" 216 }, 217 { 218 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", 219 "Counter": "0,1,2,3", 220 "CounterHTOff": "0,1,2,3,4,5,6,7", 221 "EventCode": "0x85", 222 "EventName": "ITLB_MISSES.STLB_HIT", 223 "SampleAfterValue": "100003", 224 "UMask": "0x60" 225 }, 226 { 227 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", 228 "Counter": "0,1,2,3", 229 "CounterHTOff": "0,1,2,3,4,5,6,7", 230 "EventCode": "0x85", 231 "EventName": "ITLB_MISSES.STLB_HIT_2M", 232 "SampleAfterValue": "100003", 233 "UMask": "0x40" 234 }, 235 { 236 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", 237 "Counter": "0,1,2,3", 238 "CounterHTOff": "0,1,2,3,4,5,6,7", 239 "EventCode": "0x85", 240 "EventName": "ITLB_MISSES.STLB_HIT_4K", 241 "SampleAfterValue": "100003", 242 "UMask": "0x20" 243 }, 244 { 245 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", 246 "Counter": "0,1,2,3", 247 "CounterHTOff": "0,1,2,3,4,5,6,7", 248 "Errata": "BDM69", 249 "EventCode": "0x85", 250 "EventName": "ITLB_MISSES.WALK_COMPLETED", 251 "SampleAfterValue": "100003", 252 "UMask": "0xe" 253 }, 254 { 255 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3,4,5,6,7", 258 "Errata": "BDM69", 259 "EventCode": "0x85", 260 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 261 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 262 "SampleAfterValue": "100003", 263 "UMask": "0x8" 264 }, 265 { 266 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 267 "Counter": "0,1,2,3", 268 "CounterHTOff": "0,1,2,3,4,5,6,7", 269 "Errata": "BDM69", 270 "EventCode": "0x85", 271 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 272 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 273 "SampleAfterValue": "100003", 274 "UMask": "0x4" 275 }, 276 { 277 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 278 "Counter": "0,1,2,3", 279 "CounterHTOff": "0,1,2,3,4,5,6,7", 280 "Errata": "BDM69", 281 "EventCode": "0x85", 282 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 283 "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", 284 "SampleAfterValue": "100003", 285 "UMask": "0x2" 286 }, 287 { 288 "BriefDescription": "Cycles when PMH is busy with page walks", 289 "Counter": "0,1,2,3", 290 "CounterHTOff": "0,1,2,3,4,5,6,7", 291 "Errata": "BDM69", 292 "EventCode": "0x85", 293 "EventName": "ITLB_MISSES.WALK_DURATION", 294 "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", 295 "SampleAfterValue": "100003", 296 "UMask": "0x10" 297 }, 298 { 299 "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", 300 "Counter": "0,1,2,3", 301 "CounterHTOff": "0,1,2,3", 302 "Errata": "BDM69, BDM98", 303 "EventCode": "0xBC", 304 "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 305 "SampleAfterValue": "2000003", 306 "UMask": "0x11" 307 }, 308 { 309 "BriefDescription": "Number of DTLB page walker hits in the L2.", 310 "Counter": "0,1,2,3", 311 "CounterHTOff": "0,1,2,3", 312 "Errata": "BDM69, BDM98", 313 "EventCode": "0xBC", 314 "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 315 "SampleAfterValue": "2000003", 316 "UMask": "0x12" 317 }, 318 { 319 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", 320 "Counter": "0,1,2,3", 321 "CounterHTOff": "0,1,2,3", 322 "Errata": "BDM69, BDM98", 323 "EventCode": "0xBC", 324 "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 325 "SampleAfterValue": "2000003", 326 "UMask": "0x14" 327 }, 328 { 329 "BriefDescription": "Number of DTLB page walker hits in Memory.", 330 "Counter": "0,1,2,3", 331 "CounterHTOff": "0,1,2,3", 332 "Errata": "BDM69, BDM98", 333 "EventCode": "0xBC", 334 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 335 "SampleAfterValue": "2000003", 336 "UMask": "0x18" 337 }, 338 { 339 "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", 340 "Counter": "0,1,2,3", 341 "CounterHTOff": "0,1,2,3", 342 "Errata": "BDM69, BDM98", 343 "EventCode": "0xBC", 344 "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 345 "SampleAfterValue": "2000003", 346 "UMask": "0x21" 347 }, 348 { 349 "BriefDescription": "Number of ITLB page walker hits in the L2.", 350 "Counter": "0,1,2,3", 351 "CounterHTOff": "0,1,2,3", 352 "Errata": "BDM69, BDM98", 353 "EventCode": "0xBC", 354 "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 355 "SampleAfterValue": "2000003", 356 "UMask": "0x22" 357 }, 358 { 359 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", 360 "Counter": "0,1,2,3", 361 "CounterHTOff": "0,1,2,3", 362 "Errata": "BDM69, BDM98", 363 "EventCode": "0xBC", 364 "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 365 "SampleAfterValue": "2000003", 366 "UMask": "0x24" 367 }, 368 { 369 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 370 "Counter": "0,1,2,3", 371 "CounterHTOff": "0,1,2,3,4,5,6,7", 372 "EventCode": "0xBD", 373 "EventName": "TLB_FLUSH.DTLB_THREAD", 374 "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", 375 "SampleAfterValue": "100007", 376 "UMask": "0x1" 377 }, 378 { 379 "BriefDescription": "STLB flush attempts", 380 "Counter": "0,1,2,3", 381 "CounterHTOff": "0,1,2,3,4,5,6,7", 382 "EventCode": "0xBD", 383 "EventName": "TLB_FLUSH.STLB_ANY", 384 "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", 385 "SampleAfterValue": "100007", 386 "UMask": "0x20" 387 } 388]