1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xc8", 7 "EventName": "HLE_RETIRED.ABORTED", 8 "PEBS": "1", 9 "PublicDescription": "Number of times HLE abort was triggered.", 10 "SampleAfterValue": "2000003", 11 "UMask": "0x4" 12 }, 13 { 14 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 15 "Counter": "0,1,2,3", 16 "CounterHTOff": "0,1,2,3,4,5,6,7", 17 "EventCode": "0xc8", 18 "EventName": "HLE_RETIRED.ABORTED_MISC1", 19 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 20 "SampleAfterValue": "2000003", 21 "UMask": "0x8" 22 }, 23 { 24 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 25 "Counter": "0,1,2,3", 26 "CounterHTOff": "0,1,2,3,4,5,6,7", 27 "EventCode": "0xc8", 28 "EventName": "HLE_RETIRED.ABORTED_MISC2", 29 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x10" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC3", 39 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x20" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 45 "Counter": "0,1,2,3", 46 "CounterHTOff": "0,1,2,3,4,5,6,7", 47 "EventCode": "0xc8", 48 "EventName": "HLE_RETIRED.ABORTED_MISC4", 49 "PublicDescription": "Number of times HLE caused a fault.", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x40" 52 }, 53 { 54 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0xc8", 58 "EventName": "HLE_RETIRED.ABORTED_MISC5", 59 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x80" 62 }, 63 { 64 "BriefDescription": "Number of times HLE commit succeeded", 65 "Counter": "0,1,2,3", 66 "CounterHTOff": "0,1,2,3,4,5,6,7", 67 "EventCode": "0xc8", 68 "EventName": "HLE_RETIRED.COMMIT", 69 "PublicDescription": "Number of times HLE commit succeeded.", 70 "SampleAfterValue": "2000003", 71 "UMask": "0x2" 72 }, 73 { 74 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 75 "Counter": "0,1,2,3", 76 "CounterHTOff": "0,1,2,3,4,5,6,7", 77 "EventCode": "0xc8", 78 "EventName": "HLE_RETIRED.START", 79 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x1" 82 }, 83 { 84 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 85 "Counter": "0,1,2,3", 86 "CounterHTOff": "0,1,2,3,4,5,6,7", 87 "EventCode": "0xC3", 88 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 89 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x2" 92 }, 93 { 94 "BriefDescription": "Randomly selected loads with latency value being above 128", 95 "Counter": "3", 96 "CounterHTOff": "3", 97 "Data_LA": "1", 98 "Errata": "BDM100, BDM35", 99 "EventCode": "0xcd", 100 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 101 "MSRIndex": "0x3F6", 102 "MSRValue": "0x80", 103 "PEBS": "2", 104 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 105 "SampleAfterValue": "1009", 106 "TakenAlone": "1", 107 "UMask": "0x1" 108 }, 109 { 110 "BriefDescription": "Randomly selected loads with latency value being above 16", 111 "Counter": "3", 112 "CounterHTOff": "3", 113 "Data_LA": "1", 114 "Errata": "BDM100, BDM35", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x10", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 121 "SampleAfterValue": "20011", 122 "TakenAlone": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Randomly selected loads with latency value being above 256", 127 "Counter": "3", 128 "CounterHTOff": "3", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x100", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 137 "SampleAfterValue": "503", 138 "TakenAlone": "1", 139 "UMask": "0x1" 140 }, 141 { 142 "BriefDescription": "Randomly selected loads with latency value being above 32", 143 "Counter": "3", 144 "CounterHTOff": "3", 145 "Data_LA": "1", 146 "Errata": "BDM100, BDM35", 147 "EventCode": "0xcd", 148 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 149 "MSRIndex": "0x3F6", 150 "MSRValue": "0x20", 151 "PEBS": "2", 152 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 153 "SampleAfterValue": "100007", 154 "TakenAlone": "1", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Randomly selected loads with latency value being above 4", 159 "Counter": "3", 160 "CounterHTOff": "3", 161 "Data_LA": "1", 162 "Errata": "BDM100, BDM35", 163 "EventCode": "0xcd", 164 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 165 "MSRIndex": "0x3F6", 166 "MSRValue": "0x4", 167 "PEBS": "2", 168 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 169 "SampleAfterValue": "100003", 170 "TakenAlone": "1", 171 "UMask": "0x1" 172 }, 173 { 174 "BriefDescription": "Randomly selected loads with latency value being above 512", 175 "Counter": "3", 176 "CounterHTOff": "3", 177 "Data_LA": "1", 178 "Errata": "BDM100, BDM35", 179 "EventCode": "0xcd", 180 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 181 "MSRIndex": "0x3F6", 182 "MSRValue": "0x200", 183 "PEBS": "2", 184 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 185 "SampleAfterValue": "101", 186 "TakenAlone": "1", 187 "UMask": "0x1" 188 }, 189 { 190 "BriefDescription": "Randomly selected loads with latency value being above 64", 191 "Counter": "3", 192 "CounterHTOff": "3", 193 "Data_LA": "1", 194 "Errata": "BDM100, BDM35", 195 "EventCode": "0xcd", 196 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 197 "MSRIndex": "0x3F6", 198 "MSRValue": "0x40", 199 "PEBS": "2", 200 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 201 "SampleAfterValue": "2003", 202 "TakenAlone": "1", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Randomly selected loads with latency value being above 8", 207 "Counter": "3", 208 "CounterHTOff": "3", 209 "Data_LA": "1", 210 "Errata": "BDM100, BDM35", 211 "EventCode": "0xcd", 212 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 213 "MSRIndex": "0x3F6", 214 "MSRValue": "0x8", 215 "PEBS": "2", 216 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 217 "SampleAfterValue": "50021", 218 "TakenAlone": "1", 219 "UMask": "0x1" 220 }, 221 { 222 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 223 "Counter": "0,1,2,3", 224 "CounterHTOff": "0,1,2,3,4,5,6,7", 225 "EventCode": "0x05", 226 "EventName": "MISALIGN_MEM_REF.LOADS", 227 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 228 "SampleAfterValue": "2000003", 229 "UMask": "0x1" 230 }, 231 { 232 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 233 "Counter": "0,1,2,3", 234 "CounterHTOff": "0,1,2,3,4,5,6,7", 235 "EventCode": "0x05", 236 "EventName": "MISALIGN_MEM_REF.STORES", 237 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 238 "SampleAfterValue": "2000003", 239 "UMask": "0x2" 240 }, 241 { 242 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 243 "Counter": "0,1,2,3", 244 "CounterHTOff": "0,1,2,3", 245 "EventCode": "0xB7, 0xBB", 246 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 247 "MSRIndex": "0x1a6,0x1a7", 248 "MSRValue": "0x3FBFC00244", 249 "Offcore": "1", 250 "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3", 258 "EventCode": "0xB7, 0xBB", 259 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", 260 "MSRIndex": "0x1a6,0x1a7", 261 "MSRValue": "0x0604000244", 262 "Offcore": "1", 263 "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 264 "SampleAfterValue": "100003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 269 "Counter": "0,1,2,3", 270 "CounterHTOff": "0,1,2,3", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x3FBFC00091", 275 "Offcore": "1", 276 "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", 277 "SampleAfterValue": "100003", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 282 "Counter": "0,1,2,3", 283 "CounterHTOff": "0,1,2,3", 284 "EventCode": "0xB7, 0xBB", 285 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", 286 "MSRIndex": "0x1a6,0x1a7", 287 "MSRValue": "0x0604000091", 288 "Offcore": "1", 289 "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 290 "SampleAfterValue": "100003", 291 "UMask": "0x1" 292 }, 293 { 294 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 295 "Counter": "0,1,2,3", 296 "CounterHTOff": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x063BC00091", 301 "Offcore": "1", 302 "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 303 "SampleAfterValue": "100003", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 308 "Counter": "0,1,2,3", 309 "CounterHTOff": "0,1,2,3", 310 "EventCode": "0xB7, 0xBB", 311 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", 312 "MSRIndex": "0x1a6,0x1a7", 313 "MSRValue": "0x103FC00091", 314 "Offcore": "1", 315 "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 316 "SampleAfterValue": "100003", 317 "UMask": "0x1" 318 }, 319 { 320 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3", 323 "EventCode": "0xB7, 0xBB", 324 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x087FC00091", 327 "Offcore": "1", 328 "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 329 "SampleAfterValue": "100003", 330 "UMask": "0x1" 331 }, 332 { 333 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 334 "Counter": "0,1,2,3", 335 "CounterHTOff": "0,1,2,3", 336 "EventCode": "0xB7, 0xBB", 337 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", 338 "MSRIndex": "0x1a6,0x1a7", 339 "MSRValue": "0x3FBFC007F7", 340 "Offcore": "1", 341 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 342 "SampleAfterValue": "100003", 343 "UMask": "0x1" 344 }, 345 { 346 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram", 347 "Counter": "0,1,2,3", 348 "CounterHTOff": "0,1,2,3", 349 "EventCode": "0xB7, 0xBB", 350 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", 351 "MSRIndex": "0x1a6,0x1a7", 352 "MSRValue": "0x06040007F7", 353 "Offcore": "1", 354 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram", 355 "SampleAfterValue": "100003", 356 "UMask": "0x1" 357 }, 358 { 359 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 360 "Counter": "0,1,2,3", 361 "CounterHTOff": "0,1,2,3", 362 "EventCode": "0xB7, 0xBB", 363 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", 364 "MSRIndex": "0x1a6,0x1a7", 365 "MSRValue": "0x063BC007F7", 366 "Offcore": "1", 367 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 368 "SampleAfterValue": "100003", 369 "UMask": "0x1" 370 }, 371 { 372 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 373 "Counter": "0,1,2,3", 374 "CounterHTOff": "0,1,2,3", 375 "EventCode": "0xB7, 0xBB", 376 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", 377 "MSRIndex": "0x1a6,0x1a7", 378 "MSRValue": "0x103FC007F7", 379 "Offcore": "1", 380 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 386 "Counter": "0,1,2,3", 387 "CounterHTOff": "0,1,2,3", 388 "EventCode": "0xB7, 0xBB", 389 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", 390 "MSRIndex": "0x1a6,0x1a7", 391 "MSRValue": "0x087FC007F7", 392 "Offcore": "1", 393 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 394 "SampleAfterValue": "100003", 395 "UMask": "0x1" 396 }, 397 { 398 "BriefDescription": "Counts all requests miss in the L3", 399 "Counter": "0,1,2,3", 400 "CounterHTOff": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x3FBFC08FFF", 405 "Offcore": "1", 406 "PublicDescription": "Counts all requests miss in the L3", 407 "SampleAfterValue": "100003", 408 "UMask": "0x1" 409 }, 410 { 411 "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", 412 "Counter": "0,1,2,3", 413 "CounterHTOff": "0,1,2,3", 414 "EventCode": "0xB7, 0xBB", 415 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", 416 "MSRIndex": "0x1a6,0x1a7", 417 "MSRValue": "0x3FBFC00122", 418 "Offcore": "1", 419 "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", 420 "SampleAfterValue": "100003", 421 "UMask": "0x1" 422 }, 423 { 424 "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 425 "Counter": "0,1,2,3", 426 "CounterHTOff": "0,1,2,3", 427 "EventCode": "0xB7, 0xBB", 428 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", 429 "MSRIndex": "0x1a6,0x1a7", 430 "MSRValue": "0x0604000122", 431 "Offcore": "1", 432 "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 433 "SampleAfterValue": "100003", 434 "UMask": "0x1" 435 }, 436 { 437 "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", 438 "Counter": "0,1,2,3", 439 "CounterHTOff": "0,1,2,3", 440 "EventCode": "0xB7, 0xBB", 441 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", 442 "MSRIndex": "0x1a6,0x1a7", 443 "MSRValue": "0x3FBFC00002", 444 "Offcore": "1", 445 "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", 446 "SampleAfterValue": "100003", 447 "UMask": "0x1" 448 }, 449 { 450 "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 451 "Counter": "0,1,2,3", 452 "CounterHTOff": "0,1,2,3", 453 "EventCode": "0xB7, 0xBB", 454 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", 455 "MSRIndex": "0x1a6,0x1a7", 456 "MSRValue": "0x103FC00002", 457 "Offcore": "1", 458 "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 459 "SampleAfterValue": "100003", 460 "UMask": "0x1" 461 }, 462 { 463 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 464 "Counter": "0,1,2,3", 465 "CounterHTOff": "0,1,2,3", 466 "EventCode": "0xB7, 0xBB", 467 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 468 "MSRIndex": "0x1a6,0x1a7", 469 "MSRValue": "0x3FBFC00200", 470 "Offcore": "1", 471 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 472 "SampleAfterValue": "100003", 473 "UMask": "0x1" 474 }, 475 { 476 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 477 "Counter": "0,1,2,3", 478 "CounterHTOff": "0,1,2,3", 479 "EventCode": "0xB7, 0xBB", 480 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", 481 "MSRIndex": "0x1a6,0x1a7", 482 "MSRValue": "0x3FBFC00100", 483 "Offcore": "1", 484 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 485 "SampleAfterValue": "100003", 486 "UMask": "0x1" 487 }, 488 { 489 "BriefDescription": "Number of times RTM abort was triggered", 490 "Counter": "0,1,2,3", 491 "CounterHTOff": "0,1,2,3", 492 "EventCode": "0xc9", 493 "EventName": "RTM_RETIRED.ABORTED", 494 "PEBS": "1", 495 "PublicDescription": "Number of times RTM abort was triggered .", 496 "SampleAfterValue": "2000003", 497 "UMask": "0x4" 498 }, 499 { 500 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 501 "Counter": "0,1,2,3", 502 "CounterHTOff": "0,1,2,3", 503 "EventCode": "0xc9", 504 "EventName": "RTM_RETIRED.ABORTED_MISC1", 505 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 506 "SampleAfterValue": "2000003", 507 "UMask": "0x8" 508 }, 509 { 510 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 511 "Counter": "0,1,2,3", 512 "CounterHTOff": "0,1,2,3", 513 "EventCode": "0xc9", 514 "EventName": "RTM_RETIRED.ABORTED_MISC2", 515 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 516 "SampleAfterValue": "2000003", 517 "UMask": "0x10" 518 }, 519 { 520 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 521 "Counter": "0,1,2,3", 522 "CounterHTOff": "0,1,2,3", 523 "EventCode": "0xc9", 524 "EventName": "RTM_RETIRED.ABORTED_MISC3", 525 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 526 "SampleAfterValue": "2000003", 527 "UMask": "0x20" 528 }, 529 { 530 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 531 "Counter": "0,1,2,3", 532 "CounterHTOff": "0,1,2,3", 533 "EventCode": "0xc9", 534 "EventName": "RTM_RETIRED.ABORTED_MISC4", 535 "PublicDescription": "Number of times a RTM caused a fault.", 536 "SampleAfterValue": "2000003", 537 "UMask": "0x40" 538 }, 539 { 540 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 541 "Counter": "0,1,2,3", 542 "CounterHTOff": "0,1,2,3", 543 "EventCode": "0xc9", 544 "EventName": "RTM_RETIRED.ABORTED_MISC5", 545 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 546 "SampleAfterValue": "2000003", 547 "UMask": "0x80" 548 }, 549 { 550 "BriefDescription": "Number of times RTM commit succeeded", 551 "Counter": "0,1,2,3", 552 "CounterHTOff": "0,1,2,3", 553 "EventCode": "0xc9", 554 "EventName": "RTM_RETIRED.COMMIT", 555 "PublicDescription": "Number of times RTM commit succeeded.", 556 "SampleAfterValue": "2000003", 557 "UMask": "0x2" 558 }, 559 { 560 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 561 "Counter": "0,1,2,3", 562 "CounterHTOff": "0,1,2,3", 563 "EventCode": "0xc9", 564 "EventName": "RTM_RETIRED.START", 565 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 566 "SampleAfterValue": "2000003", 567 "UMask": "0x1" 568 }, 569 { 570 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 571 "Counter": "0,1,2,3", 572 "CounterHTOff": "0,1,2,3,4,5,6,7", 573 "EventCode": "0x5d", 574 "EventName": "TX_EXEC.MISC1", 575 "SampleAfterValue": "2000003", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 580 "Counter": "0,1,2,3", 581 "CounterHTOff": "0,1,2,3,4,5,6,7", 582 "EventCode": "0x5d", 583 "EventName": "TX_EXEC.MISC2", 584 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 585 "SampleAfterValue": "2000003", 586 "UMask": "0x2" 587 }, 588 { 589 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 590 "Counter": "0,1,2,3", 591 "CounterHTOff": "0,1,2,3,4,5,6,7", 592 "EventCode": "0x5d", 593 "EventName": "TX_EXEC.MISC3", 594 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 595 "SampleAfterValue": "2000003", 596 "UMask": "0x4" 597 }, 598 { 599 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 600 "Counter": "0,1,2,3", 601 "CounterHTOff": "0,1,2,3,4,5,6,7", 602 "EventCode": "0x5d", 603 "EventName": "TX_EXEC.MISC4", 604 "PublicDescription": "RTM region detected inside HLE.", 605 "SampleAfterValue": "2000003", 606 "UMask": "0x8" 607 }, 608 { 609 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 610 "Counter": "0,1,2,3", 611 "CounterHTOff": "0,1,2,3,4,5,6,7", 612 "EventCode": "0x5d", 613 "EventName": "TX_EXEC.MISC5", 614 "SampleAfterValue": "2000003", 615 "UMask": "0x10" 616 }, 617 { 618 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 619 "Counter": "0,1,2,3", 620 "CounterHTOff": "0,1,2,3,4,5,6,7", 621 "EventCode": "0x54", 622 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 623 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 624 "SampleAfterValue": "2000003", 625 "UMask": "0x2" 626 }, 627 { 628 "BriefDescription": "Number of times a TSX line had a cache conflict", 629 "Counter": "0,1,2,3", 630 "CounterHTOff": "0,1,2,3,4,5,6,7", 631 "EventCode": "0x54", 632 "EventName": "TX_MEM.ABORT_CONFLICT", 633 "PublicDescription": "Number of times a TSX line had a cache conflict.", 634 "SampleAfterValue": "2000003", 635 "UMask": "0x1" 636 }, 637 { 638 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 639 "Counter": "0,1,2,3", 640 "CounterHTOff": "0,1,2,3,4,5,6,7", 641 "EventCode": "0x54", 642 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 643 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 644 "SampleAfterValue": "2000003", 645 "UMask": "0x10" 646 }, 647 { 648 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 649 "Counter": "0,1,2,3", 650 "CounterHTOff": "0,1,2,3,4,5,6,7", 651 "EventCode": "0x54", 652 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 653 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 654 "SampleAfterValue": "2000003", 655 "UMask": "0x8" 656 }, 657 { 658 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 659 "Counter": "0,1,2,3", 660 "CounterHTOff": "0,1,2,3,4,5,6,7", 661 "EventCode": "0x54", 662 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 663 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 664 "SampleAfterValue": "2000003", 665 "UMask": "0x20" 666 }, 667 { 668 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 669 "Counter": "0,1,2,3", 670 "CounterHTOff": "0,1,2,3,4,5,6,7", 671 "EventCode": "0x54", 672 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 673 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 674 "SampleAfterValue": "2000003", 675 "UMask": "0x4" 676 }, 677 { 678 "BriefDescription": "Number of times we could not allocate Lock Buffer", 679 "Counter": "0,1,2,3", 680 "CounterHTOff": "0,1,2,3,4,5,6,7", 681 "EventCode": "0x54", 682 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 683 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 684 "SampleAfterValue": "2000003", 685 "UMask": "0x40" 686 } 687]