1*959826caSMatt Macy[ 2*959826caSMatt Macy { 3*959826caSMatt Macy "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 4*959826caSMatt Macy "EventCode": "0x5C", 5*959826caSMatt Macy "Counter": "0,1,2,3", 6*959826caSMatt Macy "UMask": "0x1", 7*959826caSMatt Macy "EventName": "CPL_CYCLES.RING0", 8*959826caSMatt Macy "SampleAfterValue": "2000003", 9*959826caSMatt Macy "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 10*959826caSMatt Macy "CounterHTOff": "0,1,2,3,4,5,6,7" 11*959826caSMatt Macy }, 12*959826caSMatt Macy { 13*959826caSMatt Macy "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 14*959826caSMatt Macy "EventCode": "0x5C", 15*959826caSMatt Macy "Counter": "0,1,2,3", 16*959826caSMatt Macy "UMask": "0x1", 17*959826caSMatt Macy "EdgeDetect": "1", 18*959826caSMatt Macy "EventName": "CPL_CYCLES.RING0_TRANS", 19*959826caSMatt Macy "SampleAfterValue": "100007", 20*959826caSMatt Macy "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 21*959826caSMatt Macy "CounterMask": "1", 22*959826caSMatt Macy "CounterHTOff": "0,1,2,3,4,5,6,7" 23*959826caSMatt Macy }, 24*959826caSMatt Macy { 25*959826caSMatt Macy "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 26*959826caSMatt Macy "EventCode": "0x5C", 27*959826caSMatt Macy "Counter": "0,1,2,3", 28*959826caSMatt Macy "UMask": "0x2", 29*959826caSMatt Macy "EventName": "CPL_CYCLES.RING123", 30*959826caSMatt Macy "SampleAfterValue": "2000003", 31*959826caSMatt Macy "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 32*959826caSMatt Macy "CounterHTOff": "0,1,2,3,4,5,6,7" 33*959826caSMatt Macy }, 34*959826caSMatt Macy { 35*959826caSMatt Macy "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 36*959826caSMatt Macy "EventCode": "0x63", 37*959826caSMatt Macy "Counter": "0,1,2,3", 38*959826caSMatt Macy "UMask": "0x1", 39*959826caSMatt Macy "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40*959826caSMatt Macy "SampleAfterValue": "2000003", 41*959826caSMatt Macy "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 42*959826caSMatt Macy "CounterHTOff": "0,1,2,3,4,5,6,7" 43*959826caSMatt Macy } 44*959826caSMatt Macy]