1959826caSMatt Macy[ 2959826caSMatt Macy { 3959826caSMatt Macy "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*18054d02SAlexander Motin "Counter": "0,1,2,3", 5*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 6*18054d02SAlexander Motin "EventCode": "0x5C", 7*18054d02SAlexander Motin "EventName": "CPL_CYCLES.RING0", 8*18054d02SAlexander Motin "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 9*18054d02SAlexander Motin "SampleAfterValue": "2000003", 10*18054d02SAlexander Motin "UMask": "0x1" 11959826caSMatt Macy }, 12959826caSMatt Macy { 13959826caSMatt Macy "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 14*18054d02SAlexander Motin "Counter": "0,1,2,3", 15*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 16959826caSMatt Macy "CounterMask": "1", 17*18054d02SAlexander Motin "EdgeDetect": "1", 18959826caSMatt Macy "EventCode": "0x5C", 19*18054d02SAlexander Motin "EventName": "CPL_CYCLES.RING0_TRANS", 20*18054d02SAlexander Motin "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 21*18054d02SAlexander Motin "SampleAfterValue": "100007", 22*18054d02SAlexander Motin "UMask": "0x1" 23959826caSMatt Macy }, 24959826caSMatt Macy { 25*18054d02SAlexander Motin "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 26959826caSMatt Macy "Counter": "0,1,2,3", 27*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 28*18054d02SAlexander Motin "EventCode": "0x5C", 29*18054d02SAlexander Motin "EventName": "CPL_CYCLES.RING123", 30*18054d02SAlexander Motin "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 31959826caSMatt Macy "SampleAfterValue": "2000003", 32*18054d02SAlexander Motin "UMask": "0x2" 33*18054d02SAlexander Motin }, 34*18054d02SAlexander Motin { 35959826caSMatt Macy "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 36*18054d02SAlexander Motin "Counter": "0,1,2,3", 37*18054d02SAlexander Motin "CounterHTOff": "0,1,2,3,4,5,6,7", 38*18054d02SAlexander Motin "EventCode": "0x63", 39*18054d02SAlexander Motin "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40*18054d02SAlexander Motin "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 41*18054d02SAlexander Motin "SampleAfterValue": "2000003", 42*18054d02SAlexander Motin "UMask": "0x1" 43959826caSMatt Macy } 44959826caSMatt Macy]