1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xc8", 7 "EventName": "HLE_RETIRED.ABORTED", 8 "PEBS": "1", 9 "PublicDescription": "Number of times HLE abort was triggered.", 10 "SampleAfterValue": "2000003", 11 "UMask": "0x4" 12 }, 13 { 14 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 15 "Counter": "0,1,2,3", 16 "CounterHTOff": "0,1,2,3,4,5,6,7", 17 "EventCode": "0xc8", 18 "EventName": "HLE_RETIRED.ABORTED_MISC1", 19 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 20 "SampleAfterValue": "2000003", 21 "UMask": "0x8" 22 }, 23 { 24 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 25 "Counter": "0,1,2,3", 26 "CounterHTOff": "0,1,2,3,4,5,6,7", 27 "EventCode": "0xc8", 28 "EventName": "HLE_RETIRED.ABORTED_MISC2", 29 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x10" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC3", 39 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x20" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 45 "Counter": "0,1,2,3", 46 "CounterHTOff": "0,1,2,3,4,5,6,7", 47 "EventCode": "0xc8", 48 "EventName": "HLE_RETIRED.ABORTED_MISC4", 49 "PublicDescription": "Number of times HLE caused a fault.", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x40" 52 }, 53 { 54 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 55 "Counter": "0,1,2,3", 56 "CounterHTOff": "0,1,2,3,4,5,6,7", 57 "EventCode": "0xc8", 58 "EventName": "HLE_RETIRED.ABORTED_MISC5", 59 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x80" 62 }, 63 { 64 "BriefDescription": "Number of times HLE commit succeeded", 65 "Counter": "0,1,2,3", 66 "CounterHTOff": "0,1,2,3,4,5,6,7", 67 "EventCode": "0xc8", 68 "EventName": "HLE_RETIRED.COMMIT", 69 "PublicDescription": "Number of times HLE commit succeeded.", 70 "SampleAfterValue": "2000003", 71 "UMask": "0x2" 72 }, 73 { 74 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 75 "Counter": "0,1,2,3", 76 "CounterHTOff": "0,1,2,3,4,5,6,7", 77 "EventCode": "0xc8", 78 "EventName": "HLE_RETIRED.START", 79 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x1" 82 }, 83 { 84 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 85 "Counter": "0,1,2,3", 86 "CounterHTOff": "0,1,2,3,4,5,6,7", 87 "EventCode": "0xC3", 88 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 89 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x2" 92 }, 93 { 94 "BriefDescription": "Randomly selected loads with latency value being above 128", 95 "Counter": "3", 96 "CounterHTOff": "3", 97 "Data_LA": "1", 98 "Errata": "BDM100, BDM35", 99 "EventCode": "0xcd", 100 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 101 "MSRIndex": "0x3F6", 102 "MSRValue": "0x80", 103 "PEBS": "2", 104 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 105 "SampleAfterValue": "1009", 106 "TakenAlone": "1", 107 "UMask": "0x1" 108 }, 109 { 110 "BriefDescription": "Randomly selected loads with latency value being above 16", 111 "Counter": "3", 112 "CounterHTOff": "3", 113 "Data_LA": "1", 114 "Errata": "BDM100, BDM35", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x10", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 121 "SampleAfterValue": "20011", 122 "TakenAlone": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Randomly selected loads with latency value being above 256", 127 "Counter": "3", 128 "CounterHTOff": "3", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x100", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 137 "SampleAfterValue": "503", 138 "TakenAlone": "1", 139 "UMask": "0x1" 140 }, 141 { 142 "BriefDescription": "Randomly selected loads with latency value being above 32", 143 "Counter": "3", 144 "CounterHTOff": "3", 145 "Data_LA": "1", 146 "Errata": "BDM100, BDM35", 147 "EventCode": "0xcd", 148 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 149 "MSRIndex": "0x3F6", 150 "MSRValue": "0x20", 151 "PEBS": "2", 152 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 153 "SampleAfterValue": "100007", 154 "TakenAlone": "1", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Randomly selected loads with latency value being above 4", 159 "Counter": "3", 160 "CounterHTOff": "3", 161 "Data_LA": "1", 162 "Errata": "BDM100, BDM35", 163 "EventCode": "0xcd", 164 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 165 "MSRIndex": "0x3F6", 166 "MSRValue": "0x4", 167 "PEBS": "2", 168 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 169 "SampleAfterValue": "100003", 170 "TakenAlone": "1", 171 "UMask": "0x1" 172 }, 173 { 174 "BriefDescription": "Randomly selected loads with latency value being above 512", 175 "Counter": "3", 176 "CounterHTOff": "3", 177 "Data_LA": "1", 178 "Errata": "BDM100, BDM35", 179 "EventCode": "0xcd", 180 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 181 "MSRIndex": "0x3F6", 182 "MSRValue": "0x200", 183 "PEBS": "2", 184 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 185 "SampleAfterValue": "101", 186 "TakenAlone": "1", 187 "UMask": "0x1" 188 }, 189 { 190 "BriefDescription": "Randomly selected loads with latency value being above 64", 191 "Counter": "3", 192 "CounterHTOff": "3", 193 "Data_LA": "1", 194 "Errata": "BDM100, BDM35", 195 "EventCode": "0xcd", 196 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 197 "MSRIndex": "0x3F6", 198 "MSRValue": "0x40", 199 "PEBS": "2", 200 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 201 "SampleAfterValue": "2003", 202 "TakenAlone": "1", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Randomly selected loads with latency value being above 8", 207 "Counter": "3", 208 "CounterHTOff": "3", 209 "Data_LA": "1", 210 "Errata": "BDM100, BDM35", 211 "EventCode": "0xcd", 212 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 213 "MSRIndex": "0x3F6", 214 "MSRValue": "0x8", 215 "PEBS": "2", 216 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 217 "SampleAfterValue": "50021", 218 "TakenAlone": "1", 219 "UMask": "0x1" 220 }, 221 { 222 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 223 "Counter": "0,1,2,3", 224 "CounterHTOff": "0,1,2,3,4,5,6,7", 225 "EventCode": "0x05", 226 "EventName": "MISALIGN_MEM_REF.LOADS", 227 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 228 "SampleAfterValue": "2000003", 229 "UMask": "0x1" 230 }, 231 { 232 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 233 "Counter": "0,1,2,3", 234 "CounterHTOff": "0,1,2,3,4,5,6,7", 235 "EventCode": "0x05", 236 "EventName": "MISALIGN_MEM_REF.STORES", 237 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 238 "SampleAfterValue": "2000003", 239 "UMask": "0x2" 240 }, 241 { 242 "BriefDescription": "Counts all demand & prefetch data reads", 243 "Counter": "0,1,2,3", 244 "CounterHTOff": "0,1,2,3", 245 "EventCode": "0xB7, 0xBB", 246 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 247 "MSRIndex": "0x1a6,0x1a7", 248 "MSRValue": "0x20003C0091", 249 "Offcore": "1", 250 "PublicDescription": "Counts all demand & prefetch data reads", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Counts all demand & prefetch data reads", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3", 258 "EventCode": "0xB7, 0xBB", 259 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 260 "MSRIndex": "0x1a6,0x1a7", 261 "MSRValue": "0x043C000091", 262 "Offcore": "1", 263 "PublicDescription": "Counts all demand & prefetch data reads", 264 "SampleAfterValue": "100003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "Counts all demand & prefetch data reads", 269 "Counter": "0,1,2,3", 270 "CounterHTOff": "0,1,2,3", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x023C000091", 275 "Offcore": "1", 276 "PublicDescription": "Counts all demand & prefetch data reads", 277 "SampleAfterValue": "100003", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "Counts all demand & prefetch data reads", 282 "Counter": "0,1,2,3", 283 "CounterHTOff": "0,1,2,3", 284 "EventCode": "0xB7, 0xBB", 285 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 286 "MSRIndex": "0x1a6,0x1a7", 287 "MSRValue": "0x00BC000091", 288 "Offcore": "1", 289 "PublicDescription": "Counts all demand & prefetch data reads", 290 "SampleAfterValue": "100003", 291 "UMask": "0x1" 292 }, 293 { 294 "BriefDescription": "Counts all demand & prefetch data reads", 295 "Counter": "0,1,2,3", 296 "CounterHTOff": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x013C000091", 301 "Offcore": "1", 302 "PublicDescription": "Counts all demand & prefetch data reads", 303 "SampleAfterValue": "100003", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "Counts all demand & prefetch data reads", 308 "Counter": "0,1,2,3", 309 "CounterHTOff": "0,1,2,3", 310 "EventCode": "0xB7, 0xBB", 311 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 312 "MSRIndex": "0x1a6,0x1a7", 313 "MSRValue": "0x3F84000091", 314 "Offcore": "1", 315 "PublicDescription": "Counts all demand & prefetch data reads", 316 "SampleAfterValue": "100003", 317 "UMask": "0x1" 318 }, 319 { 320 "BriefDescription": "Counts all demand & prefetch data reads", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3", 323 "EventCode": "0xB7, 0xBB", 324 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x1004000091", 327 "Offcore": "1", 328 "PublicDescription": "Counts all demand & prefetch data reads", 329 "SampleAfterValue": "100003", 330 "UMask": "0x1" 331 }, 332 { 333 "BriefDescription": "Counts all demand & prefetch data reads", 334 "Counter": "0,1,2,3", 335 "CounterHTOff": "0,1,2,3", 336 "EventCode": "0xB7, 0xBB", 337 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 338 "MSRIndex": "0x1a6,0x1a7", 339 "MSRValue": "0x0404000091", 340 "Offcore": "1", 341 "PublicDescription": "Counts all demand & prefetch data reads", 342 "SampleAfterValue": "100003", 343 "UMask": "0x1" 344 }, 345 { 346 "BriefDescription": "Counts all demand & prefetch data reads", 347 "Counter": "0,1,2,3", 348 "CounterHTOff": "0,1,2,3", 349 "EventCode": "0xB7, 0xBB", 350 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 351 "MSRIndex": "0x1a6,0x1a7", 352 "MSRValue": "0x0204000091", 353 "Offcore": "1", 354 "PublicDescription": "Counts all demand & prefetch data reads", 355 "SampleAfterValue": "100003", 356 "UMask": "0x1" 357 }, 358 { 359 "BriefDescription": "Counts all demand & prefetch data reads", 360 "Counter": "0,1,2,3", 361 "CounterHTOff": "0,1,2,3", 362 "EventCode": "0xB7, 0xBB", 363 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 364 "MSRIndex": "0x1a6,0x1a7", 365 "MSRValue": "0x0084000091", 366 "Offcore": "1", 367 "PublicDescription": "Counts all demand & prefetch data reads", 368 "SampleAfterValue": "100003", 369 "UMask": "0x1" 370 }, 371 { 372 "BriefDescription": "Counts all demand & prefetch data reads", 373 "Counter": "0,1,2,3", 374 "CounterHTOff": "0,1,2,3", 375 "EventCode": "0xB7, 0xBB", 376 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 377 "MSRIndex": "0x1a6,0x1a7", 378 "MSRValue": "0x2004000091", 379 "Offcore": "1", 380 "PublicDescription": "Counts all demand & prefetch data reads", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts all demand & prefetch data reads", 386 "Counter": "0,1,2,3", 387 "CounterHTOff": "0,1,2,3", 388 "EventCode": "0xB7, 0xBB", 389 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 390 "MSRIndex": "0x1a6,0x1a7", 391 "MSRValue": "0x0104000091", 392 "Offcore": "1", 393 "PublicDescription": "Counts all demand & prefetch data reads", 394 "SampleAfterValue": "100003", 395 "UMask": "0x1" 396 }, 397 { 398 "BriefDescription": "Counts all demand & prefetch data reads", 399 "Counter": "0,1,2,3", 400 "CounterHTOff": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x2000020091", 405 "Offcore": "1", 406 "PublicDescription": "Counts all demand & prefetch data reads", 407 "SampleAfterValue": "100003", 408 "UMask": "0x1" 409 }, 410 { 411 "BriefDescription": "Counts all prefetch code reads", 412 "Counter": "0,1,2,3", 413 "CounterHTOff": "0,1,2,3", 414 "EventCode": "0xB7, 0xBB", 415 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 416 "MSRIndex": "0x1a6,0x1a7", 417 "MSRValue": "0x20003C0240", 418 "Offcore": "1", 419 "PublicDescription": "Counts all prefetch code reads", 420 "SampleAfterValue": "100003", 421 "UMask": "0x1" 422 }, 423 { 424 "BriefDescription": "Counts all prefetch code reads", 425 "Counter": "0,1,2,3", 426 "CounterHTOff": "0,1,2,3", 427 "EventCode": "0xB7, 0xBB", 428 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 429 "MSRIndex": "0x1a6,0x1a7", 430 "MSRValue": "0x043C000240", 431 "Offcore": "1", 432 "PublicDescription": "Counts all prefetch code reads", 433 "SampleAfterValue": "100003", 434 "UMask": "0x1" 435 }, 436 { 437 "BriefDescription": "Counts all prefetch code reads", 438 "Counter": "0,1,2,3", 439 "CounterHTOff": "0,1,2,3", 440 "EventCode": "0xB7, 0xBB", 441 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", 442 "MSRIndex": "0x1a6,0x1a7", 443 "MSRValue": "0x023C000240", 444 "Offcore": "1", 445 "PublicDescription": "Counts all prefetch code reads", 446 "SampleAfterValue": "100003", 447 "UMask": "0x1" 448 }, 449 { 450 "BriefDescription": "Counts all prefetch code reads", 451 "Counter": "0,1,2,3", 452 "CounterHTOff": "0,1,2,3", 453 "EventCode": "0xB7, 0xBB", 454 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", 455 "MSRIndex": "0x1a6,0x1a7", 456 "MSRValue": "0x00BC000240", 457 "Offcore": "1", 458 "PublicDescription": "Counts all prefetch code reads", 459 "SampleAfterValue": "100003", 460 "UMask": "0x1" 461 }, 462 { 463 "BriefDescription": "Counts all prefetch code reads", 464 "Counter": "0,1,2,3", 465 "CounterHTOff": "0,1,2,3", 466 "EventCode": "0xB7, 0xBB", 467 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 468 "MSRIndex": "0x1a6,0x1a7", 469 "MSRValue": "0x013C000240", 470 "Offcore": "1", 471 "PublicDescription": "Counts all prefetch code reads", 472 "SampleAfterValue": "100003", 473 "UMask": "0x1" 474 }, 475 { 476 "BriefDescription": "Counts all prefetch code reads", 477 "Counter": "0,1,2,3", 478 "CounterHTOff": "0,1,2,3", 479 "EventCode": "0xB7, 0xBB", 480 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 481 "MSRIndex": "0x1a6,0x1a7", 482 "MSRValue": "0x3F84000240", 483 "Offcore": "1", 484 "PublicDescription": "Counts all prefetch code reads", 485 "SampleAfterValue": "100003", 486 "UMask": "0x1" 487 }, 488 { 489 "BriefDescription": "Counts all prefetch code reads", 490 "Counter": "0,1,2,3", 491 "CounterHTOff": "0,1,2,3", 492 "EventCode": "0xB7, 0xBB", 493 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 494 "MSRIndex": "0x1a6,0x1a7", 495 "MSRValue": "0x1004000240", 496 "Offcore": "1", 497 "PublicDescription": "Counts all prefetch code reads", 498 "SampleAfterValue": "100003", 499 "UMask": "0x1" 500 }, 501 { 502 "BriefDescription": "Counts all prefetch code reads", 503 "Counter": "0,1,2,3", 504 "CounterHTOff": "0,1,2,3", 505 "EventCode": "0xB7, 0xBB", 506 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 507 "MSRIndex": "0x1a6,0x1a7", 508 "MSRValue": "0x0404000240", 509 "Offcore": "1", 510 "PublicDescription": "Counts all prefetch code reads", 511 "SampleAfterValue": "100003", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "Counts all prefetch code reads", 516 "Counter": "0,1,2,3", 517 "CounterHTOff": "0,1,2,3", 518 "EventCode": "0xB7, 0xBB", 519 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 520 "MSRIndex": "0x1a6,0x1a7", 521 "MSRValue": "0x0204000240", 522 "Offcore": "1", 523 "PublicDescription": "Counts all prefetch code reads", 524 "SampleAfterValue": "100003", 525 "UMask": "0x1" 526 }, 527 { 528 "BriefDescription": "Counts all prefetch code reads", 529 "Counter": "0,1,2,3", 530 "CounterHTOff": "0,1,2,3", 531 "EventCode": "0xB7, 0xBB", 532 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 533 "MSRIndex": "0x1a6,0x1a7", 534 "MSRValue": "0x0084000240", 535 "Offcore": "1", 536 "PublicDescription": "Counts all prefetch code reads", 537 "SampleAfterValue": "100003", 538 "UMask": "0x1" 539 }, 540 { 541 "BriefDescription": "Counts all prefetch code reads", 542 "Counter": "0,1,2,3", 543 "CounterHTOff": "0,1,2,3", 544 "EventCode": "0xB7, 0xBB", 545 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 546 "MSRIndex": "0x1a6,0x1a7", 547 "MSRValue": "0x2004000240", 548 "Offcore": "1", 549 "PublicDescription": "Counts all prefetch code reads", 550 "SampleAfterValue": "100003", 551 "UMask": "0x1" 552 }, 553 { 554 "BriefDescription": "Counts all prefetch code reads", 555 "Counter": "0,1,2,3", 556 "CounterHTOff": "0,1,2,3", 557 "EventCode": "0xB7, 0xBB", 558 "EventName": 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"Offcore": "1", 588 "PublicDescription": "Counts all prefetch data reads", 589 "SampleAfterValue": "100003", 590 "UMask": "0x1" 591 }, 592 { 593 "BriefDescription": "Counts all prefetch data reads", 594 "Counter": "0,1,2,3", 595 "CounterHTOff": "0,1,2,3", 596 "EventCode": "0xB7, 0xBB", 597 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 598 "MSRIndex": "0x1a6,0x1a7", 599 "MSRValue": "0x043C000090", 600 "Offcore": "1", 601 "PublicDescription": "Counts all prefetch data reads", 602 "SampleAfterValue": "100003", 603 "UMask": "0x1" 604 }, 605 { 606 "BriefDescription": "Counts all prefetch data reads", 607 "Counter": "0,1,2,3", 608 "CounterHTOff": "0,1,2,3", 609 "EventCode": "0xB7, 0xBB", 610 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 611 "MSRIndex": "0x1a6,0x1a7", 612 "MSRValue": "0x023C000090", 613 "Offcore": "1", 614 "PublicDescription": "Counts all prefetch data reads", 615 "SampleAfterValue": "100003", 616 "UMask": "0x1" 617 }, 618 { 619 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code reads", 2513 "SampleAfterValue": "100003", 2514 "UMask": "0x1" 2515 }, 2516 { 2517 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2518 "Counter": "0,1,2,3", 2519 "CounterHTOff": "0,1,2,3", 2520 "EventCode": "0xB7, 0xBB", 2521 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 2522 "MSRIndex": "0x1a6,0x1a7", 2523 "MSRValue": "0x20003C0080", 2524 "Offcore": "1", 2525 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2526 "SampleAfterValue": "100003", 2527 "UMask": "0x1" 2528 }, 2529 { 2530 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2531 "Counter": "0,1,2,3", 2532 "CounterHTOff": "0,1,2,3", 2533 "EventCode": "0xB7, 0xBB", 2534 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 2535 "MSRIndex": "0x1a6,0x1a7", 2536 "MSRValue": "0x043C000080", 2537 "Offcore": "1", 2538 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2539 "SampleAfterValue": "100003", 2540 "UMask": "0x1" 2541 }, 2542 { 2543 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2544 "Counter": "0,1,2,3", 2545 "CounterHTOff": "0,1,2,3", 2546 "EventCode": "0xB7, 0xBB", 2547 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 2548 "MSRIndex": "0x1a6,0x1a7", 2549 "MSRValue": "0x023C000080", 2550 "Offcore": "1", 2551 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2552 "SampleAfterValue": "100003", 2553 "UMask": "0x1" 2554 }, 2555 { 2556 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2557 "Counter": "0,1,2,3", 2558 "CounterHTOff": "0,1,2,3", 2559 "EventCode": "0xB7, 0xBB", 2560 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 2561 "MSRIndex": "0x1a6,0x1a7", 2562 "MSRValue": "0x00BC000080", 2563 "Offcore": "1", 2564 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2565 "SampleAfterValue": "100003", 2566 "UMask": "0x1" 2567 }, 2568 { 2569 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2570 "Counter": "0,1,2,3", 2571 "CounterHTOff": "0,1,2,3", 2572 "EventCode": "0xB7, 0xBB", 2573 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 2574 "MSRIndex": "0x1a6,0x1a7", 2575 "MSRValue": "0x013C000080", 2576 "Offcore": "1", 2577 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2578 "SampleAfterValue": "100003", 2579 "UMask": "0x1" 2580 }, 2581 { 2582 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2583 "Counter": "0,1,2,3", 2584 "CounterHTOff": "0,1,2,3", 2585 "EventCode": "0xB7, 0xBB", 2586 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2587 "MSRIndex": "0x1a6,0x1a7", 2588 "MSRValue": "0x3F84000080", 2589 "Offcore": "1", 2590 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2591 "SampleAfterValue": "100003", 2592 "UMask": "0x1" 2593 }, 2594 { 2595 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2596 "Counter": "0,1,2,3", 2597 "CounterHTOff": "0,1,2,3", 2598 "EventCode": "0xB7, 0xBB", 2599 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 2600 "MSRIndex": "0x1a6,0x1a7", 2601 "MSRValue": "0x1004000080", 2602 "Offcore": "1", 2603 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2604 "SampleAfterValue": "100003", 2605 "UMask": "0x1" 2606 }, 2607 { 2608 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2609 "Counter": "0,1,2,3", 2610 "CounterHTOff": "0,1,2,3", 2611 "EventCode": "0xB7, 0xBB", 2612 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 2613 "MSRIndex": "0x1a6,0x1a7", 2614 "MSRValue": "0x0404000080", 2615 "Offcore": "1", 2616 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2617 "SampleAfterValue": "100003", 2618 "UMask": "0x1" 2619 }, 2620 { 2621 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2622 "Counter": "0,1,2,3", 2623 "CounterHTOff": "0,1,2,3", 2624 "EventCode": "0xB7, 0xBB", 2625 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2626 "MSRIndex": "0x1a6,0x1a7", 2627 "MSRValue": "0x0204000080", 2628 "Offcore": "1", 2629 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2630 "SampleAfterValue": "100003", 2631 "UMask": "0x1" 2632 }, 2633 { 2634 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2635 "Counter": "0,1,2,3", 2636 "CounterHTOff": "0,1,2,3", 2637 "EventCode": "0xB7, 0xBB", 2638 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2639 "MSRIndex": "0x1a6,0x1a7", 2640 "MSRValue": "0x0084000080", 2641 "Offcore": "1", 2642 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2643 "SampleAfterValue": "100003", 2644 "UMask": "0x1" 2645 }, 2646 { 2647 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2648 "Counter": "0,1,2,3", 2649 "CounterHTOff": "0,1,2,3", 2650 "EventCode": "0xB7, 0xBB", 2651 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 2652 "MSRIndex": "0x1a6,0x1a7", 2653 "MSRValue": "0x2004000080", 2654 "Offcore": "1", 2655 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2656 "SampleAfterValue": "100003", 2657 "UMask": "0x1" 2658 }, 2659 { 2660 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2661 "Counter": "0,1,2,3", 2662 "CounterHTOff": "0,1,2,3", 2663 "EventCode": "0xB7, 0xBB", 2664 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 2665 "MSRIndex": "0x1a6,0x1a7", 2666 "MSRValue": "0x0104000080", 2667 "Offcore": "1", 2668 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2669 "SampleAfterValue": "100003", 2670 "UMask": "0x1" 2671 }, 2672 { 2673 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2674 "Counter": "0,1,2,3", 2675 "CounterHTOff": "0,1,2,3", 2676 "EventCode": "0xB7, 0xBB", 2677 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 2678 "MSRIndex": "0x1a6,0x1a7", 2679 "MSRValue": "0x2000020080", 2680 "Offcore": "1", 2681 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2682 "SampleAfterValue": "100003", 2683 "UMask": "0x1" 2684 }, 2685 { 2686 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2687 "Counter": "0,1,2,3", 2688 "CounterHTOff": "0,1,2,3", 2689 "EventCode": "0xB7, 0xBB", 2690 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", 2691 "MSRIndex": "0x1a6,0x1a7", 2692 "MSRValue": "0x20003C0100", 2693 "Offcore": "1", 2694 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2695 "SampleAfterValue": "100003", 2696 "UMask": "0x1" 2697 }, 2698 { 2699 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2700 "Counter": "0,1,2,3", 2701 "CounterHTOff": "0,1,2,3", 2702 "EventCode": "0xB7, 0xBB", 2703 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 2704 "MSRIndex": "0x1a6,0x1a7", 2705 "MSRValue": "0x043C000100", 2706 "Offcore": "1", 2707 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2708 "SampleAfterValue": "100003", 2709 "UMask": "0x1" 2710 }, 2711 { 2712 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2713 "Counter": "0,1,2,3", 2714 "CounterHTOff": "0,1,2,3", 2715 "EventCode": "0xB7, 0xBB", 2716 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", 2717 "MSRIndex": "0x1a6,0x1a7", 2718 "MSRValue": "0x023C000100", 2719 "Offcore": "1", 2720 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2721 "SampleAfterValue": "100003", 2722 "UMask": "0x1" 2723 }, 2724 { 2725 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2726 "Counter": "0,1,2,3", 2727 "CounterHTOff": "0,1,2,3", 2728 "EventCode": "0xB7, 0xBB", 2729 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", 2730 "MSRIndex": "0x1a6,0x1a7", 2731 "MSRValue": "0x00BC000100", 2732 "Offcore": "1", 2733 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2734 "SampleAfterValue": "100003", 2735 "UMask": "0x1" 2736 }, 2737 { 2738 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2739 "Counter": "0,1,2,3", 2740 "CounterHTOff": "0,1,2,3", 2741 "EventCode": "0xB7, 0xBB", 2742 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", 2743 "MSRIndex": "0x1a6,0x1a7", 2744 "MSRValue": "0x013C000100", 2745 "Offcore": "1", 2746 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2747 "SampleAfterValue": "100003", 2748 "UMask": "0x1" 2749 }, 2750 { 2751 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2752 "Counter": "0,1,2,3", 2753 "CounterHTOff": "0,1,2,3", 2754 "EventCode": "0xB7, 0xBB", 2755 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2756 "MSRIndex": "0x1a6,0x1a7", 2757 "MSRValue": "0x3F84000100", 2758 "Offcore": "1", 2759 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2760 "SampleAfterValue": "100003", 2761 "UMask": "0x1" 2762 }, 2763 { 2764 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2765 "Counter": "0,1,2,3", 2766 "CounterHTOff": "0,1,2,3", 2767 "EventCode": "0xB7, 0xBB", 2768 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 2769 "MSRIndex": "0x1a6,0x1a7", 2770 "MSRValue": "0x1004000100", 2771 "Offcore": "1", 2772 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2773 "SampleAfterValue": "100003", 2774 "UMask": "0x1" 2775 }, 2776 { 2777 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2778 "Counter": "0,1,2,3", 2779 "CounterHTOff": "0,1,2,3", 2780 "EventCode": "0xB7, 0xBB", 2781 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 2782 "MSRIndex": "0x1a6,0x1a7", 2783 "MSRValue": "0x0404000100", 2784 "Offcore": "1", 2785 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2786 "SampleAfterValue": "100003", 2787 "UMask": "0x1" 2788 }, 2789 { 2790 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2791 "Counter": "0,1,2,3", 2792 "CounterHTOff": "0,1,2,3", 2793 "EventCode": "0xB7, 0xBB", 2794 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2795 "MSRIndex": "0x1a6,0x1a7", 2796 "MSRValue": "0x0204000100", 2797 "Offcore": "1", 2798 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2799 "SampleAfterValue": "100003", 2800 "UMask": "0x1" 2801 }, 2802 { 2803 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2804 "Counter": "0,1,2,3", 2805 "CounterHTOff": "0,1,2,3", 2806 "EventCode": "0xB7, 0xBB", 2807 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2808 "MSRIndex": "0x1a6,0x1a7", 2809 "MSRValue": "0x0084000100", 2810 "Offcore": "1", 2811 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2812 "SampleAfterValue": "100003", 2813 "UMask": "0x1" 2814 }, 2815 { 2816 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2817 "Counter": "0,1,2,3", 2818 "CounterHTOff": "0,1,2,3", 2819 "EventCode": "0xB7, 0xBB", 2820 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 2821 "MSRIndex": "0x1a6,0x1a7", 2822 "MSRValue": "0x2004000100", 2823 "Offcore": "1", 2824 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2825 "SampleAfterValue": "100003", 2826 "UMask": "0x1" 2827 }, 2828 { 2829 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2830 "Counter": "0,1,2,3", 2831 "CounterHTOff": "0,1,2,3", 2832 "EventCode": "0xB7, 0xBB", 2833 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 2834 "MSRIndex": "0x1a6,0x1a7", 2835 "MSRValue": "0x0104000100", 2836 "Offcore": "1", 2837 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2838 "SampleAfterValue": "100003", 2839 "UMask": "0x1" 2840 }, 2841 { 2842 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2843 "Counter": "0,1,2,3", 2844 "CounterHTOff": "0,1,2,3", 2845 "EventCode": "0xB7, 0xBB", 2846 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 2847 "MSRIndex": "0x1a6,0x1a7", 2848 "MSRValue": "0x2000020100", 2849 "Offcore": "1", 2850 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2851 "SampleAfterValue": "100003", 2852 "UMask": "0x1" 2853 }, 2854 { 2855 "BriefDescription": "Number of times RTM abort was triggered", 2856 "Counter": "0,1,2,3", 2857 "CounterHTOff": "0,1,2,3", 2858 "EventCode": "0xc9", 2859 "EventName": "RTM_RETIRED.ABORTED", 2860 "PEBS": "1", 2861 "PublicDescription": "Number of times RTM abort was triggered .", 2862 "SampleAfterValue": "2000003", 2863 "UMask": "0x4" 2864 }, 2865 { 2866 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 2867 "Counter": "0,1,2,3", 2868 "CounterHTOff": "0,1,2,3", 2869 "EventCode": "0xc9", 2870 "EventName": "RTM_RETIRED.ABORTED_MISC1", 2871 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 2872 "SampleAfterValue": "2000003", 2873 "UMask": "0x8" 2874 }, 2875 { 2876 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 2877 "Counter": "0,1,2,3", 2878 "CounterHTOff": "0,1,2,3", 2879 "EventCode": "0xc9", 2880 "EventName": "RTM_RETIRED.ABORTED_MISC2", 2881 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 2882 "SampleAfterValue": "2000003", 2883 "UMask": "0x10" 2884 }, 2885 { 2886 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 2887 "Counter": "0,1,2,3", 2888 "CounterHTOff": "0,1,2,3", 2889 "EventCode": "0xc9", 2890 "EventName": "RTM_RETIRED.ABORTED_MISC3", 2891 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 2892 "SampleAfterValue": "2000003", 2893 "UMask": "0x20" 2894 }, 2895 { 2896 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 2897 "Counter": "0,1,2,3", 2898 "CounterHTOff": "0,1,2,3", 2899 "EventCode": "0xc9", 2900 "EventName": "RTM_RETIRED.ABORTED_MISC4", 2901 "PublicDescription": "Number of times a RTM caused a fault.", 2902 "SampleAfterValue": "2000003", 2903 "UMask": "0x40" 2904 }, 2905 { 2906 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 2907 "Counter": "0,1,2,3", 2908 "CounterHTOff": "0,1,2,3", 2909 "EventCode": "0xc9", 2910 "EventName": "RTM_RETIRED.ABORTED_MISC5", 2911 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 2912 "SampleAfterValue": "2000003", 2913 "UMask": "0x80" 2914 }, 2915 { 2916 "BriefDescription": "Number of times RTM commit succeeded", 2917 "Counter": "0,1,2,3", 2918 "CounterHTOff": "0,1,2,3", 2919 "EventCode": "0xc9", 2920 "EventName": "RTM_RETIRED.COMMIT", 2921 "PublicDescription": "Number of times RTM commit succeeded.", 2922 "SampleAfterValue": "2000003", 2923 "UMask": "0x2" 2924 }, 2925 { 2926 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 2927 "Counter": "0,1,2,3", 2928 "CounterHTOff": "0,1,2,3", 2929 "EventCode": "0xc9", 2930 "EventName": "RTM_RETIRED.START", 2931 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 2932 "SampleAfterValue": "2000003", 2933 "UMask": "0x1" 2934 }, 2935 { 2936 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 2937 "Counter": "0,1,2,3", 2938 "CounterHTOff": "0,1,2,3,4,5,6,7", 2939 "EventCode": "0x5d", 2940 "EventName": "TX_EXEC.MISC1", 2941 "SampleAfterValue": "2000003", 2942 "UMask": "0x1" 2943 }, 2944 { 2945 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 2946 "Counter": "0,1,2,3", 2947 "CounterHTOff": "0,1,2,3,4,5,6,7", 2948 "EventCode": "0x5d", 2949 "EventName": "TX_EXEC.MISC2", 2950 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 2951 "SampleAfterValue": "2000003", 2952 "UMask": "0x2" 2953 }, 2954 { 2955 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 2956 "Counter": "0,1,2,3", 2957 "CounterHTOff": "0,1,2,3,4,5,6,7", 2958 "EventCode": "0x5d", 2959 "EventName": "TX_EXEC.MISC3", 2960 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 2961 "SampleAfterValue": "2000003", 2962 "UMask": "0x4" 2963 }, 2964 { 2965 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 2966 "Counter": "0,1,2,3", 2967 "CounterHTOff": "0,1,2,3,4,5,6,7", 2968 "EventCode": "0x5d", 2969 "EventName": "TX_EXEC.MISC4", 2970 "PublicDescription": "RTM region detected inside HLE.", 2971 "SampleAfterValue": "2000003", 2972 "UMask": "0x8" 2973 }, 2974 { 2975 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 2976 "Counter": "0,1,2,3", 2977 "CounterHTOff": "0,1,2,3,4,5,6,7", 2978 "EventCode": "0x5d", 2979 "EventName": "TX_EXEC.MISC5", 2980 "SampleAfterValue": "2000003", 2981 "UMask": "0x10" 2982 }, 2983 { 2984 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 2985 "Counter": "0,1,2,3", 2986 "CounterHTOff": "0,1,2,3,4,5,6,7", 2987 "EventCode": "0x54", 2988 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 2989 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 2990 "SampleAfterValue": "2000003", 2991 "UMask": "0x2" 2992 }, 2993 { 2994 "BriefDescription": "Number of times a TSX line had a cache conflict", 2995 "Counter": "0,1,2,3", 2996 "CounterHTOff": "0,1,2,3,4,5,6,7", 2997 "EventCode": "0x54", 2998 "EventName": "TX_MEM.ABORT_CONFLICT", 2999 "PublicDescription": "Number of times a TSX line had a cache conflict.", 3000 "SampleAfterValue": "2000003", 3001 "UMask": "0x1" 3002 }, 3003 { 3004 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 3005 "Counter": "0,1,2,3", 3006 "CounterHTOff": "0,1,2,3,4,5,6,7", 3007 "EventCode": "0x54", 3008 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 3009 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 3010 "SampleAfterValue": "2000003", 3011 "UMask": "0x10" 3012 }, 3013 { 3014 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 3015 "Counter": "0,1,2,3", 3016 "CounterHTOff": "0,1,2,3,4,5,6,7", 3017 "EventCode": "0x54", 3018 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 3019 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 3020 "SampleAfterValue": "2000003", 3021 "UMask": "0x8" 3022 }, 3023 { 3024 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 3025 "Counter": "0,1,2,3", 3026 "CounterHTOff": "0,1,2,3,4,5,6,7", 3027 "EventCode": "0x54", 3028 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 3029 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 3030 "SampleAfterValue": "2000003", 3031 "UMask": "0x20" 3032 }, 3033 { 3034 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 3035 "Counter": "0,1,2,3", 3036 "CounterHTOff": "0,1,2,3,4,5,6,7", 3037 "EventCode": "0x54", 3038 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 3039 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 3040 "SampleAfterValue": "2000003", 3041 "UMask": "0x4" 3042 }, 3043 { 3044 "BriefDescription": "Number of times we could not allocate Lock Buffer", 3045 "Counter": "0,1,2,3", 3046 "CounterHTOff": "0,1,2,3,4,5,6,7", 3047 "EventCode": "0x54", 3048 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 3049 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 3050 "SampleAfterValue": "2000003", 3051 "UMask": "0x40" 3052 } 3053]