xref: /freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json (revision b9f654b163bce26de79705e77b872427c9f2afa1)
1[
2    {
3        "EventCode": "0x80",
4        "Counter": "0,1",
5        "UMask": "0x3",
6        "EventName": "ICACHE.ACCESSES",
7        "SampleAfterValue": "200000",
8        "BriefDescription": "Instruction fetches."
9    },
10    {
11        "EventCode": "0x80",
12        "Counter": "0,1",
13        "UMask": "0x1",
14        "EventName": "ICACHE.HIT",
15        "SampleAfterValue": "200000",
16        "BriefDescription": "Icache hit"
17    },
18    {
19        "EventCode": "0x80",
20        "Counter": "0,1",
21        "UMask": "0x2",
22        "EventName": "ICACHE.MISSES",
23        "SampleAfterValue": "200000",
24        "BriefDescription": "Icache miss"
25    },
26    {
27        "EventCode": "0x86",
28        "Counter": "0,1",
29        "UMask": "0x1",
30        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
31        "SampleAfterValue": "2000000",
32        "BriefDescription": "Cycles during which instruction fetches are  stalled."
33    },
34    {
35        "EventCode": "0x87",
36        "Counter": "0,1",
37        "UMask": "0x1",
38        "EventName": "DECODE_STALL.PFB_EMPTY",
39        "SampleAfterValue": "2000000",
40        "BriefDescription": "Decode stall due to PFB empty"
41    },
42    {
43        "EventCode": "0x87",
44        "Counter": "0,1",
45        "UMask": "0x2",
46        "EventName": "DECODE_STALL.IQ_FULL",
47        "SampleAfterValue": "2000000",
48        "BriefDescription": "Decode stall due to IQ full"
49    },
50    {
51        "EventCode": "0xAA",
52        "Counter": "0,1",
53        "UMask": "0x1",
54        "EventName": "MACRO_INSTS.NON_CISC_DECODED",
55        "SampleAfterValue": "2000000",
56        "BriefDescription": "Non-CISC nacro instructions decoded"
57    },
58    {
59        "EventCode": "0xAA",
60        "Counter": "0,1",
61        "UMask": "0x2",
62        "EventName": "MACRO_INSTS.CISC_DECODED",
63        "SampleAfterValue": "2000000",
64        "BriefDescription": "CISC macro instructions decoded"
65    },
66    {
67        "EventCode": "0xAA",
68        "Counter": "0,1",
69        "UMask": "0x3",
70        "EventName": "MACRO_INSTS.ALL_DECODED",
71        "SampleAfterValue": "2000000",
72        "BriefDescription": "All Instructions decoded"
73    },
74    {
75        "EventCode": "0xA9",
76        "Counter": "0,1",
77        "UMask": "0x1",
78        "EventName": "UOPS.MS_CYCLES",
79        "SampleAfterValue": "2000000",
80        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
81        "CounterMask": "1"
82    }
83]