1*959826caSMatt Macy[ 2*959826caSMatt Macy { 3*959826caSMatt Macy "EventCode": "0x80", 4*959826caSMatt Macy "Counter": "0,1", 5*959826caSMatt Macy "UMask": "0x3", 6*959826caSMatt Macy "EventName": "ICACHE.ACCESSES", 7*959826caSMatt Macy "SampleAfterValue": "200000", 8*959826caSMatt Macy "BriefDescription": "Instruction fetches." 9*959826caSMatt Macy }, 10*959826caSMatt Macy { 11*959826caSMatt Macy "EventCode": "0x80", 12*959826caSMatt Macy "Counter": "0,1", 13*959826caSMatt Macy "UMask": "0x1", 14*959826caSMatt Macy "EventName": "ICACHE.HIT", 15*959826caSMatt Macy "SampleAfterValue": "200000", 16*959826caSMatt Macy "BriefDescription": "Icache hit" 17*959826caSMatt Macy }, 18*959826caSMatt Macy { 19*959826caSMatt Macy "EventCode": "0x80", 20*959826caSMatt Macy "Counter": "0,1", 21*959826caSMatt Macy "UMask": "0x2", 22*959826caSMatt Macy "EventName": "ICACHE.MISSES", 23*959826caSMatt Macy "SampleAfterValue": "200000", 24*959826caSMatt Macy "BriefDescription": "Icache miss" 25*959826caSMatt Macy }, 26*959826caSMatt Macy { 27*959826caSMatt Macy "EventCode": "0x86", 28*959826caSMatt Macy "Counter": "0,1", 29*959826caSMatt Macy "UMask": "0x1", 30*959826caSMatt Macy "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", 31*959826caSMatt Macy "SampleAfterValue": "2000000", 32*959826caSMatt Macy "BriefDescription": "Cycles during which instruction fetches are stalled." 33*959826caSMatt Macy }, 34*959826caSMatt Macy { 35*959826caSMatt Macy "EventCode": "0x87", 36*959826caSMatt Macy "Counter": "0,1", 37*959826caSMatt Macy "UMask": "0x1", 38*959826caSMatt Macy "EventName": "DECODE_STALL.PFB_EMPTY", 39*959826caSMatt Macy "SampleAfterValue": "2000000", 40*959826caSMatt Macy "BriefDescription": "Decode stall due to PFB empty" 41*959826caSMatt Macy }, 42*959826caSMatt Macy { 43*959826caSMatt Macy "EventCode": "0x87", 44*959826caSMatt Macy "Counter": "0,1", 45*959826caSMatt Macy "UMask": "0x2", 46*959826caSMatt Macy "EventName": "DECODE_STALL.IQ_FULL", 47*959826caSMatt Macy "SampleAfterValue": "2000000", 48*959826caSMatt Macy "BriefDescription": "Decode stall due to IQ full" 49*959826caSMatt Macy }, 50*959826caSMatt Macy { 51*959826caSMatt Macy "EventCode": "0xAA", 52*959826caSMatt Macy "Counter": "0,1", 53*959826caSMatt Macy "UMask": "0x1", 54*959826caSMatt Macy "EventName": "MACRO_INSTS.NON_CISC_DECODED", 55*959826caSMatt Macy "SampleAfterValue": "2000000", 56*959826caSMatt Macy "BriefDescription": "Non-CISC nacro instructions decoded" 57*959826caSMatt Macy }, 58*959826caSMatt Macy { 59*959826caSMatt Macy "EventCode": "0xAA", 60*959826caSMatt Macy "Counter": "0,1", 61*959826caSMatt Macy "UMask": "0x2", 62*959826caSMatt Macy "EventName": "MACRO_INSTS.CISC_DECODED", 63*959826caSMatt Macy "SampleAfterValue": "2000000", 64*959826caSMatt Macy "BriefDescription": "CISC macro instructions decoded" 65*959826caSMatt Macy }, 66*959826caSMatt Macy { 67*959826caSMatt Macy "EventCode": "0xAA", 68*959826caSMatt Macy "Counter": "0,1", 69*959826caSMatt Macy "UMask": "0x3", 70*959826caSMatt Macy "EventName": "MACRO_INSTS.ALL_DECODED", 71*959826caSMatt Macy "SampleAfterValue": "2000000", 72*959826caSMatt Macy "BriefDescription": "All Instructions decoded" 73*959826caSMatt Macy }, 74*959826caSMatt Macy { 75*959826caSMatt Macy "EventCode": "0xA9", 76*959826caSMatt Macy "Counter": "0,1", 77*959826caSMatt Macy "UMask": "0x1", 78*959826caSMatt Macy "EventName": "UOPS.MS_CYCLES", 79*959826caSMatt Macy "SampleAfterValue": "2000000", 80*959826caSMatt Macy "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ", 81*959826caSMatt Macy "CounterMask": "1" 82*959826caSMatt Macy } 83*959826caSMatt Macy]