xref: /freebsd/lib/libpmc/pmu-events/arch/x86/bonnell/frontend.json (revision 18054d0220cfc8df9c9568c437bd6fbb59d53c3c)
1959826caSMatt Macy[
2959826caSMatt Macy    {
3*18054d02SAlexander Motin        "BriefDescription": "BACLEARS asserted.",
4959826caSMatt Macy        "Counter": "0,1",
5*18054d02SAlexander Motin        "EventCode": "0xE6",
6*18054d02SAlexander Motin        "EventName": "BACLEARS.ANY",
7*18054d02SAlexander Motin        "SampleAfterValue": "2000000",
8*18054d02SAlexander Motin        "UMask": "0x1"
9959826caSMatt Macy    },
10959826caSMatt Macy    {
11*18054d02SAlexander Motin        "BriefDescription": "Cycles during which instruction fetches are  stalled.",
12959826caSMatt Macy        "Counter": "0,1",
13959826caSMatt Macy        "EventCode": "0x86",
14959826caSMatt Macy        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
15959826caSMatt Macy        "SampleAfterValue": "2000000",
16*18054d02SAlexander Motin        "UMask": "0x1"
17959826caSMatt Macy    },
18959826caSMatt Macy    {
19*18054d02SAlexander Motin        "BriefDescription": "Decode stall due to IQ full",
20959826caSMatt Macy        "Counter": "0,1",
21959826caSMatt Macy        "EventCode": "0x87",
22959826caSMatt Macy        "EventName": "DECODE_STALL.IQ_FULL",
23959826caSMatt Macy        "SampleAfterValue": "2000000",
24*18054d02SAlexander Motin        "UMask": "0x2"
25959826caSMatt Macy    },
26959826caSMatt Macy    {
27*18054d02SAlexander Motin        "BriefDescription": "Decode stall due to PFB empty",
28959826caSMatt Macy        "Counter": "0,1",
29*18054d02SAlexander Motin        "EventCode": "0x87",
30*18054d02SAlexander Motin        "EventName": "DECODE_STALL.PFB_EMPTY",
31959826caSMatt Macy        "SampleAfterValue": "2000000",
32*18054d02SAlexander Motin        "UMask": "0x1"
33959826caSMatt Macy    },
34959826caSMatt Macy    {
35*18054d02SAlexander Motin        "BriefDescription": "Instruction fetches.",
36959826caSMatt Macy        "Counter": "0,1",
37*18054d02SAlexander Motin        "EventCode": "0x80",
38*18054d02SAlexander Motin        "EventName": "ICACHE.ACCESSES",
39*18054d02SAlexander Motin        "SampleAfterValue": "200000",
40*18054d02SAlexander Motin        "UMask": "0x3"
41959826caSMatt Macy    },
42959826caSMatt Macy    {
43*18054d02SAlexander Motin        "BriefDescription": "Icache hit",
44959826caSMatt Macy        "Counter": "0,1",
45*18054d02SAlexander Motin        "EventCode": "0x80",
46*18054d02SAlexander Motin        "EventName": "ICACHE.HIT",
47*18054d02SAlexander Motin        "SampleAfterValue": "200000",
48*18054d02SAlexander Motin        "UMask": "0x1"
49*18054d02SAlexander Motin    },
50*18054d02SAlexander Motin    {
51*18054d02SAlexander Motin        "BriefDescription": "Icache miss",
52*18054d02SAlexander Motin        "Counter": "0,1",
53*18054d02SAlexander Motin        "EventCode": "0x80",
54*18054d02SAlexander Motin        "EventName": "ICACHE.MISSES",
55*18054d02SAlexander Motin        "SampleAfterValue": "200000",
56*18054d02SAlexander Motin        "UMask": "0x2"
57*18054d02SAlexander Motin    },
58*18054d02SAlexander Motin    {
59*18054d02SAlexander Motin        "BriefDescription": "All Instructions decoded",
60*18054d02SAlexander Motin        "Counter": "0,1",
61*18054d02SAlexander Motin        "EventCode": "0xAA",
62959826caSMatt Macy        "EventName": "MACRO_INSTS.ALL_DECODED",
63959826caSMatt Macy        "SampleAfterValue": "2000000",
64*18054d02SAlexander Motin        "UMask": "0x3"
65959826caSMatt Macy    },
66959826caSMatt Macy    {
67*18054d02SAlexander Motin        "BriefDescription": "CISC macro instructions decoded",
68959826caSMatt Macy        "Counter": "0,1",
69*18054d02SAlexander Motin        "EventCode": "0xAA",
70*18054d02SAlexander Motin        "EventName": "MACRO_INSTS.CISC_DECODED",
71*18054d02SAlexander Motin        "SampleAfterValue": "2000000",
72*18054d02SAlexander Motin        "UMask": "0x2"
73*18054d02SAlexander Motin    },
74*18054d02SAlexander Motin    {
75*18054d02SAlexander Motin        "BriefDescription": "Non-CISC nacro instructions decoded",
76*18054d02SAlexander Motin        "Counter": "0,1",
77*18054d02SAlexander Motin        "EventCode": "0xAA",
78*18054d02SAlexander Motin        "EventName": "MACRO_INSTS.NON_CISC_DECODED",
79*18054d02SAlexander Motin        "SampleAfterValue": "2000000",
80*18054d02SAlexander Motin        "UMask": "0x1"
81*18054d02SAlexander Motin    },
82*18054d02SAlexander Motin    {
83*18054d02SAlexander Motin        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
84*18054d02SAlexander Motin        "Counter": "0,1",
85*18054d02SAlexander Motin        "CounterMask": "1",
86*18054d02SAlexander Motin        "EventCode": "0xA9",
87959826caSMatt Macy        "EventName": "UOPS.MS_CYCLES",
88959826caSMatt Macy        "SampleAfterValue": "2000000",
89*18054d02SAlexander Motin        "UMask": "0x1"
90959826caSMatt Macy    }
91959826caSMatt Macy]