xref: /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen6/memory-controller.json (revision 178d0b5b8da7480f455273aedf40dd8f1e785d3f) 
1*178d0b5bSAli Mashtizadeh[
2*178d0b5bSAli Mashtizadeh  {
3*178d0b5bSAli Mashtizadeh    "EventName": "umc_mem_clk",
4*178d0b5bSAli Mashtizadeh    "PublicDescription": "Memory clock (MEMCLK) cycles.",
5*178d0b5bSAli Mashtizadeh    "EventCode": "0x00",
6*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
7*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
8*178d0b5bSAli Mashtizadeh  },
9*178d0b5bSAli Mashtizadeh  {
10*178d0b5bSAli Mashtizadeh    "EventName": "umc_act_cmd.all",
11*178d0b5bSAli Mashtizadeh    "PublicDescription": "ACTIVATE commands sent.",
12*178d0b5bSAli Mashtizadeh    "EventCode": "0x05",
13*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
14*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
15*178d0b5bSAli Mashtizadeh  },
16*178d0b5bSAli Mashtizadeh  {
17*178d0b5bSAli Mashtizadeh    "EventName": "umc_act_cmd.rd",
18*178d0b5bSAli Mashtizadeh    "PublicDescription": "ACTIVATE commands sent for reads.",
19*178d0b5bSAli Mashtizadeh    "EventCode": "0x05",
20*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x1",
21*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
22*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
23*178d0b5bSAli Mashtizadeh  },
24*178d0b5bSAli Mashtizadeh  {
25*178d0b5bSAli Mashtizadeh    "EventName": "umc_act_cmd.wr",
26*178d0b5bSAli Mashtizadeh    "PublicDescription": "ACTIVATE commands sent for writes.",
27*178d0b5bSAli Mashtizadeh    "EventCode": "0x05",
28*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x2",
29*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
30*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
31*178d0b5bSAli Mashtizadeh  },
32*178d0b5bSAli Mashtizadeh  {
33*178d0b5bSAli Mashtizadeh    "EventName": "umc_pchg_cmd.all",
34*178d0b5bSAli Mashtizadeh    "PublicDescription": "PRECHARGE commands sent.",
35*178d0b5bSAli Mashtizadeh    "EventCode": "0x06",
36*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
37*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
38*178d0b5bSAli Mashtizadeh  },
39*178d0b5bSAli Mashtizadeh  {
40*178d0b5bSAli Mashtizadeh    "EventName": "umc_pchg_cmd.rd",
41*178d0b5bSAli Mashtizadeh    "PublicDescription": "PRECHARGE commands sent for reads.",
42*178d0b5bSAli Mashtizadeh    "EventCode": "0x06",
43*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x1",
44*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
45*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
46*178d0b5bSAli Mashtizadeh  },
47*178d0b5bSAli Mashtizadeh  {
48*178d0b5bSAli Mashtizadeh    "EventName": "umc_pchg_cmd.wr",
49*178d0b5bSAli Mashtizadeh    "PublicDescription": "PRECHARGE commands sent for writes.",
50*178d0b5bSAli Mashtizadeh    "EventCode": "0x06",
51*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x2",
52*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
53*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
54*178d0b5bSAli Mashtizadeh  },
55*178d0b5bSAli Mashtizadeh  {
56*178d0b5bSAli Mashtizadeh    "EventName": "umc_cas_cmd.all",
57*178d0b5bSAli Mashtizadeh    "PublicDescription": "CAS commands sent.",
58*178d0b5bSAli Mashtizadeh    "EventCode": "0x0a",
59*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
60*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
61*178d0b5bSAli Mashtizadeh  },
62*178d0b5bSAli Mashtizadeh  {
63*178d0b5bSAli Mashtizadeh    "EventName": "umc_cas_cmd.rd",
64*178d0b5bSAli Mashtizadeh    "PublicDescription": "CAS commands sent for reads.",
65*178d0b5bSAli Mashtizadeh    "EventCode": "0x0a",
66*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x1",
67*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
68*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
69*178d0b5bSAli Mashtizadeh  },
70*178d0b5bSAli Mashtizadeh  {
71*178d0b5bSAli Mashtizadeh    "EventName": "umc_cas_cmd.wr",
72*178d0b5bSAli Mashtizadeh    "PublicDescription": "CAS commands sent for writes.",
73*178d0b5bSAli Mashtizadeh    "EventCode": "0x0a",
74*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x2",
75*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
76*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
77*178d0b5bSAli Mashtizadeh  },
78*178d0b5bSAli Mashtizadeh  {
79*178d0b5bSAli Mashtizadeh    "EventName": "umc_data_slot_clks.all",
80*178d0b5bSAli Mashtizadeh    "PublicDescription": "Clock cycles where the data bus is utilized.",
81*178d0b5bSAli Mashtizadeh    "EventCode": "0x14",
82*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
83*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
84*178d0b5bSAli Mashtizadeh  },
85*178d0b5bSAli Mashtizadeh  {
86*178d0b5bSAli Mashtizadeh    "EventName": "umc_data_slot_clks.rd",
87*178d0b5bSAli Mashtizadeh    "PublicDescription": "Clock cycles where the data bus is utilized for reads.",
88*178d0b5bSAli Mashtizadeh    "EventCode": "0x14",
89*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x1",
90*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
91*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
92*178d0b5bSAli Mashtizadeh  },
93*178d0b5bSAli Mashtizadeh  {
94*178d0b5bSAli Mashtizadeh    "EventName": "umc_data_slot_clks.wr",
95*178d0b5bSAli Mashtizadeh    "PublicDescription": "Clock cycles where the data bus is utilized for writes.",
96*178d0b5bSAli Mashtizadeh    "EventCode": "0x14",
97*178d0b5bSAli Mashtizadeh    "RdWrMask": "0x2",
98*178d0b5bSAli Mashtizadeh    "PerPkg": "1",
99*178d0b5bSAli Mashtizadeh    "Unit": "UMCPMC"
100*178d0b5bSAli Mashtizadeh  }
101*178d0b5bSAli Mashtizadeh]
102