xref: /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen5/memory-controller.json (revision bae832487038b2c8778dc6f52700b4353175ccec) 
1*bae83248SAli Mashtizadeh[
2*bae83248SAli Mashtizadeh  {
3*bae83248SAli Mashtizadeh    "EventName": "umc_mem_clk",
4*bae83248SAli Mashtizadeh    "PublicDescription": "Number of memory clock (MEMCLK) cycles.",
5*bae83248SAli Mashtizadeh    "EventCode": "0x00",
6*bae83248SAli Mashtizadeh    "PerPkg": "1",
7*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
8*bae83248SAli Mashtizadeh  },
9*bae83248SAli Mashtizadeh  {
10*bae83248SAli Mashtizadeh    "EventName": "umc_act_cmd.all",
11*bae83248SAli Mashtizadeh    "PublicDescription": "Number of ACTIVATE commands sent.",
12*bae83248SAli Mashtizadeh    "EventCode": "0x05",
13*bae83248SAli Mashtizadeh    "PerPkg": "1",
14*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
15*bae83248SAli Mashtizadeh  },
16*bae83248SAli Mashtizadeh  {
17*bae83248SAli Mashtizadeh    "EventName": "umc_act_cmd.rd",
18*bae83248SAli Mashtizadeh    "PublicDescription": "Number of ACTIVATE commands sent for reads.",
19*bae83248SAli Mashtizadeh    "EventCode": "0x05",
20*bae83248SAli Mashtizadeh    "RdWrMask": "0x1",
21*bae83248SAli Mashtizadeh    "PerPkg": "1",
22*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
23*bae83248SAli Mashtizadeh  },
24*bae83248SAli Mashtizadeh  {
25*bae83248SAli Mashtizadeh    "EventName": "umc_act_cmd.wr",
26*bae83248SAli Mashtizadeh    "PublicDescription": "Number of ACTIVATE commands sent for writes.",
27*bae83248SAli Mashtizadeh    "EventCode": "0x05",
28*bae83248SAli Mashtizadeh    "RdWrMask": "0x2",
29*bae83248SAli Mashtizadeh    "PerPkg": "1",
30*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
31*bae83248SAli Mashtizadeh  },
32*bae83248SAli Mashtizadeh  {
33*bae83248SAli Mashtizadeh    "EventName": "umc_pchg_cmd.all",
34*bae83248SAli Mashtizadeh    "PublicDescription": "Number of PRECHARGE commands sent.",
35*bae83248SAli Mashtizadeh    "EventCode": "0x06",
36*bae83248SAli Mashtizadeh    "PerPkg": "1",
37*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
38*bae83248SAli Mashtizadeh  },
39*bae83248SAli Mashtizadeh  {
40*bae83248SAli Mashtizadeh    "EventName": "umc_pchg_cmd.rd",
41*bae83248SAli Mashtizadeh    "PublicDescription": "Number of PRECHARGE commands sent for reads.",
42*bae83248SAli Mashtizadeh    "EventCode": "0x06",
43*bae83248SAli Mashtizadeh    "RdWrMask": "0x1",
44*bae83248SAli Mashtizadeh    "PerPkg": "1",
45*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
46*bae83248SAli Mashtizadeh  },
47*bae83248SAli Mashtizadeh  {
48*bae83248SAli Mashtizadeh    "EventName": "umc_pchg_cmd.wr",
49*bae83248SAli Mashtizadeh    "PublicDescription": "Number of PRECHARGE commands sent for writes.",
50*bae83248SAli Mashtizadeh    "EventCode": "0x06",
51*bae83248SAli Mashtizadeh    "RdWrMask": "0x2",
52*bae83248SAli Mashtizadeh    "PerPkg": "1",
53*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
54*bae83248SAli Mashtizadeh  },
55*bae83248SAli Mashtizadeh  {
56*bae83248SAli Mashtizadeh    "EventName": "umc_cas_cmd.all",
57*bae83248SAli Mashtizadeh    "PublicDescription": "Number of CAS commands sent.",
58*bae83248SAli Mashtizadeh    "EventCode": "0x0a",
59*bae83248SAli Mashtizadeh    "PerPkg": "1",
60*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
61*bae83248SAli Mashtizadeh  },
62*bae83248SAli Mashtizadeh  {
63*bae83248SAli Mashtizadeh    "EventName": "umc_cas_cmd.rd",
64*bae83248SAli Mashtizadeh    "PublicDescription": "Number of CAS commands sent for reads.",
65*bae83248SAli Mashtizadeh    "EventCode": "0x0a",
66*bae83248SAli Mashtizadeh    "RdWrMask": "0x1",
67*bae83248SAli Mashtizadeh    "PerPkg": "1",
68*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
69*bae83248SAli Mashtizadeh  },
70*bae83248SAli Mashtizadeh  {
71*bae83248SAli Mashtizadeh    "EventName": "umc_cas_cmd.wr",
72*bae83248SAli Mashtizadeh    "PublicDescription": "Number of CAS commands sent for writes.",
73*bae83248SAli Mashtizadeh    "EventCode": "0x0a",
74*bae83248SAli Mashtizadeh    "RdWrMask": "0x2",
75*bae83248SAli Mashtizadeh    "PerPkg": "1",
76*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
77*bae83248SAli Mashtizadeh  },
78*bae83248SAli Mashtizadeh  {
79*bae83248SAli Mashtizadeh    "EventName": "umc_data_slot_clks.all",
80*bae83248SAli Mashtizadeh    "PublicDescription": "Number of clock cycles used by the data bus.",
81*bae83248SAli Mashtizadeh    "EventCode": "0x14",
82*bae83248SAli Mashtizadeh    "PerPkg": "1",
83*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
84*bae83248SAli Mashtizadeh  },
85*bae83248SAli Mashtizadeh  {
86*bae83248SAli Mashtizadeh    "EventName": "umc_data_slot_clks.rd",
87*bae83248SAli Mashtizadeh    "PublicDescription": "Number of clock cycles used by the data bus for reads.",
88*bae83248SAli Mashtizadeh    "EventCode": "0x14",
89*bae83248SAli Mashtizadeh    "RdWrMask": "0x1",
90*bae83248SAli Mashtizadeh    "PerPkg": "1",
91*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
92*bae83248SAli Mashtizadeh  },
93*bae83248SAli Mashtizadeh  {
94*bae83248SAli Mashtizadeh    "EventName": "umc_data_slot_clks.wr",
95*bae83248SAli Mashtizadeh    "PublicDescription": "Number of clock cycles used by the data bus for writes.",
96*bae83248SAli Mashtizadeh    "EventCode": "0x14",
97*bae83248SAli Mashtizadeh    "RdWrMask": "0x2",
98*bae83248SAli Mashtizadeh    "PerPkg": "1",
99*bae83248SAli Mashtizadeh    "Unit": "UMCPMC"
100*bae83248SAli Mashtizadeh  }
101*bae83248SAli Mashtizadeh]
102