x86/amdzen3/memory.json

[
  {
    "EventName": "ls_bad_status2.stli_other",
    "EventCode": "0x24",
    "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
    "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_locks.spec_lock_hi_spec",
    "EventCode": "0x25",
    "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_locks.spec_lock_lo_spec",
    "EventCode": "0x25",
    "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_locks.non_spec_lock",
    "EventCode": "0x25",
    "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_locks.bus_lock",
    "EventCode": "0x25",
    "BriefDescription": "Retired lock instructions. Comparable to legacy bus lock.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_ret_cl_flush",
    "EventCode": "0x26",
    "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event."
  },
  {
    "EventName": "ls_ret_cpuid",
    "EventCode": "0x27",
    "BriefDescription": "The number of CPUID instructions retired."
  },
  {
    "EventName": "ls_dispatch.ld_st_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_dispatch.store_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dispatch.ld_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_smi_rx",
    "EventCode": "0x2b",
    "BriefDescription": "Counts the number of SMIs received."
  },
  {
    "EventName": "ls_int_taken",
    "EventCode": "0x2c",
    "BriefDescription": "Counts the number of interrupts taken."
  },
  {
    "EventName": "ls_rdtsc",
    "EventCode": "0x2d",
    "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
  },
  {
    "EventName": "ls_stlf",
    "EventCode": "0x35",
    "BriefDescription": "Number of STLF hits."
  },
  {
    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
    "EventCode": "0x37",
    "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_dc_accesses",
    "EventCode": "0x40",
    "BriefDescription": "Number of accesses to the dcache for load/store references.",
    "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
  },
  {
    "EventName": "ls_mab_alloc.all_allocations",
    "EventCode": "0x41",
    "BriefDescription": "All Allocations. Counts when a LS pipe allocates a MAB entry.",
    "UMask": "0x7f"
  },
  {
    "EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
    "EventCode": "0x41",
    "BriefDescription": "Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_mab_alloc.load_store_allocations",
    "EventCode": "0x41",
    "BriefDescription": "Load Store Allocations. Counts when a LS pipe allocates a MAB entry.",
    "UMask": "0x3f"
  },
  {
    "EventName": "ls_mab_alloc.dc_prefetcher",
    "EventCode": "0x41",
    "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_mab_alloc.stores",
    "EventCode": "0x41",
    "BriefDescription": "LS MAB Allocates by Type. Stores.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_mab_alloc.loads",
    "EventCode": "0x41",
    "BriefDescription": "LS MAB Allocates by Type. Loads.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.mem_io_remote",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.ext_cache_remote",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From CCX Cache in different Node.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.mem_io_local",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.ext_cache_local",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From cache of different CCX in same node.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.int_cache",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dmnd_fills_from_sys.lcl_l2",
    "EventCode": "0x43",
    "BriefDescription": "Demand Data Cache Fills by Data Source. From Local L2 to the core.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_any_fills_from_sys.mem_io_remote",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_any_fills_from_sys.ext_cache_remote",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From CCX Cache in different Node.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_any_fills_from_sys.mem_io_local",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_any_fills_from_sys.ext_cache_local",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From cache of different CCX in same node.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_any_fills_from_sys.int_cache",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_any_fills_from_sys.lcl_l2",
    "EventCode": "0x44",
    "BriefDescription": "Any Data Cache Fills by Data Source. From Local L2 to the core.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.all",
    "EventCode": "0x45",
    "BriefDescription": "All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead.",
    "UMask": "0xff"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.",
    "UMask": "0x80"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.",
    "UMask": "0x20"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_tablewalker.iside",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks on I-side.",
    "UMask": "0x0c"
  },
  {
    "EventName": "ls_tablewalker.ic_type1",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks IC Type 1.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_tablewalker.ic_type0",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks IC Type 0.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_tablewalker.dside",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks on D-side.",
    "UMask": "0x03"
  },
  {
    "EventName": "ls_tablewalker.dc_type1",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks DC Type 1.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_tablewalker.dc_type0",
    "EventCode": "0x46",
    "BriefDescription": "Total Page Table Walks DC Type 0.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_misal_loads.ma4k",
    "EventCode": "0x47",
    "BriefDescription": "The number of 4KB misaligned (i.e., page crossing) loads.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_misal_loads.ma64",
    "EventCode": "0x47",
    "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_pref_instr_disp",
    "EventCode": "0x4b",
    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
    "UMask": "0xff"
  },
  {
    "EventName": "ls_pref_instr_disp.prefetch_nta",
    "EventCode": "0x4b",
    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_pref_instr_disp.prefetch_w",
    "EventCode": "0x4b",
    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_pref_instr_disp.prefetch",
    "EventCode": "0x4b",
    "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
    "EventCode": "0x52",
    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
    "EventCode": "0x52",
    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.mem_io_remote",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.ext_cache_remote",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.mem_io_local",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.ext_cache_local",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.int_cache",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_sw_pf_dc_fills.lcl_l2",
    "EventCode": "0x59",
    "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.mem_io_remote",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
    "UMask": "0x40"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.ext_cache_remote",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.mem_io_local",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.ext_cache_local",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.int_cache",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_hw_pf_dc_fills.lcl_l2",
    "EventCode": "0x5a",
    "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_alloc_mab_count",
    "EventCode": "0x5f",
    "BriefDescription": "Count of Allocated Mabs",
    "PublicDescription": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]."
  },
  {
    "EventName": "ls_not_halted_cyc",
    "EventCode": "0x76",
    "BriefDescription": "Cycles not in Halt."
  },
  {
    "EventName": "ls_tlb_flush.all_tlb_flushes",
    "EventCode": "0x78",
    "BriefDescription": "All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead",
    "UMask": "0xff"
  }
]