1[ 2 { 3 "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5", 6 "EventCode": "0xc4", 7 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 8 "PEBS": "1", 9 "PEBScounters": "0,1,2,3,4,5", 10 "SampleAfterValue": "200003", 11 "Unit": "cpu_atom" 12 }, 13 { 14 "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL", 15 "CollectPEBSRecord": "2", 16 "Counter": "0,1,2,3,4,5", 17 "EventCode": "0xc4", 18 "EventName": "BR_INST_RETIRED.CALL", 19 "PEBS": "1", 20 "PEBScounters": "0,1,2,3,4,5", 21 "SampleAfterValue": "200003", 22 "UMask": "0xf9", 23 "Unit": "cpu_atom" 24 }, 25 { 26 "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return.", 27 "CollectPEBSRecord": "2", 28 "Counter": "0,1,2,3,4,5", 29 "EventCode": "0xc4", 30 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 31 "PEBS": "1", 32 "PEBScounters": "0,1,2,3,4,5", 33 "SampleAfterValue": "200003", 34 "UMask": "0xbf", 35 "Unit": "cpu_atom" 36 }, 37 { 38 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 39 "CollectPEBSRecord": "2", 40 "Counter": "0,1,2,3,4,5", 41 "EventCode": "0xc4", 42 "EventName": "BR_INST_RETIRED.NEAR_CALL", 43 "PEBS": "1", 44 "PEBScounters": "0,1,2,3,4,5", 45 "SampleAfterValue": "200003", 46 "UMask": "0xf9", 47 "Unit": "cpu_atom" 48 }, 49 { 50 "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", 51 "CollectPEBSRecord": "2", 52 "Counter": "0,1,2,3,4,5", 53 "EventCode": "0xc5", 54 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 55 "PEBS": "1", 56 "PEBScounters": "0,1,2,3,4,5", 57 "SampleAfterValue": "200003", 58 "Unit": "cpu_atom" 59 }, 60 { 61 "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", 62 "CollectPEBSRecord": "2", 63 "Counter": "33", 64 "EventName": "CPU_CLK_UNHALTED.CORE", 65 "PEBScounters": "33", 66 "SampleAfterValue": "2000003", 67 "UMask": "0x2", 68 "Unit": "cpu_atom" 69 }, 70 { 71 "BriefDescription": "Counts the number of unhalted core clock cycles.", 72 "CollectPEBSRecord": "2", 73 "Counter": "0,1,2,3,4,5", 74 "EventCode": "0x3c", 75 "EventName": "CPU_CLK_UNHALTED.CORE_P", 76 "PEBScounters": "0,1,2,3,4,5", 77 "SampleAfterValue": "2000003", 78 "Unit": "cpu_atom" 79 }, 80 { 81 "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", 82 "CollectPEBSRecord": "2", 83 "Counter": "34", 84 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 85 "PEBScounters": "34", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x3", 88 "Unit": "cpu_atom" 89 }, 90 { 91 "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", 92 "CollectPEBSRecord": "2", 93 "Counter": "33", 94 "EventName": "CPU_CLK_UNHALTED.THREAD", 95 "PEBScounters": "33", 96 "SampleAfterValue": "2000003", 97 "UMask": "0x2", 98 "Unit": "cpu_atom" 99 }, 100 { 101 "BriefDescription": "Counts the number of unhalted core clock cycles.", 102 "CollectPEBSRecord": "2", 103 "Counter": "0,1,2,3,4,5", 104 "EventCode": "0x3c", 105 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 106 "PEBScounters": "0,1,2,3,4,5", 107 "SampleAfterValue": "2000003", 108 "Unit": "cpu_atom" 109 }, 110 { 111 "BriefDescription": "Counts the number of instructions retired. (Fixed event)", 112 "CollectPEBSRecord": "2", 113 "Counter": "32", 114 "EventName": "INST_RETIRED.ANY", 115 "PEBS": "1", 116 "PEBScounters": "32", 117 "SampleAfterValue": "2000003", 118 "UMask": "0x1", 119 "Unit": "cpu_atom" 120 }, 121 { 122 "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", 123 "CollectPEBSRecord": "2", 124 "Counter": "0,1,2,3,4,5", 125 "EventCode": "0x03", 126 "EventName": "LD_BLOCKS.4K_ALIAS", 127 "PEBS": "1", 128 "PEBScounters": "0,1,2,3,4,5", 129 "SampleAfterValue": "1000003", 130 "UMask": "0x4", 131 "Unit": "cpu_atom" 132 }, 133 { 134 "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", 135 "CollectPEBSRecord": "2", 136 "Counter": "0,1,2,3,4,5", 137 "EventCode": "0x03", 138 "EventName": "LD_BLOCKS.ADDRESS_ALIAS", 139 "PEBS": "1", 140 "PEBScounters": "0,1,2,3,4,5", 141 "SampleAfterValue": "1000003", 142 "UMask": "0x4", 143 "Unit": "cpu_atom" 144 }, 145 { 146 "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", 147 "CollectPEBSRecord": "2", 148 "Counter": "0,1,2,3,4,5", 149 "EventCode": "0x03", 150 "EventName": "LD_BLOCKS.DATA_UNKNOWN", 151 "PEBS": "1", 152 "PEBScounters": "0,1,2,3,4,5", 153 "SampleAfterValue": "1000003", 154 "UMask": "0x1", 155 "Unit": "cpu_atom" 156 }, 157 { 158 "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", 159 "CollectPEBSRecord": "2", 160 "Counter": "0,1,2,3,4,5", 161 "EventCode": "0xc3", 162 "EventName": "MACHINE_CLEARS.DISAMBIGUATION", 163 "PEBScounters": "0,1,2,3,4,5", 164 "SampleAfterValue": "20003", 165 "UMask": "0x8", 166 "Unit": "cpu_atom" 167 }, 168 { 169 "BriefDescription": "Counts the number of machines clears due to memory renaming.", 170 "CollectPEBSRecord": "2", 171 "Counter": "0,1,2,3,4,5", 172 "EventCode": "0xc3", 173 "EventName": "MACHINE_CLEARS.MRN_NUKE", 174 "PEBScounters": "0,1,2,3,4,5", 175 "SampleAfterValue": "1000003", 176 "UMask": "0x80", 177 "Unit": "cpu_atom" 178 }, 179 { 180 "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", 181 "CollectPEBSRecord": "2", 182 "Counter": "0,1,2,3,4,5", 183 "EventCode": "0xc3", 184 "EventName": "MACHINE_CLEARS.PAGE_FAULT", 185 "PEBS": "1", 186 "PEBScounters": "0,1,2,3,4,5", 187 "SampleAfterValue": "20003", 188 "UMask": "0x20", 189 "Unit": "cpu_atom" 190 }, 191 { 192 "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", 193 "CollectPEBSRecord": "2", 194 "Counter": "0,1,2,3,4,5", 195 "EventCode": "0xc3", 196 "EventName": "MACHINE_CLEARS.SLOW", 197 "PEBScounters": "0,1,2,3,4,5", 198 "SampleAfterValue": "20003", 199 "UMask": "0x6f", 200 "Unit": "cpu_atom" 201 }, 202 { 203 "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", 204 "CollectPEBSRecord": "2", 205 "Counter": "0,1,2,3,4,5", 206 "EventCode": "0xc3", 207 "EventName": "MACHINE_CLEARS.SMC", 208 "PEBScounters": "0,1,2,3,4,5", 209 "SampleAfterValue": "20003", 210 "UMask": "0x1", 211 "Unit": "cpu_atom" 212 }, 213 { 214 "BriefDescription": "Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires.", 215 "CollectPEBSRecord": "2", 216 "Counter": "0,1,2,3,4,5", 217 "EventCode": "0x75", 218 "EventName": "SERIALIZATION.NON_C01_MS_SCB", 219 "PEBScounters": "0,1,2,3,4,5", 220 "SampleAfterValue": "200003", 221 "UMask": "0x2", 222 "Unit": "cpu_atom" 223 }, 224 { 225 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", 226 "CollectPEBSRecord": "2", 227 "Counter": "0,1,2,3,4,5", 228 "EventCode": "0x73", 229 "EventName": "TOPDOWN_BAD_SPECULATION.ALL", 230 "PEBScounters": "0,1,2,3,4,5", 231 "SampleAfterValue": "1000003", 232 "Unit": "cpu_atom" 233 }, 234 { 235 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", 236 "CollectPEBSRecord": "2", 237 "Counter": "0,1,2,3,4,5", 238 "EventCode": "0x73", 239 "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", 240 "PEBScounters": "0,1,2,3,4,5", 241 "SampleAfterValue": "1000003", 242 "UMask": "0x2", 243 "Unit": "cpu_atom" 244 }, 245 { 246 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", 247 "CollectPEBSRecord": "2", 248 "Counter": "0,1,2,3,4,5", 249 "EventCode": "0x73", 250 "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", 251 "PEBScounters": "0,1,2,3,4,5", 252 "SampleAfterValue": "1000003", 253 "UMask": "0x3", 254 "Unit": "cpu_atom" 255 }, 256 { 257 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", 258 "CollectPEBSRecord": "2", 259 "Counter": "0,1,2,3,4,5", 260 "EventCode": "0x73", 261 "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", 262 "PEBScounters": "0,1,2,3,4,5", 263 "SampleAfterValue": "1000003", 264 "UMask": "0x4", 265 "Unit": "cpu_atom" 266 }, 267 { 268 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", 269 "CollectPEBSRecord": "2", 270 "Counter": "0,1,2,3,4,5", 271 "EventCode": "0x73", 272 "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", 273 "PEBScounters": "0,1,2,3,4,5", 274 "SampleAfterValue": "1000003", 275 "UMask": "0x1", 276 "Unit": "cpu_atom" 277 }, 278 { 279 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", 280 "CollectPEBSRecord": "2", 281 "Counter": "0,1,2,3,4,5", 282 "EventCode": "0x74", 283 "EventName": "TOPDOWN_BE_BOUND.ALL", 284 "PEBScounters": "0,1,2,3,4,5", 285 "SampleAfterValue": "1000003", 286 "Unit": "cpu_atom" 287 }, 288 { 289 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", 290 "CollectPEBSRecord": "2", 291 "Counter": "0,1,2,3,4,5", 292 "EventCode": "0x74", 293 "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", 294 "PEBScounters": "0,1,2,3,4,5", 295 "SampleAfterValue": "1000003", 296 "UMask": "0x1", 297 "Unit": "cpu_atom" 298 }, 299 { 300 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", 301 "CollectPEBSRecord": "2", 302 "Counter": "0,1,2,3,4,5", 303 "EventCode": "0x74", 304 "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", 305 "PEBScounters": "0,1,2,3,4,5", 306 "SampleAfterValue": "1000003", 307 "UMask": "0x2", 308 "Unit": "cpu_atom" 309 }, 310 { 311 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", 312 "CollectPEBSRecord": "2", 313 "Counter": "0,1,2,3,4,5", 314 "EventCode": "0x74", 315 "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", 316 "PEBScounters": "0,1,2,3,4,5", 317 "SampleAfterValue": "1000003", 318 "UMask": "0x8", 319 "Unit": "cpu_atom" 320 }, 321 { 322 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", 323 "CollectPEBSRecord": "2", 324 "Counter": "0,1,2,3,4,5", 325 "EventCode": "0x74", 326 "EventName": "TOPDOWN_BE_BOUND.REGISTER", 327 "PEBScounters": "0,1,2,3,4,5", 328 "SampleAfterValue": "1000003", 329 "UMask": "0x20", 330 "Unit": "cpu_atom" 331 }, 332 { 333 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", 334 "CollectPEBSRecord": "2", 335 "Counter": "0,1,2,3,4,5", 336 "EventCode": "0x74", 337 "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", 338 "PEBScounters": "0,1,2,3,4,5", 339 "SampleAfterValue": "1000003", 340 "UMask": "0x40", 341 "Unit": "cpu_atom" 342 }, 343 { 344 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", 345 "CollectPEBSRecord": "2", 346 "Counter": "0,1,2,3,4,5", 347 "EventCode": "0x74", 348 "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", 349 "PEBScounters": "0,1,2,3,4,5", 350 "SampleAfterValue": "1000003", 351 "UMask": "0x10", 352 "Unit": "cpu_atom" 353 }, 354 { 355 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", 356 "CollectPEBSRecord": "2", 357 "Counter": "0,1,2,3,4,5", 358 "EventCode": "0x71", 359 "EventName": "TOPDOWN_FE_BOUND.ALL", 360 "PEBScounters": "0,1,2,3,4,5", 361 "SampleAfterValue": "1000003", 362 "Unit": "cpu_atom" 363 }, 364 { 365 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", 366 "CollectPEBSRecord": "2", 367 "Counter": "0,1,2,3,4,5", 368 "EventCode": "0x71", 369 "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", 370 "PEBScounters": "0,1,2,3,4,5", 371 "SampleAfterValue": "1000003", 372 "UMask": "0x2", 373 "Unit": "cpu_atom" 374 }, 375 { 376 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", 377 "CollectPEBSRecord": "2", 378 "Counter": "0,1,2,3,4,5", 379 "EventCode": "0x71", 380 "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", 381 "PEBScounters": "0,1,2,3,4,5", 382 "SampleAfterValue": "1000003", 383 "UMask": "0x40", 384 "Unit": "cpu_atom" 385 }, 386 { 387 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", 388 "CollectPEBSRecord": "2", 389 "Counter": "0,1,2,3,4,5", 390 "EventCode": "0x71", 391 "EventName": "TOPDOWN_FE_BOUND.CISC", 392 "PEBScounters": "0,1,2,3,4,5", 393 "SampleAfterValue": "1000003", 394 "UMask": "0x1", 395 "Unit": "cpu_atom" 396 }, 397 { 398 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", 399 "CollectPEBSRecord": "2", 400 "Counter": "0,1,2,3,4,5", 401 "EventCode": "0x71", 402 "EventName": "TOPDOWN_FE_BOUND.DECODE", 403 "PEBScounters": "0,1,2,3,4,5", 404 "SampleAfterValue": "1000003", 405 "UMask": "0x8", 406 "Unit": "cpu_atom" 407 }, 408 { 409 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", 410 "CollectPEBSRecord": "2", 411 "Counter": "0,1,2,3,4,5", 412 "EventCode": "0x71", 413 "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", 414 "PEBScounters": "0,1,2,3,4,5", 415 "SampleAfterValue": "1000003", 416 "UMask": "0x8d", 417 "Unit": "cpu_atom" 418 }, 419 { 420 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", 421 "CollectPEBSRecord": "2", 422 "Counter": "0,1,2,3,4,5", 423 "EventCode": "0x71", 424 "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", 425 "PEBScounters": "0,1,2,3,4,5", 426 "SampleAfterValue": "1000003", 427 "UMask": "0x72", 428 "Unit": "cpu_atom" 429 }, 430 { 431 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", 432 "CollectPEBSRecord": "2", 433 "Counter": "0,1,2,3,4,5", 434 "EventCode": "0x71", 435 "EventName": "TOPDOWN_FE_BOUND.ITLB", 436 "PEBScounters": "0,1,2,3,4,5", 437 "SampleAfterValue": "1000003", 438 "UMask": "0x10", 439 "Unit": "cpu_atom" 440 }, 441 { 442 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", 443 "CollectPEBSRecord": "2", 444 "Counter": "0,1,2,3,4,5", 445 "EventCode": "0x71", 446 "EventName": "TOPDOWN_FE_BOUND.OTHER", 447 "PEBScounters": "0,1,2,3,4,5", 448 "SampleAfterValue": "1000003", 449 "UMask": "0x80", 450 "Unit": "cpu_atom" 451 }, 452 { 453 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", 454 "CollectPEBSRecord": "2", 455 "Counter": "0,1,2,3,4,5", 456 "EventCode": "0x71", 457 "EventName": "TOPDOWN_FE_BOUND.PREDECODE", 458 "PEBScounters": "0,1,2,3,4,5", 459 "SampleAfterValue": "1000003", 460 "UMask": "0x4", 461 "Unit": "cpu_atom" 462 }, 463 { 464 "BriefDescription": "Counts the total number of consumed retirement slots.", 465 "CollectPEBSRecord": "2", 466 "Counter": "0,1,2,3,4,5", 467 "EventCode": "0xc2", 468 "EventName": "TOPDOWN_RETIRING.ALL", 469 "PEBS": "1", 470 "PEBScounters": "0,1,2,3,4,5", 471 "SampleAfterValue": "1000003", 472 "Unit": "cpu_atom" 473 }, 474 { 475 "BriefDescription": "Counts the total number of uops retired.", 476 "CollectPEBSRecord": "2", 477 "Counter": "0,1,2,3,4,5", 478 "EventCode": "0xc2", 479 "EventName": "UOPS_RETIRED.ALL", 480 "PEBS": "1", 481 "PEBScounters": "0,1,2,3,4,5", 482 "SampleAfterValue": "2000003", 483 "Unit": "cpu_atom" 484 }, 485 { 486 "BriefDescription": "Counts the number of integer divide uops retired.", 487 "CollectPEBSRecord": "2", 488 "Counter": "0,1,2,3,4,5", 489 "EventCode": "0xc2", 490 "EventName": "UOPS_RETIRED.IDIV", 491 "PEBS": "1", 492 "PEBScounters": "0,1,2,3,4,5", 493 "SampleAfterValue": "2000003", 494 "UMask": "0x10", 495 "Unit": "cpu_atom" 496 }, 497 { 498 "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", 499 "CollectPEBSRecord": "2", 500 "Counter": "0,1,2,3,4,5", 501 "EventCode": "0xc2", 502 "EventName": "UOPS_RETIRED.MS", 503 "PEBS": "1", 504 "PEBScounters": "0,1,2,3,4,5", 505 "SampleAfterValue": "2000003", 506 "UMask": "0x1", 507 "Unit": "cpu_atom" 508 }, 509 { 510 "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", 511 "CollectPEBSRecord": "2", 512 "Counter": "0,1,2,3,4,5", 513 "EventCode": "0xc2", 514 "EventName": "UOPS_RETIRED.X87", 515 "PEBS": "1", 516 "PEBScounters": "0,1,2,3,4,5", 517 "SampleAfterValue": "2000003", 518 "UMask": "0x2", 519 "Unit": "cpu_atom" 520 }, 521 { 522 "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", 523 "CollectPEBSRecord": "2", 524 "Counter": "0,1,2,3,4,5,6,7", 525 "CounterMask": "1", 526 "EventCode": "0xb0", 527 "EventName": "ARITH.DIVIDER_ACTIVE", 528 "PEBScounters": "0,1,2,3,4,5,6,7", 529 "SampleAfterValue": "1000003", 530 "UMask": "0x9", 531 "Unit": "cpu_core" 532 }, 533 { 534 "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", 535 "CollectPEBSRecord": "2", 536 "Counter": "0,1,2,3,4,5,6,7", 537 "CounterMask": "1", 538 "EventCode": "0xb0", 539 "EventName": "ARITH.DIV_ACTIVE", 540 "PEBScounters": "0,1,2,3,4,5,6,7", 541 "SampleAfterValue": "1000003", 542 "UMask": "0x9", 543 "Unit": "cpu_core" 544 }, 545 { 546 "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", 547 "CollectPEBSRecord": "2", 548 "Counter": "0,1,2,3,4,5,6,7", 549 "CounterMask": "1", 550 "EventCode": "0xb0", 551 "EventName": "ARITH.FP_DIVIDER_ACTIVE", 552 "PEBScounters": "0,1,2,3,4,5,6,7", 553 "SampleAfterValue": "1000003", 554 "UMask": "0x1", 555 "Unit": "cpu_core" 556 }, 557 { 558 "BriefDescription": "TBD", 559 "CollectPEBSRecord": "2", 560 "Counter": "0,1,2,3,4,5,6,7", 561 "CounterMask": "1", 562 "EventCode": "0xb0", 563 "EventName": "ARITH.INT_DIVIDER_ACTIVE", 564 "PEBScounters": "0,1,2,3,4,5,6,7", 565 "SampleAfterValue": "1000003", 566 "UMask": "0x8", 567 "Unit": "cpu_core" 568 }, 569 { 570 "BriefDescription": "All branch instructions retired.", 571 "CollectPEBSRecord": "2", 572 "Counter": "0,1,2,3,4,5,6,7", 573 "EventCode": "0xc4", 574 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 575 "PEBS": "1", 576 "PEBScounters": "0,1,2,3,4,5,6,7", 577 "SampleAfterValue": "400009", 578 "Unit": "cpu_core" 579 }, 580 { 581 "BriefDescription": "Conditional branch instructions retired.", 582 "CollectPEBSRecord": "2", 583 "Counter": "0,1,2,3,4,5,6,7", 584 "EventCode": "0xc4", 585 "EventName": "BR_INST_RETIRED.COND", 586 "PEBS": "1", 587 "PEBScounters": "0,1,2,3,4,5,6,7", 588 "SampleAfterValue": "400009", 589 "UMask": "0x11", 590 "Unit": "cpu_core" 591 }, 592 { 593 "BriefDescription": "Not taken branch instructions retired.", 594 "CollectPEBSRecord": "2", 595 "Counter": "0,1,2,3,4,5,6,7", 596 "EventCode": "0xc4", 597 "EventName": "BR_INST_RETIRED.COND_NTAKEN", 598 "PEBS": "1", 599 "PEBScounters": "0,1,2,3,4,5,6,7", 600 "SampleAfterValue": "400009", 601 "UMask": "0x10", 602 "Unit": "cpu_core" 603 }, 604 { 605 "BriefDescription": "Taken conditional branch instructions retired.", 606 "CollectPEBSRecord": "2", 607 "Counter": "0,1,2,3,4,5,6,7", 608 "EventCode": "0xc4", 609 "EventName": "BR_INST_RETIRED.COND_TAKEN", 610 "PEBS": "1", 611 "PEBScounters": "0,1,2,3,4,5,6,7", 612 "SampleAfterValue": "400009", 613 "UMask": "0x1", 614 "Unit": "cpu_core" 615 }, 616 { 617 "BriefDescription": "Far branch instructions retired.", 618 "CollectPEBSRecord": "2", 619 "Counter": "0,1,2,3,4,5,6,7", 620 "EventCode": "0xc4", 621 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 622 "PEBS": "1", 623 "PEBScounters": "0,1,2,3,4,5,6,7", 624 "SampleAfterValue": "100007", 625 "UMask": "0x40", 626 "Unit": "cpu_core" 627 }, 628 { 629 "BriefDescription": "Indirect near branch instructions retired (excluding returns)", 630 "CollectPEBSRecord": "2", 631 "Counter": "0,1,2,3,4,5,6,7", 632 "EventCode": "0xc4", 633 "EventName": "BR_INST_RETIRED.INDIRECT", 634 "PEBS": "1", 635 "PEBScounters": "0,1,2,3,4,5,6,7", 636 "SampleAfterValue": "100003", 637 "UMask": "0x80", 638 "Unit": "cpu_core" 639 }, 640 { 641 "BriefDescription": "Direct and indirect near call instructions retired.", 642 "CollectPEBSRecord": "2", 643 "Counter": "0,1,2,3,4,5,6,7", 644 "EventCode": "0xc4", 645 "EventName": "BR_INST_RETIRED.NEAR_CALL", 646 "PEBS": "1", 647 "PEBScounters": "0,1,2,3,4,5,6,7", 648 "SampleAfterValue": "100007", 649 "UMask": "0x2", 650 "Unit": "cpu_core" 651 }, 652 { 653 "BriefDescription": "Return instructions retired.", 654 "CollectPEBSRecord": "2", 655 "Counter": "0,1,2,3,4,5,6,7", 656 "EventCode": "0xc4", 657 "EventName": "BR_INST_RETIRED.NEAR_RETURN", 658 "PEBS": "1", 659 "PEBScounters": "0,1,2,3,4,5,6,7", 660 "SampleAfterValue": "100007", 661 "UMask": "0x8", 662 "Unit": "cpu_core" 663 }, 664 { 665 "BriefDescription": "Taken branch instructions retired.", 666 "CollectPEBSRecord": "2", 667 "Counter": "0,1,2,3,4,5,6,7", 668 "EventCode": "0xc4", 669 "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 670 "PEBS": "1", 671 "PEBScounters": "0,1,2,3,4,5,6,7", 672 "SampleAfterValue": "400009", 673 "UMask": "0x20", 674 "Unit": "cpu_core" 675 }, 676 { 677 "BriefDescription": "All mispredicted branch instructions retired.", 678 "CollectPEBSRecord": "2", 679 "Counter": "0,1,2,3,4,5,6,7", 680 "EventCode": "0xc5", 681 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 682 "PEBS": "1", 683 "PEBScounters": "0,1,2,3,4,5,6,7", 684 "SampleAfterValue": "400009", 685 "Unit": "cpu_core" 686 }, 687 { 688 "BriefDescription": "Mispredicted conditional branch instructions retired.", 689 "CollectPEBSRecord": "2", 690 "Counter": "0,1,2,3,4,5,6,7", 691 "EventCode": "0xc5", 692 "EventName": "BR_MISP_RETIRED.COND", 693 "PEBS": "1", 694 "PEBScounters": "0,1,2,3,4,5,6,7", 695 "SampleAfterValue": "400009", 696 "UMask": "0x11", 697 "Unit": "cpu_core" 698 }, 699 { 700 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 701 "CollectPEBSRecord": "2", 702 "Counter": "0,1,2,3,4,5,6,7", 703 "EventCode": "0xc5", 704 "EventName": "BR_MISP_RETIRED.COND_NTAKEN", 705 "PEBS": "1", 706 "PEBScounters": "0,1,2,3,4,5,6,7", 707 "SampleAfterValue": "400009", 708 "UMask": "0x10", 709 "Unit": "cpu_core" 710 }, 711 { 712 "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", 713 "CollectPEBSRecord": "2", 714 "Counter": "0,1,2,3,4,5,6,7", 715 "EventCode": "0xc5", 716 "EventName": "BR_MISP_RETIRED.COND_TAKEN", 717 "PEBS": "1", 718 "PEBScounters": "0,1,2,3,4,5,6,7", 719 "SampleAfterValue": "400009", 720 "UMask": "0x1", 721 "Unit": "cpu_core" 722 }, 723 { 724 "BriefDescription": "Mispredicted indirect CALL retired.", 725 "CollectPEBSRecord": "2", 726 "Counter": "0,1,2,3,4,5,6,7", 727 "EventCode": "0xc5", 728 "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", 729 "PEBS": "1", 730 "PEBScounters": "0,1,2,3,4,5,6,7", 731 "SampleAfterValue": "400009", 732 "UMask": "0x2", 733 "Unit": "cpu_core" 734 }, 735 { 736 "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", 737 "CollectPEBSRecord": "2", 738 "Counter": "0,1,2,3,4,5,6,7", 739 "EventCode": "0xc5", 740 "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 741 "PEBS": "1", 742 "PEBScounters": "0,1,2,3,4,5,6,7", 743 "SampleAfterValue": "400009", 744 "UMask": "0x20", 745 "Unit": "cpu_core" 746 }, 747 { 748 "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", 749 "CollectPEBSRecord": "2", 750 "Counter": "0,1,2,3,4,5,6,7", 751 "EventCode": "0xc5", 752 "EventName": "BR_MISP_RETIRED.RET", 753 "PEBS": "1", 754 "PEBScounters": "0,1,2,3,4,5,6,7", 755 "SampleAfterValue": "100007", 756 "UMask": "0x8", 757 "Unit": "cpu_core" 758 }, 759 { 760 "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", 761 "CollectPEBSRecord": "2", 762 "Counter": "0,1,2,3,4,5,6,7", 763 "EventCode": "0xec", 764 "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", 765 "PEBScounters": "0,1,2,3,4,5,6,7", 766 "SampleAfterValue": "2000003", 767 "UMask": "0x2", 768 "Unit": "cpu_core" 769 }, 770 { 771 "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 772 "CollectPEBSRecord": "2", 773 "Counter": "0,1,2,3,4,5,6,7", 774 "EventCode": "0x3c", 775 "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 776 "PEBScounters": "0,1,2,3,4,5,6,7", 777 "SampleAfterValue": "25003", 778 "UMask": "0x2", 779 "Unit": "cpu_core" 780 }, 781 { 782 "BriefDescription": "TBD", 783 "CollectPEBSRecord": "2", 784 "Counter": "0,1,2,3,4,5,6,7", 785 "EventCode": "0xec", 786 "EventName": "CPU_CLK_UNHALTED.PAUSE", 787 "PEBScounters": "0,1,2,3,4,5,6,7", 788 "SampleAfterValue": "2000003", 789 "UMask": "0x40", 790 "Unit": "cpu_core" 791 }, 792 { 793 "BriefDescription": "TBD", 794 "Counter": "0,1,2,3,4,5,6,7", 795 "CounterMask": "1", 796 "EdgeDetect": "1", 797 "EventCode": "0xec", 798 "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", 799 "PEBScounters": "0,1,2,3,4,5,6,7", 800 "SampleAfterValue": "2000003", 801 "UMask": "0x40", 802 "Unit": "cpu_core" 803 }, 804 { 805 "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", 806 "Counter": "0,1,2,3,4,5,6,7", 807 "EventCode": "0x3c", 808 "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", 809 "PEBScounters": "0,1,2,3,4,5,6,7", 810 "SampleAfterValue": "2000003", 811 "UMask": "0x8", 812 "Unit": "cpu_core" 813 }, 814 { 815 "BriefDescription": "Reference cycles when the core is not in halt state.", 816 "CollectPEBSRecord": "2", 817 "Counter": "34", 818 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 819 "PEBScounters": "34", 820 "SampleAfterValue": "2000003", 821 "UMask": "0x3", 822 "Unit": "cpu_core" 823 }, 824 { 825 "BriefDescription": "Core cycles when the thread is not in halt state", 826 "CollectPEBSRecord": "2", 827 "Counter": "33", 828 "EventName": "CPU_CLK_UNHALTED.THREAD", 829 "PEBScounters": "33", 830 "SampleAfterValue": "2000003", 831 "UMask": "0x2", 832 "Unit": "cpu_core" 833 }, 834 { 835 "BriefDescription": "Thread cycles when thread is not in halt state", 836 "CollectPEBSRecord": "2", 837 "Counter": "0,1,2,3,4,5,6,7", 838 "EventCode": "0x3c", 839 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 840 "PEBScounters": "0,1,2,3,4,5,6,7", 841 "SampleAfterValue": "2000003", 842 "Unit": "cpu_core" 843 }, 844 { 845 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 846 "CollectPEBSRecord": "2", 847 "Counter": "0,1,2,3", 848 "CounterMask": "8", 849 "EventCode": "0xa3", 850 "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 851 "PEBScounters": "0,1,2,3", 852 "SampleAfterValue": "1000003", 853 "UMask": "0x8", 854 "Unit": "cpu_core" 855 }, 856 { 857 "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", 858 "CollectPEBSRecord": "2", 859 "Counter": "0,1,2,3", 860 "CounterMask": "1", 861 "EventCode": "0xa3", 862 "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 863 "PEBScounters": "0,1,2,3", 864 "SampleAfterValue": "1000003", 865 "UMask": "0x1", 866 "Unit": "cpu_core" 867 }, 868 { 869 "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 870 "CollectPEBSRecord": "2", 871 "Counter": "0,1,2,3,4,5,6,7", 872 "CounterMask": "16", 873 "EventCode": "0xa3", 874 "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 875 "PEBScounters": "0,1,2,3,4,5,6,7", 876 "SampleAfterValue": "1000003", 877 "UMask": "0x10", 878 "Unit": "cpu_core" 879 }, 880 { 881 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 882 "CollectPEBSRecord": "2", 883 "Counter": "0,1,2,3", 884 "CounterMask": "12", 885 "EventCode": "0xa3", 886 "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 887 "PEBScounters": "0,1,2,3", 888 "SampleAfterValue": "1000003", 889 "UMask": "0xc", 890 "Unit": "cpu_core" 891 }, 892 { 893 "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", 894 "CollectPEBSRecord": "2", 895 "Counter": "0,1,2,3", 896 "CounterMask": "5", 897 "EventCode": "0xa3", 898 "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 899 "PEBScounters": "0,1,2,3", 900 "SampleAfterValue": "1000003", 901 "UMask": "0x5", 902 "Unit": "cpu_core" 903 }, 904 { 905 "BriefDescription": "Total execution stalls.", 906 "CollectPEBSRecord": "2", 907 "Counter": "0,1,2,3,4,5,6,7", 908 "CounterMask": "4", 909 "EventCode": "0xa3", 910 "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 911 "PEBScounters": "0,1,2,3,4,5,6,7", 912 "SampleAfterValue": "1000003", 913 "UMask": "0x4", 914 "Unit": "cpu_core" 915 }, 916 { 917 "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", 918 "CollectPEBSRecord": "2", 919 "Counter": "0,1,2,3,4,5,6,7", 920 "EventCode": "0xa6", 921 "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", 922 "PEBScounters": "0,1,2,3,4,5,6,7", 923 "SampleAfterValue": "2000003", 924 "UMask": "0x2", 925 "Unit": "cpu_core" 926 }, 927 { 928 "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", 929 "CollectPEBSRecord": "2", 930 "Counter": "0,1,2,3,4,5,6,7", 931 "EventCode": "0xa6", 932 "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", 933 "PEBScounters": "0,1,2,3,4,5,6,7", 934 "SampleAfterValue": "2000003", 935 "UMask": "0x4", 936 "Unit": "cpu_core" 937 }, 938 { 939 "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", 940 "CollectPEBSRecord": "2", 941 "Counter": "0,1,2,3,4,5,6,7", 942 "EventCode": "0xa6", 943 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", 944 "PEBScounters": "0,1,2,3,4,5,6,7", 945 "SampleAfterValue": "2000003", 946 "UMask": "0x8", 947 "Unit": "cpu_core" 948 }, 949 { 950 "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", 951 "CollectPEBSRecord": "2", 952 "Counter": "0,1,2,3,4,5,6,7", 953 "EventCode": "0xa6", 954 "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", 955 "PEBScounters": "0,1,2,3,4,5,6,7", 956 "SampleAfterValue": "2000003", 957 "UMask": "0x10", 958 "Unit": "cpu_core" 959 }, 960 { 961 "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 962 "CollectPEBSRecord": "2", 963 "Counter": "0,1,2,3,4,5,6,7", 964 "CounterMask": "5", 965 "EventCode": "0xa6", 966 "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", 967 "PEBScounters": "0,1,2,3,4,5,6,7", 968 "SampleAfterValue": "2000003", 969 "UMask": "0x21", 970 "Unit": "cpu_core" 971 }, 972 { 973 "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", 974 "CollectPEBSRecord": "2", 975 "Counter": "0,1,2,3,4,5,6,7", 976 "CounterMask": "2", 977 "EventCode": "0xa6", 978 "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", 979 "PEBScounters": "0,1,2,3,4,5,6,7", 980 "SampleAfterValue": "1000003", 981 "UMask": "0x40", 982 "Unit": "cpu_core" 983 }, 984 { 985 "BriefDescription": "Instruction decoders utilized in a cycle", 986 "CollectPEBSRecord": "2", 987 "Counter": "0,1,2,3", 988 "EventCode": "0x75", 989 "EventName": "INST_DECODED.DECODERS", 990 "PEBScounters": "0,1,2,3", 991 "SampleAfterValue": "2000003", 992 "UMask": "0x1", 993 "Unit": "cpu_core" 994 }, 995 { 996 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 997 "CollectPEBSRecord": "2", 998 "Counter": "32", 999 "EventName": "INST_RETIRED.ANY", 1000 "PEBS": "1", 1001 "PEBScounters": "32", 1002 "SampleAfterValue": "2000003", 1003 "UMask": "0x1", 1004 "Unit": "cpu_core" 1005 }, 1006 { 1007 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 1008 "CollectPEBSRecord": "2", 1009 "Counter": "0,1,2,3,4,5,6,7", 1010 "EventCode": "0xc0", 1011 "EventName": "INST_RETIRED.ANY_P", 1012 "PEBS": "1", 1013 "PEBScounters": "1,2,3,4,5,6,7", 1014 "SampleAfterValue": "2000003", 1015 "Unit": "cpu_core" 1016 }, 1017 { 1018 "BriefDescription": "TBD", 1019 "CollectPEBSRecord": "2", 1020 "Counter": "0,1,2,3,4,5,6,7", 1021 "EventCode": "0xc0", 1022 "EventName": "INST_RETIRED.MACRO_FUSED", 1023 "PEBScounters": "1,2,3,4,5,6,7", 1024 "SampleAfterValue": "2000003", 1025 "UMask": "0x10", 1026 "Unit": "cpu_core" 1027 }, 1028 { 1029 "BriefDescription": "Number of all retired NOP instructions.", 1030 "CollectPEBSRecord": "2", 1031 "Counter": "0,1,2,3,4,5,6,7", 1032 "EventCode": "0xc0", 1033 "EventName": "INST_RETIRED.NOP", 1034 "PEBScounters": "1,2,3,4,5,6,7", 1035 "SampleAfterValue": "2000003", 1036 "UMask": "0x2", 1037 "Unit": "cpu_core" 1038 }, 1039 { 1040 "BriefDescription": "Precise instruction retired with PEBS precise-distribution", 1041 "CollectPEBSRecord": "2", 1042 "Counter": "32", 1043 "EventName": "INST_RETIRED.PREC_DIST", 1044 "PEBS": "1", 1045 "PEBScounters": "32", 1046 "SampleAfterValue": "2000003", 1047 "UMask": "0x1", 1048 "Unit": "cpu_core" 1049 }, 1050 { 1051 "BriefDescription": "TBD", 1052 "CollectPEBSRecord": "2", 1053 "Counter": "0,1,2,3,4,5,6,7", 1054 "EventCode": "0xc0", 1055 "EventName": "INST_RETIRED.REP_ITERATION", 1056 "PEBScounters": "1,2,3,4,5,6,7", 1057 "SampleAfterValue": "2000003", 1058 "UMask": "0x8", 1059 "Unit": "cpu_core" 1060 }, 1061 { 1062 "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 1063 "CollectPEBSRecord": "2", 1064 "Counter": "0,1,2,3,4,5,6,7", 1065 "EventCode": "0xad", 1066 "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", 1067 "PEBScounters": "0,1,2,3,4,5,6,7", 1068 "SampleAfterValue": "500009", 1069 "UMask": "0x80", 1070 "Unit": "cpu_core" 1071 }, 1072 { 1073 "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", 1074 "CollectPEBSRecord": "2", 1075 "Counter": "0,1,2,3,4,5,6,7", 1076 "EventCode": "0xad", 1077 "EventName": "INT_MISC.RECOVERY_CYCLES", 1078 "PEBScounters": "0,1,2,3,4,5,6,7", 1079 "SampleAfterValue": "500009", 1080 "UMask": "0x1", 1081 "Unit": "cpu_core" 1082 }, 1083 { 1084 "BriefDescription": "TBD", 1085 "CollectPEBSRecord": "2", 1086 "Counter": "0,1,2,3,4,5,6,7", 1087 "EventCode": "0xad", 1088 "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", 1089 "MSRIndex": "0x3F7", 1090 "MSRValue": "0x7", 1091 "PEBScounters": "0,1,2,3,4,5,6,7", 1092 "SampleAfterValue": "1000003", 1093 "TakenAlone": "1", 1094 "UMask": "0x40", 1095 "Unit": "cpu_core" 1096 }, 1097 { 1098 "BriefDescription": "TMA slots where uops got dropped", 1099 "CollectPEBSRecord": "2", 1100 "Counter": "0,1,2,3,4,5,6,7", 1101 "EventCode": "0xad", 1102 "EventName": "INT_MISC.UOP_DROPPING", 1103 "PEBScounters": "0,1,2,3,4,5,6,7", 1104 "SampleAfterValue": "1000003", 1105 "UMask": "0x10", 1106 "Unit": "cpu_core" 1107 }, 1108 { 1109 "BriefDescription": "TBD", 1110 "CollectPEBSRecord": "2", 1111 "Counter": "0,1,2,3,4,5,6,7", 1112 "EventCode": "0xe7", 1113 "EventName": "INT_VEC_RETIRED.128BIT", 1114 "PEBScounters": "0,1,2,3,4,5,6,7", 1115 "SampleAfterValue": "1000003", 1116 "UMask": "0x13", 1117 "Unit": "cpu_core" 1118 }, 1119 { 1120 "BriefDescription": "TBD", 1121 "CollectPEBSRecord": "2", 1122 "Counter": "0,1,2,3,4,5,6,7", 1123 "EventCode": "0xe7", 1124 "EventName": "INT_VEC_RETIRED.256BIT", 1125 "PEBScounters": "0,1,2,3,4,5,6,7", 1126 "SampleAfterValue": "1000003", 1127 "UMask": "0xac", 1128 "Unit": "cpu_core" 1129 }, 1130 { 1131 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", 1132 "CollectPEBSRecord": "2", 1133 "Counter": "0,1,2,3,4,5,6,7", 1134 "EventCode": "0xe7", 1135 "EventName": "INT_VEC_RETIRED.ADD_128", 1136 "PEBScounters": "0,1,2,3,4,5,6,7", 1137 "SampleAfterValue": "1000003", 1138 "UMask": "0x3", 1139 "Unit": "cpu_core" 1140 }, 1141 { 1142 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", 1143 "CollectPEBSRecord": "2", 1144 "Counter": "0,1,2,3,4,5,6,7", 1145 "EventCode": "0xe7", 1146 "EventName": "INT_VEC_RETIRED.ADD_256", 1147 "PEBScounters": "0,1,2,3,4,5,6,7", 1148 "SampleAfterValue": "1000003", 1149 "UMask": "0xc", 1150 "Unit": "cpu_core" 1151 }, 1152 { 1153 "BriefDescription": "TBD", 1154 "CollectPEBSRecord": "2", 1155 "Counter": "0,1,2,3,4,5,6,7", 1156 "EventCode": "0xe7", 1157 "EventName": "INT_VEC_RETIRED.MUL_256", 1158 "PEBScounters": "0,1,2,3,4,5,6,7", 1159 "SampleAfterValue": "1000003", 1160 "UMask": "0x80", 1161 "Unit": "cpu_core" 1162 }, 1163 { 1164 "BriefDescription": "TBD", 1165 "CollectPEBSRecord": "2", 1166 "Counter": "0,1,2,3,4,5,6,7", 1167 "EventCode": "0xe7", 1168 "EventName": "INT_VEC_RETIRED.SHUFFLES", 1169 "PEBScounters": "0,1,2,3,4,5,6,7", 1170 "SampleAfterValue": "1000003", 1171 "UMask": "0x40", 1172 "Unit": "cpu_core" 1173 }, 1174 { 1175 "BriefDescription": "TBD", 1176 "CollectPEBSRecord": "2", 1177 "Counter": "0,1,2,3,4,5,6,7", 1178 "EventCode": "0xe7", 1179 "EventName": "INT_VEC_RETIRED.VNNI_128", 1180 "PEBScounters": "0,1,2,3,4,5,6,7", 1181 "SampleAfterValue": "1000003", 1182 "UMask": "0x10", 1183 "Unit": "cpu_core" 1184 }, 1185 { 1186 "BriefDescription": "TBD", 1187 "CollectPEBSRecord": "2", 1188 "Counter": "0,1,2,3,4,5,6,7", 1189 "EventCode": "0xe7", 1190 "EventName": "INT_VEC_RETIRED.VNNI_256", 1191 "PEBScounters": "0,1,2,3,4,5,6,7", 1192 "SampleAfterValue": "1000003", 1193 "UMask": "0x20", 1194 "Unit": "cpu_core" 1195 }, 1196 { 1197 "BriefDescription": "False dependencies in MOB due to partial compare on address.", 1198 "CollectPEBSRecord": "2", 1199 "Counter": "0,1,2,3", 1200 "EventCode": "0x03", 1201 "EventName": "LD_BLOCKS.ADDRESS_ALIAS", 1202 "PEBScounters": "0,1,2,3", 1203 "SampleAfterValue": "100003", 1204 "UMask": "0x4", 1205 "Unit": "cpu_core" 1206 }, 1207 { 1208 "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 1209 "CollectPEBSRecord": "2", 1210 "Counter": "0,1,2,3", 1211 "EventCode": "0x03", 1212 "EventName": "LD_BLOCKS.NO_SR", 1213 "PEBScounters": "0,1,2,3", 1214 "SampleAfterValue": "100003", 1215 "UMask": "0x88", 1216 "Unit": "cpu_core" 1217 }, 1218 { 1219 "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 1220 "CollectPEBSRecord": "2", 1221 "Counter": "0,1,2,3", 1222 "EventCode": "0x03", 1223 "EventName": "LD_BLOCKS.STORE_FORWARD", 1224 "PEBScounters": "0,1,2,3", 1225 "SampleAfterValue": "100003", 1226 "UMask": "0x82", 1227 "Unit": "cpu_core" 1228 }, 1229 { 1230 "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", 1231 "CollectPEBSRecord": "2", 1232 "Counter": "0,1,2,3", 1233 "EventCode": "0x4c", 1234 "EventName": "LOAD_HIT_PREFETCH.SWPF", 1235 "PEBScounters": "0,1,2,3", 1236 "SampleAfterValue": "100003", 1237 "UMask": "0x1", 1238 "Unit": "cpu_core" 1239 }, 1240 { 1241 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 1242 "CollectPEBSRecord": "2", 1243 "Counter": "0,1,2,3,4,5,6,7", 1244 "CounterMask": "1", 1245 "EventCode": "0xa8", 1246 "EventName": "LSD.CYCLES_ACTIVE", 1247 "PEBScounters": "0,1,2,3", 1248 "SampleAfterValue": "2000003", 1249 "UMask": "0x1", 1250 "Unit": "cpu_core" 1251 }, 1252 { 1253 "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", 1254 "CollectPEBSRecord": "2", 1255 "Counter": "0,1,2,3,4,5,6,7", 1256 "CounterMask": "6", 1257 "EventCode": "0xa8", 1258 "EventName": "LSD.CYCLES_OK", 1259 "PEBScounters": "0,1,2,3", 1260 "SampleAfterValue": "2000003", 1261 "UMask": "0x1", 1262 "Unit": "cpu_core" 1263 }, 1264 { 1265 "BriefDescription": "Number of Uops delivered by the LSD.", 1266 "CollectPEBSRecord": "2", 1267 "Counter": "0,1,2,3,4,5,6,7", 1268 "EventCode": "0xa8", 1269 "EventName": "LSD.UOPS", 1270 "PEBScounters": "0,1,2,3,4,5,6,7", 1271 "SampleAfterValue": "2000003", 1272 "UMask": "0x1", 1273 "Unit": "cpu_core" 1274 }, 1275 { 1276 "BriefDescription": "Number of machine clears (nukes) of any type.", 1277 "CollectPEBSRecord": "2", 1278 "Counter": "0,1,2,3,4,5,6,7", 1279 "CounterMask": "1", 1280 "EdgeDetect": "1", 1281 "EventCode": "0xc3", 1282 "EventName": "MACHINE_CLEARS.COUNT", 1283 "PEBScounters": "0,1,2,3,4,5,6,7", 1284 "SampleAfterValue": "100003", 1285 "UMask": "0x1", 1286 "Unit": "cpu_core" 1287 }, 1288 { 1289 "BriefDescription": "Self-modifying code (SMC) detected.", 1290 "CollectPEBSRecord": "2", 1291 "Counter": "0,1,2,3,4,5,6,7", 1292 "EventCode": "0xc3", 1293 "EventName": "MACHINE_CLEARS.SMC", 1294 "PEBScounters": "0,1,2,3,4,5,6,7", 1295 "SampleAfterValue": "100003", 1296 "UMask": "0x4", 1297 "Unit": "cpu_core" 1298 }, 1299 { 1300 "BriefDescription": "TBD", 1301 "CollectPEBSRecord": "2", 1302 "Counter": "0,1,2,3,4,5,6,7", 1303 "EventCode": "0xe0", 1304 "EventName": "MISC2_RETIRED.LFENCE", 1305 "PEBScounters": "0,1,2,3,4,5,6,7", 1306 "SampleAfterValue": "400009", 1307 "UMask": "0x20", 1308 "Unit": "cpu_core" 1309 }, 1310 { 1311 "BriefDescription": "Increments whenever there is an update to the LBR array.", 1312 "CollectPEBSRecord": "2", 1313 "Counter": "0,1,2,3,4,5,6,7", 1314 "EventCode": "0xcc", 1315 "EventName": "MISC_RETIRED.LBR_INSERTS", 1316 "PEBScounters": "0,1,2,3,4,5,6,7", 1317 "SampleAfterValue": "100003", 1318 "UMask": "0x20", 1319 "Unit": "cpu_core" 1320 }, 1321 { 1322 "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 1323 "CollectPEBSRecord": "2", 1324 "Counter": "0,1,2,3,4,5,6,7", 1325 "EventCode": "0xa2", 1326 "EventName": "RESOURCE_STALLS.SB", 1327 "PEBScounters": "0,1,2,3,4,5,6,7", 1328 "SampleAfterValue": "100003", 1329 "UMask": "0x8", 1330 "Unit": "cpu_core" 1331 }, 1332 { 1333 "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", 1334 "CollectPEBSRecord": "2", 1335 "Counter": "0,1,2,3,4,5,6,7", 1336 "EventCode": "0xa2", 1337 "EventName": "RESOURCE_STALLS.SCOREBOARD", 1338 "PEBScounters": "0,1,2,3,4,5,6,7", 1339 "SampleAfterValue": "100003", 1340 "UMask": "0x2", 1341 "Unit": "cpu_core" 1342 }, 1343 { 1344 "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", 1345 "CollectPEBSRecord": "2", 1346 "Counter": "0,1,2,3,4,5,6,7", 1347 "EventCode": "0xa4", 1348 "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", 1349 "PEBScounters": "0,1,2,3,4,5,6,7", 1350 "SampleAfterValue": "10000003", 1351 "UMask": "0x2", 1352 "Unit": "cpu_core" 1353 }, 1354 { 1355 "BriefDescription": "TMA slots wasted due to incorrect speculations.", 1356 "CollectPEBSRecord": "2", 1357 "EventCode": "0xa4", 1358 "EventName": "TOPDOWN.BAD_SPEC_SLOTS", 1359 "SampleAfterValue": "10000003", 1360 "UMask": "0x4", 1361 "Unit": "cpu_core" 1362 }, 1363 { 1364 "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 1365 "CollectPEBSRecord": "2", 1366 "EventCode": "0xa4", 1367 "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 1368 "SampleAfterValue": "10000003", 1369 "UMask": "0x8", 1370 "Unit": "cpu_core" 1371 }, 1372 { 1373 "BriefDescription": "TBD", 1374 "CollectPEBSRecord": "2", 1375 "Counter": "0,1,2,3,4,5,6,7", 1376 "EventCode": "0xa4", 1377 "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", 1378 "PEBScounters": "0,1,2,3,4,5,6,7", 1379 "SampleAfterValue": "10000003", 1380 "UMask": "0x10", 1381 "Unit": "cpu_core" 1382 }, 1383 { 1384 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", 1385 "CollectPEBSRecord": "2", 1386 "Counter": "35", 1387 "EventName": "TOPDOWN.SLOTS", 1388 "PEBScounters": "35", 1389 "SampleAfterValue": "10000003", 1390 "UMask": "0x4", 1391 "Unit": "cpu_core" 1392 }, 1393 { 1394 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", 1395 "CollectPEBSRecord": "2", 1396 "Counter": "0,1,2,3,4,5,6,7", 1397 "EventCode": "0xa4", 1398 "EventName": "TOPDOWN.SLOTS_P", 1399 "PEBScounters": "0,1,2,3,4,5,6,7", 1400 "SampleAfterValue": "10000003", 1401 "UMask": "0x1", 1402 "Unit": "cpu_core" 1403 }, 1404 { 1405 "BriefDescription": "TBD", 1406 "CollectPEBSRecord": "2", 1407 "Counter": "0,1,2,3", 1408 "EventCode": "0x76", 1409 "EventName": "UOPS_DECODED.DEC0_UOPS", 1410 "PEBScounters": "0,1,2,3", 1411 "SampleAfterValue": "1000003", 1412 "UMask": "0x1", 1413 "Unit": "cpu_core" 1414 }, 1415 { 1416 "BriefDescription": "Uops executed on port 0", 1417 "CollectPEBSRecord": "2", 1418 "Counter": "0,1,2,3,4,5,6,7", 1419 "EventCode": "0xb2", 1420 "EventName": "UOPS_DISPATCHED.PORT_0", 1421 "PEBScounters": "0,1,2,3,4,5,6,7", 1422 "SampleAfterValue": "2000003", 1423 "UMask": "0x1", 1424 "Unit": "cpu_core" 1425 }, 1426 { 1427 "BriefDescription": "Uops executed on port 1", 1428 "CollectPEBSRecord": "2", 1429 "Counter": "0,1,2,3,4,5,6,7", 1430 "EventCode": "0xb2", 1431 "EventName": "UOPS_DISPATCHED.PORT_1", 1432 "PEBScounters": "0,1,2,3,4,5,6,7", 1433 "SampleAfterValue": "2000003", 1434 "UMask": "0x2", 1435 "Unit": "cpu_core" 1436 }, 1437 { 1438 "BriefDescription": "Uops executed on ports 2, 3 and 10", 1439 "CollectPEBSRecord": "2", 1440 "Counter": "0,1,2,3,4,5,6,7", 1441 "EventCode": "0xb2", 1442 "EventName": "UOPS_DISPATCHED.PORT_2_3_10", 1443 "PEBScounters": "0,1,2,3,4,5,6,7", 1444 "SampleAfterValue": "2000003", 1445 "UMask": "0x4", 1446 "Unit": "cpu_core" 1447 }, 1448 { 1449 "BriefDescription": "Uops executed on ports 4 and 9", 1450 "CollectPEBSRecord": "2", 1451 "Counter": "0,1,2,3,4,5,6,7", 1452 "EventCode": "0xb2", 1453 "EventName": "UOPS_DISPATCHED.PORT_4_9", 1454 "PEBScounters": "0,1,2,3,4,5,6,7", 1455 "SampleAfterValue": "2000003", 1456 "UMask": "0x10", 1457 "Unit": "cpu_core" 1458 }, 1459 { 1460 "BriefDescription": "Uops executed on ports 5 and 11", 1461 "CollectPEBSRecord": "2", 1462 "Counter": "0,1,2,3,4,5,6,7", 1463 "EventCode": "0xb2", 1464 "EventName": "UOPS_DISPATCHED.PORT_5_11", 1465 "PEBScounters": "0,1,2,3,4,5,6,7", 1466 "SampleAfterValue": "2000003", 1467 "UMask": "0x20", 1468 "Unit": "cpu_core" 1469 }, 1470 { 1471 "BriefDescription": "Uops executed on port 6", 1472 "CollectPEBSRecord": "2", 1473 "Counter": "0,1,2,3,4,5,6,7", 1474 "EventCode": "0xb2", 1475 "EventName": "UOPS_DISPATCHED.PORT_6", 1476 "PEBScounters": "0,1,2,3,4,5,6,7", 1477 "SampleAfterValue": "2000003", 1478 "UMask": "0x40", 1479 "Unit": "cpu_core" 1480 }, 1481 { 1482 "BriefDescription": "Uops executed on ports 7 and 8", 1483 "CollectPEBSRecord": "2", 1484 "Counter": "0,1,2,3,4,5,6,7", 1485 "EventCode": "0xb2", 1486 "EventName": "UOPS_DISPATCHED.PORT_7_8", 1487 "PEBScounters": "0,1,2,3,4,5,6,7", 1488 "SampleAfterValue": "2000003", 1489 "UMask": "0x80", 1490 "Unit": "cpu_core" 1491 }, 1492 { 1493 "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 1494 "CollectPEBSRecord": "2", 1495 "Counter": "0,1,2,3,4,5,6,7", 1496 "CounterMask": "1", 1497 "EventCode": "0xb1", 1498 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 1499 "PEBScounters": "0,1,2,3,4,5,6,7", 1500 "SampleAfterValue": "2000003", 1501 "UMask": "0x2", 1502 "Unit": "cpu_core" 1503 }, 1504 { 1505 "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 1506 "CollectPEBSRecord": "2", 1507 "Counter": "0,1,2,3,4,5,6,7", 1508 "CounterMask": "2", 1509 "EventCode": "0xb1", 1510 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 1511 "PEBScounters": "0,1,2,3,4,5,6,7", 1512 "SampleAfterValue": "2000003", 1513 "UMask": "0x2", 1514 "Unit": "cpu_core" 1515 }, 1516 { 1517 "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 1518 "CollectPEBSRecord": "2", 1519 "Counter": "0,1,2,3,4,5,6,7", 1520 "CounterMask": "3", 1521 "EventCode": "0xb1", 1522 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 1523 "PEBScounters": "0,1,2,3,4,5,6,7", 1524 "SampleAfterValue": "2000003", 1525 "UMask": "0x2", 1526 "Unit": "cpu_core" 1527 }, 1528 { 1529 "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 1530 "CollectPEBSRecord": "2", 1531 "Counter": "0,1,2,3,4,5,6,7", 1532 "CounterMask": "4", 1533 "EventCode": "0xb1", 1534 "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 1535 "PEBScounters": "0,1,2,3,4,5,6,7", 1536 "SampleAfterValue": "2000003", 1537 "UMask": "0x2", 1538 "Unit": "cpu_core" 1539 }, 1540 { 1541 "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 1542 "CollectPEBSRecord": "2", 1543 "Counter": "0,1,2,3,4,5,6,7", 1544 "CounterMask": "1", 1545 "EventCode": "0xb1", 1546 "EventName": "UOPS_EXECUTED.CYCLES_GE_1", 1547 "PEBScounters": "0,1,2,3,4,5,6,7", 1548 "SampleAfterValue": "2000003", 1549 "UMask": "0x1", 1550 "Unit": "cpu_core" 1551 }, 1552 { 1553 "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 1554 "CollectPEBSRecord": "2", 1555 "Counter": "0,1,2,3,4,5,6,7", 1556 "CounterMask": "2", 1557 "EventCode": "0xb1", 1558 "EventName": "UOPS_EXECUTED.CYCLES_GE_2", 1559 "PEBScounters": "0,1,2,3,4,5,6,7", 1560 "SampleAfterValue": "2000003", 1561 "UMask": "0x1", 1562 "Unit": "cpu_core" 1563 }, 1564 { 1565 "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 1566 "CollectPEBSRecord": "2", 1567 "Counter": "0,1,2,3,4,5,6,7", 1568 "CounterMask": "3", 1569 "EventCode": "0xb1", 1570 "EventName": "UOPS_EXECUTED.CYCLES_GE_3", 1571 "PEBScounters": "0,1,2,3,4,5,6,7", 1572 "SampleAfterValue": "2000003", 1573 "UMask": "0x1", 1574 "Unit": "cpu_core" 1575 }, 1576 { 1577 "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 1578 "CollectPEBSRecord": "2", 1579 "Counter": "0,1,2,3,4,5,6,7", 1580 "CounterMask": "4", 1581 "EventCode": "0xb1", 1582 "EventName": "UOPS_EXECUTED.CYCLES_GE_4", 1583 "PEBScounters": "0,1,2,3,4,5,6,7", 1584 "SampleAfterValue": "2000003", 1585 "UMask": "0x1", 1586 "Unit": "cpu_core" 1587 }, 1588 { 1589 "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 1590 "CollectPEBSRecord": "2", 1591 "Counter": "0,1,2,3,4,5,6,7", 1592 "CounterMask": "1", 1593 "EventCode": "0xb1", 1594 "EventName": "UOPS_EXECUTED.STALLS", 1595 "Invert": "1", 1596 "PEBScounters": "0,1,2,3,4,5,6,7", 1597 "SampleAfterValue": "2000003", 1598 "UMask": "0x1", 1599 "Unit": "cpu_core" 1600 }, 1601 { 1602 "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", 1603 "CollectPEBSRecord": "2", 1604 "Counter": "0,1,2,3,4,5,6,7", 1605 "CounterMask": "1", 1606 "EventCode": "0xb1", 1607 "EventName": "UOPS_EXECUTED.STALL_CYCLES", 1608 "Invert": "1", 1609 "PEBScounters": "0,1,2,3,4,5,6,7", 1610 "SampleAfterValue": "2000003", 1611 "UMask": "0x1", 1612 "Unit": "cpu_core" 1613 }, 1614 { 1615 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 1616 "CollectPEBSRecord": "2", 1617 "Counter": "0,1,2,3,4,5,6,7", 1618 "EventCode": "0xb1", 1619 "EventName": "UOPS_EXECUTED.THREAD", 1620 "PEBScounters": "0,1,2,3,4,5,6,7", 1621 "SampleAfterValue": "2000003", 1622 "UMask": "0x1", 1623 "Unit": "cpu_core" 1624 }, 1625 { 1626 "BriefDescription": "Counts the number of x87 uops dispatched.", 1627 "CollectPEBSRecord": "2", 1628 "Counter": "0,1,2,3,4,5,6,7", 1629 "EventCode": "0xb1", 1630 "EventName": "UOPS_EXECUTED.X87", 1631 "PEBScounters": "0,1,2,3,4,5,6,7", 1632 "SampleAfterValue": "2000003", 1633 "UMask": "0x10", 1634 "Unit": "cpu_core" 1635 }, 1636 { 1637 "BriefDescription": "Uops that RAT issues to RS", 1638 "CollectPEBSRecord": "2", 1639 "Counter": "0,1,2,3,4,5,6,7", 1640 "EventCode": "0xae", 1641 "EventName": "UOPS_ISSUED.ANY", 1642 "PEBScounters": "0,1,2,3,4,5,6,7", 1643 "SampleAfterValue": "2000003", 1644 "UMask": "0x1", 1645 "Unit": "cpu_core" 1646 }, 1647 { 1648 "BriefDescription": "Cycles with retired uop(s).", 1649 "CollectPEBSRecord": "2", 1650 "Counter": "0,1,2,3,4,5,6,7", 1651 "CounterMask": "1", 1652 "EventCode": "0xc2", 1653 "EventName": "UOPS_RETIRED.CYCLES", 1654 "PEBScounters": "0,1,2,3,4,5,6,7", 1655 "SampleAfterValue": "1000003", 1656 "UMask": "0x2", 1657 "Unit": "cpu_core" 1658 }, 1659 { 1660 "BriefDescription": "TBD", 1661 "CollectPEBSRecord": "2", 1662 "Counter": "0,1,2,3,4,5,6,7", 1663 "EventCode": "0xc2", 1664 "EventName": "UOPS_RETIRED.HEAVY", 1665 "PEBScounters": "0,1,2,3,4,5,6,7", 1666 "SampleAfterValue": "2000003", 1667 "UMask": "0x1", 1668 "Unit": "cpu_core" 1669 }, 1670 { 1671 "BriefDescription": "TBD", 1672 "CollectPEBSRecord": "2", 1673 "Counter": "0,1,2,3,4,5,6,7", 1674 "EventCode": "0xc2", 1675 "EventName": "UOPS_RETIRED.MS", 1676 "MSRIndex": "0x3F7", 1677 "MSRValue": "0x8", 1678 "PEBScounters": "0,1,2,3,4,5,6,7", 1679 "SampleAfterValue": "2000003", 1680 "TakenAlone": "1", 1681 "UMask": "0x4", 1682 "Unit": "cpu_core" 1683 }, 1684 { 1685 "BriefDescription": "Retirement slots used.", 1686 "CollectPEBSRecord": "2", 1687 "Counter": "0,1,2,3,4,5,6,7", 1688 "EventCode": "0xc2", 1689 "EventName": "UOPS_RETIRED.SLOTS", 1690 "PEBScounters": "0,1,2,3,4,5,6,7", 1691 "SampleAfterValue": "2000003", 1692 "UMask": "0x2", 1693 "Unit": "cpu_core" 1694 }, 1695 { 1696 "BriefDescription": "Cycles without actually retired uops.", 1697 "CollectPEBSRecord": "2", 1698 "Counter": "0,1,2,3,4,5,6,7", 1699 "CounterMask": "1", 1700 "EventCode": "0xc2", 1701 "EventName": "UOPS_RETIRED.STALLS", 1702 "Invert": "1", 1703 "PEBScounters": "0,1,2,3,4,5,6,7", 1704 "SampleAfterValue": "1000003", 1705 "UMask": "0x2", 1706 "Unit": "cpu_core" 1707 }, 1708 { 1709 "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", 1710 "CollectPEBSRecord": "2", 1711 "Counter": "0,1,2,3,4,5,6,7", 1712 "CounterMask": "1", 1713 "EventCode": "0xc2", 1714 "EventName": "UOPS_RETIRED.STALL_CYCLES", 1715 "Invert": "1", 1716 "PEBScounters": "0,1,2,3,4,5,6,7", 1717 "SampleAfterValue": "1000003", 1718 "UMask": "0x2", 1719 "Unit": "cpu_core" 1720 } 1721]