1[ 2 { 3 "EventCode": "128", 4 "EventName": "DTLB1_MISSES", 5 "BriefDescription": "DTLB1 Misses", 6 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress." 7 }, 8 { 9 "EventCode": "129", 10 "EventName": "ITLB1_MISSES", 11 "BriefDescription": "ITLB1 Misses", 12 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress." 13 }, 14 { 15 "EventCode": "130", 16 "EventName": "L1D_L2I_SOURCED_WRITES", 17 "BriefDescription": "L1D L2I Sourced Writes", 18 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache" 19 }, 20 { 21 "EventCode": "131", 22 "EventName": "L1I_L2I_SOURCED_WRITES", 23 "BriefDescription": "L1I L2I Sourced Writes", 24 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" 25 }, 26 { 27 "EventCode": "132", 28 "EventName": "L1D_L2D_SOURCED_WRITES", 29 "BriefDescription": "L1D L2D Sourced Writes", 30 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" 31 }, 32 { 33 "EventCode": "133", 34 "EventName": "DTLB1_WRITES", 35 "BriefDescription": "DTLB1 Writes", 36 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" 37 }, 38 { 39 "EventCode": "135", 40 "EventName": "L1D_LMEM_SOURCED_WRITES", 41 "BriefDescription": "L1D Local Memory Sourced Writes", 42 "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" 43 }, 44 { 45 "EventCode": "137", 46 "EventName": "L1I_LMEM_SOURCED_WRITES", 47 "BriefDescription": "L1I Local Memory Sourced Writes", 48 "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)" 49 }, 50 { 51 "EventCode": "138", 52 "EventName": "L1D_RO_EXCL_WRITES", 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" 55 }, 56 { 57 "EventCode": "139", 58 "EventName": "DTLB1_HPAGE_WRITES", 59 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 60 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" 61 }, 62 { 63 "EventCode": "140", 64 "EventName": "ITLB1_WRITES", 65 "BriefDescription": "ITLB1 Writes", 66 "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" 67 }, 68 { 69 "EventCode": "141", 70 "EventName": "TLB2_PTE_WRITES", 71 "BriefDescription": "TLB2 PTE Writes", 72 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" 73 }, 74 { 75 "EventCode": "142", 76 "EventName": "TLB2_CRSTE_HPAGE_WRITES", 77 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", 78 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" 79 }, 80 { 81 "EventCode": "143", 82 "EventName": "TLB2_CRSTE_WRITES", 83 "BriefDescription": "TLB2 CRSTE Writes", 84 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" 85 }, 86 { 87 "EventCode": "144", 88 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", 89 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 90 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" 91 }, 92 { 93 "EventCode": "145", 94 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES", 95 "BriefDescription": "L1D Off-Chip L3 Sourced Writes", 96 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" 97 }, 98 { 99 "EventCode": "146", 100 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES", 101 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 102 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" 103 }, 104 { 105 "EventCode": "147", 106 "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES", 107 "BriefDescription": "L1D On-Book L4 Sourced Writes", 108 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache" 109 }, 110 { 111 "EventCode": "148", 112 "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES", 113 "BriefDescription": "L1D Off-Book L4 Sourced Writes", 114 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache" 115 }, 116 { 117 "EventCode": "149", 118 "EventName": "TX_NC_TEND", 119 "BriefDescription": "Completed TEND instructions in non-constrained TX mode", 120 "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode" 121 }, 122 { 123 "EventCode": "150", 124 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", 125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 126 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention" 127 }, 128 { 129 "EventCode": "151", 130 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV", 131 "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention", 132 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" 133 }, 134 { 135 "EventCode": "152", 136 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV", 137 "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention", 138 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" 139 }, 140 { 141 "EventCode": "153", 142 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", 143 "BriefDescription": "L1I On-Chip L3 Sourced Writes", 144 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" 145 }, 146 { 147 "EventCode": "154", 148 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES", 149 "BriefDescription": "L1I Off-Chip L3 Sourced Writes", 150 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" 151 }, 152 { 153 "EventCode": "155", 154 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES", 155 "BriefDescription": "L1I Off-Book L3 Sourced Writes", 156 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" 157 }, 158 { 159 "EventCode": "156", 160 "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES", 161 "BriefDescription": "L1I On-Book L4 Sourced Writes", 162 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache" 163 }, 164 { 165 "EventCode": "157", 166 "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES", 167 "BriefDescription": "L1I Off-Book L4 Sourced Writes", 168 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache" 169 }, 170 { 171 "EventCode": "158", 172 "EventName": "TX_C_TEND", 173 "BriefDescription": "Completed TEND instructions in constrained TX mode", 174 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" 175 }, 176 { 177 "EventCode": "159", 178 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", 179 "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", 180 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention" 181 }, 182 { 183 "EventCode": "160", 184 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV", 185 "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention", 186 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" 187 }, 188 { 189 "EventCode": "161", 190 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV", 191 "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention", 192 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" 193 }, 194 { 195 "EventCode": "177", 196 "EventName": "TX_NC_TABORT", 197 "BriefDescription": "Aborted transactions in non-constrained TX mode", 198 "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode" 199 }, 200 { 201 "EventCode": "178", 202 "EventName": "TX_C_TABORT_NO_SPECIAL", 203 "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", 204 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" 205 }, 206 { 207 "EventCode": "179", 208 "EventName": "TX_C_TABORT_SPECIAL", 209 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", 210 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" 211 }, 212] 213