1[ 2 { 3 "EventCode": "0x20036", 4 "EventName": "PM_BR_2PATH", 5 "BriefDescription": "Branches that are not strongly biased" 6 }, 7 { 8 "EventCode": "0x40056", 9 "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH", 10 "BriefDescription": "Local memory above threshold for LSU medium" 11 }, 12 { 13 "EventCode": "0x40118", 14 "EventName": "PM_MRK_DCACHE_RELOAD_INTV", 15 "BriefDescription": "Combined Intervention event" 16 }, 17 { 18 "EventCode": "0x4F148", 19 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD", 20 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 21 }, 22 { 23 "EventCode": "0x301E8", 24 "EventName": "PM_THRESH_EXC_64", 25 "BriefDescription": "Threshold counter exceeded a value of 64" 26 }, 27 { 28 "EventCode": "0x4E04E", 29 "EventName": "PM_DPTEG_FROM_L3MISS", 30 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 31 }, 32 { 33 "EventCode": "0x40050", 34 "EventName": "PM_SYS_PUMP_MPRED_RTY", 35 "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" 36 }, 37 { 38 "EventCode": "0x1F14E", 39 "EventName": "PM_MRK_DPTEG_FROM_L2MISS", 40 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 41 }, 42 { 43 "EventCode": "0x4D018", 44 "EventName": "PM_CMPLU_STALL_BRU", 45 "BriefDescription": "Completion stall due to a Branch Unit" 46 }, 47 { 48 "EventCode": "0x45052", 49 "EventName": "PM_4FLOP_CMPL", 50 "BriefDescription": "4 FLOP instruction completed" 51 }, 52 { 53 "EventCode": "0x3D142", 54 "EventName": "PM_MRK_DATA_FROM_LMEM", 55 "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load" 56 }, 57 { 58 "EventCode": "0x4C01E", 59 "EventName": "PM_CMPLU_STALL_CRYPTO", 60 "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish" 61 }, 62 { 63 "EventCode": "0x3000C", 64 "EventName": "PM_FREQ_DOWN", 65 "BriefDescription": "Power Management: Below Threshold B" 66 }, 67 { 68 "EventCode": "0x4D128", 69 "EventName": "PM_MRK_DATA_FROM_LMEM_CYC", 70 "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load" 71 }, 72 { 73 "EventCode": "0x4D054", 74 "EventName": "PM_8FLOP_CMPL", 75 "BriefDescription": "8 FLOP instruction completed" 76 }, 77 { 78 "EventCode": "0x10026", 79 "EventName": "PM_TABLEWALK_CYC", 80 "BriefDescription": "Cycles when an instruction tablewalk is active" 81 }, 82 { 83 "EventCode": "0x2C012", 84 "EventName": "PM_CMPLU_STALL_DCACHE_MISS", 85 "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest" 86 }, 87 { 88 "EventCode": "0x2E04C", 89 "EventName": "PM_DPTEG_FROM_MEMORY", 90 "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 91 }, 92 { 93 "EventCode": "0x3F142", 94 "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", 95 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 96 }, 97 { 98 "EventCode": "0x4F142", 99 "EventName": "PM_MRK_DPTEG_FROM_L3", 100 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 101 }, 102 { 103 "EventCode": "0x10060", 104 "EventName": "PM_TM_TRANS_RUN_CYC", 105 "BriefDescription": "run cycles in transactional state" 106 }, 107 { 108 "EventCode": "0x1E04C", 109 "EventName": "PM_DPTEG_FROM_LL4", 110 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" 111 }, 112 { 113 "EventCode": "0x45050", 114 "EventName": "PM_1FLOP_CMPL", 115 "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed" 116 } 117]