1*959826caSMatt Macy[ 2*959826caSMatt Macy {, 3*959826caSMatt Macy "EventCode": "0x1415A", 4*959826caSMatt Macy "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", 5*959826caSMatt Macy "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load" 6*959826caSMatt Macy }, 7*959826caSMatt Macy {, 8*959826caSMatt Macy "EventCode": "0x10058", 9*959826caSMatt Macy "EventName": "PM_MEM_LOC_THRESH_IFU", 10*959826caSMatt Macy "BriefDescription": "Local Memory above threshold for IFU speculation control" 11*959826caSMatt Macy }, 12*959826caSMatt Macy {, 13*959826caSMatt Macy "EventCode": "0x2D028", 14*959826caSMatt Macy "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", 15*959826caSMatt Macy "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache" 16*959826caSMatt Macy }, 17*959826caSMatt Macy {, 18*959826caSMatt Macy "EventCode": "0x30012", 19*959826caSMatt Macy "EventName": "PM_FLUSH_COMPLETION", 20*959826caSMatt Macy "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush" 21*959826caSMatt Macy }, 22*959826caSMatt Macy {, 23*959826caSMatt Macy "EventCode": "0x2D154", 24*959826caSMatt Macy "EventName": "PM_MRK_DERAT_MISS_64K", 25*959826caSMatt Macy "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K" 26*959826caSMatt Macy }, 27*959826caSMatt Macy {, 28*959826caSMatt Macy "EventCode": "0x4016E", 29*959826caSMatt Macy "EventName": "PM_THRESH_NOT_MET", 30*959826caSMatt Macy "BriefDescription": "Threshold counter did not meet threshold" 31*959826caSMatt Macy } 32*959826caSMatt Macy]