1959826caSMatt Macy[ 2*3a3deb00SEd Maste { 3959826caSMatt Macy "EventCode": "0x1415A", 4959826caSMatt Macy "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", 5959826caSMatt Macy "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load" 6959826caSMatt Macy }, 7*3a3deb00SEd Maste { 8959826caSMatt Macy "EventCode": "0x10058", 9959826caSMatt Macy "EventName": "PM_MEM_LOC_THRESH_IFU", 10959826caSMatt Macy "BriefDescription": "Local Memory above threshold for IFU speculation control" 11959826caSMatt Macy }, 12*3a3deb00SEd Maste { 13959826caSMatt Macy "EventCode": "0x2D028", 14959826caSMatt Macy "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", 15959826caSMatt Macy "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache" 16959826caSMatt Macy }, 17*3a3deb00SEd Maste { 18959826caSMatt Macy "EventCode": "0x30012", 19959826caSMatt Macy "EventName": "PM_FLUSH_COMPLETION", 20959826caSMatt Macy "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush" 21959826caSMatt Macy }, 22*3a3deb00SEd Maste { 23959826caSMatt Macy "EventCode": "0x2D154", 24959826caSMatt Macy "EventName": "PM_MRK_DERAT_MISS_64K", 25959826caSMatt Macy "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K" 26959826caSMatt Macy }, 27*3a3deb00SEd Maste { 28959826caSMatt Macy "EventCode": "0x4016E", 29959826caSMatt Macy "EventName": "PM_THRESH_NOT_MET", 30959826caSMatt Macy "BriefDescription": "Threshold counter did not meet threshold" 31959826caSMatt Macy } 32959826caSMatt Macy]