1[ 2 { 3 "EventCode": "0x3515e", 4 "EventName": "PM_MRK_BACK_BR_CMPL", 5 "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address", 6 "PublicDescription": "" 7 }, 8 { 9 "EventCode": "0x2013a", 10 "EventName": "PM_MRK_BRU_FIN", 11 "BriefDescription": "bru marked instr finish", 12 "PublicDescription": "" 13 }, 14 { 15 "EventCode": "0x1016e", 16 "EventName": "PM_MRK_BR_CMPL", 17 "BriefDescription": "Branch Instruction completed", 18 "PublicDescription": "" 19 }, 20 { 21 "EventCode": "0x301e4", 22 "EventName": "PM_MRK_BR_MPRED_CMPL", 23 "BriefDescription": "Marked Branch Mispredicted", 24 "PublicDescription": "" 25 }, 26 { 27 "EventCode": "0x101e2", 28 "EventName": "PM_MRK_BR_TAKEN_CMPL", 29 "BriefDescription": "Marked Branch Taken completed", 30 "PublicDescription": "" 31 }, 32 { 33 "EventCode": "0x4d148", 34 "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD", 35 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 36 "PublicDescription": "" 37 }, 38 { 39 "EventCode": "0x2d128", 40 "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", 41 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 42 "PublicDescription": "" 43 }, 44 { 45 "EventCode": "0x3d148", 46 "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR", 47 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 48 "PublicDescription": "" 49 }, 50 { 51 "EventCode": "0x2c128", 52 "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", 53 "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 54 "PublicDescription": "" 55 }, 56 { 57 "EventCode": "0x3d14c", 58 "EventName": "PM_MRK_DATA_FROM_DL4", 59 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", 60 "PublicDescription": "" 61 }, 62 { 63 "EventCode": "0x2c12c", 64 "EventName": "PM_MRK_DATA_FROM_DL4_CYC", 65 "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", 66 "PublicDescription": "" 67 }, 68 { 69 "EventCode": "0x4d14c", 70 "EventName": "PM_MRK_DATA_FROM_DMEM", 71 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", 72 "PublicDescription": "" 73 }, 74 { 75 "EventCode": "0x2d12c", 76 "EventName": "PM_MRK_DATA_FROM_DMEM_CYC", 77 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", 78 "PublicDescription": "" 79 }, 80 { 81 "EventCode": "0x1d142", 82 "EventName": "PM_MRK_DATA_FROM_L2", 83 "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load", 84 "PublicDescription": "" 85 }, 86 { 87 "EventCode": "0x1d14e", 88 "EventName": "PM_MRK_DATA_FROM_L2MISS", 89 "BriefDescription": "Data cache reload L2 miss", 90 "PublicDescription": "" 91 }, 92 { 93 "EventCode": "0x4c12e", 94 "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC", 95 "BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", 96 "PublicDescription": "" 97 }, 98 { 99 "EventCode": "0x4c122", 100 "EventName": "PM_MRK_DATA_FROM_L2_CYC", 101 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load", 102 "PublicDescription": "" 103 }, 104 { 105 "EventCode": "0x3d140", 106 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", 107 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", 108 "PublicDescription": "" 109 }, 110 { 111 "EventCode": "0x2c120", 112 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", 113 "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", 114 "PublicDescription": "" 115 }, 116 { 117 "EventCode": "0x4d140", 118 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", 119 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", 120 "PublicDescription": "" 121 }, 122 { 123 "EventCode": "0x2d120", 124 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", 125 "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", 126 "PublicDescription": "" 127 }, 128 { 129 "EventCode": "0x2d140", 130 "EventName": "PM_MRK_DATA_FROM_L2_MEPF", 131 "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", 132 "PublicDescription": "" 133 }, 134 { 135 "EventCode": "0x4d120", 136 "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC", 137 "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", 138 "PublicDescription": "" 139 }, 140 { 141 "EventCode": "0x1d140", 142 "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT", 143 "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", 144 "PublicDescription": "" 145 }, 146 { 147 "EventCode": "0x4c120", 148 "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", 149 "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load", 150 "PublicDescription": "" 151 }, 152 { 153 "EventCode": "0x4d142", 154 "EventName": "PM_MRK_DATA_FROM_L3", 155 "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load", 156 "PublicDescription": "" 157 }, 158 { 159 "EventCode": "0x201e4", 160 "EventName": "PM_MRK_DATA_FROM_L3MISS", 161 "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load", 162 "PublicDescription": "" 163 }, 164 { 165 "EventCode": "0x2d12e", 166 "EventName": "PM_MRK_DATA_FROM_L3MISS_CYC", 167 "BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load", 168 "PublicDescription": "" 169 }, 170 { 171 "EventCode": "0x2d122", 172 "EventName": "PM_MRK_DATA_FROM_L3_CYC", 173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", 174 "PublicDescription": "" 175 }, 176 { 177 "EventCode": "0x3d142", 178 "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", 179 "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", 180 "PublicDescription": "" 181 }, 182 { 183 "EventCode": "0x2c122", 184 "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", 185 "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", 186 "PublicDescription": "" 187 }, 188 { 189 "EventCode": "0x2d142", 190 "EventName": "PM_MRK_DATA_FROM_L3_MEPF", 191 "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", 192 "PublicDescription": "" 193 }, 194 { 195 "EventCode": "0x4d122", 196 "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC", 197 "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", 198 "PublicDescription": "" 199 }, 200 { 201 "EventCode": "0x1d144", 202 "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT", 203 "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", 204 "PublicDescription": "" 205 }, 206 { 207 "EventCode": "0x4c124", 208 "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", 209 "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load", 210 "PublicDescription": "" 211 }, 212 { 213 "EventCode": "0x1d14c", 214 "EventName": "PM_MRK_DATA_FROM_LL4", 215 "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", 216 "PublicDescription": "" 217 }, 218 { 219 "EventCode": "0x4c12c", 220 "EventName": "PM_MRK_DATA_FROM_LL4_CYC", 221 "BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load", 222 "PublicDescription": "" 223 }, 224 { 225 "EventCode": "0x2d148", 226 "EventName": "PM_MRK_DATA_FROM_LMEM", 227 "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load", 228 "PublicDescription": "" 229 }, 230 { 231 "EventCode": "0x4d128", 232 "EventName": "PM_MRK_DATA_FROM_LMEM_CYC", 233 "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load", 234 "PublicDescription": "" 235 }, 236 { 237 "EventCode": "0x2d14c", 238 "EventName": "PM_MRK_DATA_FROM_MEMORY", 239 "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", 240 "PublicDescription": "" 241 }, 242 { 243 "EventCode": "0x4d12c", 244 "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC", 245 "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", 246 "PublicDescription": "" 247 }, 248 { 249 "EventCode": "0x4d14a", 250 "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", 251 "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", 252 "PublicDescription": "" 253 }, 254 { 255 "EventCode": "0x2d12a", 256 "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", 257 "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", 258 "PublicDescription": "" 259 }, 260 { 261 "EventCode": "0x1d148", 262 "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE", 263 "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load", 264 "PublicDescription": "" 265 }, 266 { 267 "EventCode": "0x4c128", 268 "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", 269 "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", 270 "PublicDescription": "" 271 }, 272 { 273 "EventCode": "0x2d146", 274 "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD", 275 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", 276 "PublicDescription": "" 277 }, 278 { 279 "EventCode": "0x4d126", 280 "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", 281 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", 282 "PublicDescription": "" 283 }, 284 { 285 "EventCode": "0x1d14a", 286 "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR", 287 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", 288 "PublicDescription": "" 289 }, 290 { 291 "EventCode": "0x4c12a", 292 "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", 293 "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", 294 "PublicDescription": "" 295 }, 296 { 297 "EventCode": "0x2d14a", 298 "EventName": "PM_MRK_DATA_FROM_RL4", 299 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", 300 "PublicDescription": "" 301 }, 302 { 303 "EventCode": "0x4d12a", 304 "EventName": "PM_MRK_DATA_FROM_RL4_CYC", 305 "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", 306 "PublicDescription": "" 307 }, 308 { 309 "EventCode": "0x3d14a", 310 "EventName": "PM_MRK_DATA_FROM_RMEM", 311 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", 312 "PublicDescription": "" 313 }, 314 { 315 "EventCode": "0x2c12a", 316 "EventName": "PM_MRK_DATA_FROM_RMEM_CYC", 317 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", 318 "PublicDescription": "" 319 }, 320 { 321 "EventCode": "0x40118", 322 "EventName": "PM_MRK_DCACHE_RELOAD_INTV", 323 "BriefDescription": "Combined Intervention event", 324 "PublicDescription": "" 325 }, 326 { 327 "EventCode": "0x301e6", 328 "EventName": "PM_MRK_DERAT_MISS", 329 "BriefDescription": "Erat Miss (TLB Access) All page sizes", 330 "PublicDescription": "" 331 }, 332 { 333 "EventCode": "0x4d154", 334 "EventName": "PM_MRK_DERAT_MISS_16G", 335 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G", 336 "PublicDescription": "" 337 }, 338 { 339 "EventCode": "0x3d154", 340 "EventName": "PM_MRK_DERAT_MISS_16M", 341 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M", 342 "PublicDescription": "" 343 }, 344 { 345 "EventCode": "0x1d156", 346 "EventName": "PM_MRK_DERAT_MISS_4K", 347 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K", 348 "PublicDescription": "" 349 }, 350 { 351 "EventCode": "0x2d154", 352 "EventName": "PM_MRK_DERAT_MISS_64K", 353 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K", 354 "PublicDescription": "" 355 }, 356 { 357 "EventCode": "0x20132", 358 "EventName": "PM_MRK_DFU_FIN", 359 "BriefDescription": "Decimal Unit marked Instruction Finish", 360 "PublicDescription": "" 361 }, 362 { 363 "EventCode": "0x4f148", 364 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD", 365 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", 366 "PublicDescription": "" 367 }, 368 { 369 "EventCode": "0x3f148", 370 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR", 371 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", 372 "PublicDescription": "" 373 }, 374 { 375 "EventCode": "0x3f14c", 376 "EventName": "PM_MRK_DPTEG_FROM_DL4", 377 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request", 378 "PublicDescription": "" 379 }, 380 { 381 "EventCode": "0x4f14c", 382 "EventName": "PM_MRK_DPTEG_FROM_DMEM", 383 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request", 384 "PublicDescription": "" 385 }, 386 { 387 "EventCode": "0x1f142", 388 "EventName": "PM_MRK_DPTEG_FROM_L2", 389 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request", 390 "PublicDescription": "" 391 }, 392 { 393 "EventCode": "0x1f14e", 394 "EventName": "PM_MRK_DPTEG_FROM_L2MISS", 395 "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request", 396 "PublicDescription": "" 397 }, 398 { 399 "EventCode": "0x2f140", 400 "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF", 401 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request", 402 "PublicDescription": "" 403 }, 404 { 405 "EventCode": "0x1f140", 406 "EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT", 407 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request", 408 "PublicDescription": "" 409 }, 410 { 411 "EventCode": "0x4f142", 412 "EventName": "PM_MRK_DPTEG_FROM_L3", 413 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request", 414 "PublicDescription": "" 415 }, 416 { 417 "EventCode": "0x4f14e", 418 "EventName": "PM_MRK_DPTEG_FROM_L3MISS", 419 "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request", 420 "PublicDescription": "" 421 }, 422 { 423 "EventCode": "0x3f142", 424 "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", 425 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request", 426 "PublicDescription": "" 427 }, 428 { 429 "EventCode": "0x2f142", 430 "EventName": "PM_MRK_DPTEG_FROM_L3_MEPF", 431 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request", 432 "PublicDescription": "" 433 }, 434 { 435 "EventCode": "0x1f144", 436 "EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT", 437 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request", 438 "PublicDescription": "" 439 }, 440 { 441 "EventCode": "0x1f14c", 442 "EventName": "PM_MRK_DPTEG_FROM_LL4", 443 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request", 444 "PublicDescription": "" 445 }, 446 { 447 "EventCode": "0x2f148", 448 "EventName": "PM_MRK_DPTEG_FROM_LMEM", 449 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request", 450 "PublicDescription": "" 451 }, 452 { 453 "EventCode": "0x2f14c", 454 "EventName": "PM_MRK_DPTEG_FROM_MEMORY", 455 "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request", 456 "PublicDescription": "" 457 }, 458 { 459 "EventCode": "0x4f14a", 460 "EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE", 461 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request", 462 "PublicDescription": "" 463 }, 464 { 465 "EventCode": "0x1f148", 466 "EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE", 467 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request", 468 "PublicDescription": "" 469 }, 470 { 471 "EventCode": "0x2f146", 472 "EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD", 473 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", 474 "PublicDescription": "" 475 }, 476 { 477 "EventCode": "0x1f14a", 478 "EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR", 479 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request", 480 "PublicDescription": "" 481 }, 482 { 483 "EventCode": "0x2f14a", 484 "EventName": "PM_MRK_DPTEG_FROM_RL4", 485 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request", 486 "PublicDescription": "" 487 }, 488 { 489 "EventCode": "0x3f14a", 490 "EventName": "PM_MRK_DPTEG_FROM_RMEM", 491 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request", 492 "PublicDescription": "" 493 }, 494 { 495 "EventCode": "0x401e4", 496 "EventName": "PM_MRK_DTLB_MISS", 497 "BriefDescription": "Marked dtlb miss", 498 "PublicDescription": "" 499 }, 500 { 501 "EventCode": "0x1d158", 502 "EventName": "PM_MRK_DTLB_MISS_16G", 503 "BriefDescription": "Marked Data TLB Miss page size 16G", 504 "PublicDescription": "" 505 }, 506 { 507 "EventCode": "0x4d156", 508 "EventName": "PM_MRK_DTLB_MISS_16M", 509 "BriefDescription": "Marked Data TLB Miss page size 16M", 510 "PublicDescription": "" 511 }, 512 { 513 "EventCode": "0x2d156", 514 "EventName": "PM_MRK_DTLB_MISS_4K", 515 "BriefDescription": "Marked Data TLB Miss page size 4k", 516 "PublicDescription": "" 517 }, 518 { 519 "EventCode": "0x3d156", 520 "EventName": "PM_MRK_DTLB_MISS_64K", 521 "BriefDescription": "Marked Data TLB Miss page size 64K", 522 "PublicDescription": "" 523 }, 524 { 525 "EventCode": "0x40154", 526 "EventName": "PM_MRK_FAB_RSP_BKILL", 527 "BriefDescription": "Marked store had to do a bkill", 528 "PublicDescription": "" 529 }, 530 { 531 "EventCode": "0x2f150", 532 "EventName": "PM_MRK_FAB_RSP_BKILL_CYC", 533 "BriefDescription": "cycles L2 RC took for a bkill", 534 "PublicDescription": "" 535 }, 536 { 537 "EventCode": "0x3015e", 538 "EventName": "PM_MRK_FAB_RSP_CLAIM_RTY", 539 "BriefDescription": "Sampled store did a rwitm and got a rty", 540 "PublicDescription": "" 541 }, 542 { 543 "EventCode": "0x30154", 544 "EventName": "PM_MRK_FAB_RSP_DCLAIM", 545 "BriefDescription": "Marked store had to do a dclaim", 546 "PublicDescription": "" 547 }, 548 { 549 "EventCode": "0x2f152", 550 "EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC", 551 "BriefDescription": "cycles L2 RC took for a dclaim", 552 "PublicDescription": "" 553 }, 554 { 555 "EventCode": "0x4015e", 556 "EventName": "PM_MRK_FAB_RSP_RD_RTY", 557 "BriefDescription": "Sampled L2 reads retry count", 558 "PublicDescription": "" 559 }, 560 { 561 "EventCode": "0x1015e", 562 "EventName": "PM_MRK_FAB_RSP_RD_T_INTV", 563 "BriefDescription": "Sampled Read got a T intervention", 564 "PublicDescription": "" 565 }, 566 { 567 "EventCode": "0x4f150", 568 "EventName": "PM_MRK_FAB_RSP_RWITM_CYC", 569 "BriefDescription": "cycles L2 RC took for a rwitm", 570 "PublicDescription": "" 571 }, 572 { 573 "EventCode": "0x2015e", 574 "EventName": "PM_MRK_FAB_RSP_RWITM_RTY", 575 "BriefDescription": "Sampled store did a rwitm and got a rty", 576 "PublicDescription": "" 577 }, 578 { 579 "EventCode": "0x20134", 580 "EventName": "PM_MRK_FXU_FIN", 581 "BriefDescription": "fxu marked instr finish", 582 "PublicDescription": "" 583 }, 584 { 585 "EventCode": "0x401e0", 586 "EventName": "PM_MRK_INST_CMPL", 587 "BriefDescription": "marked instruction completed", 588 "PublicDescription": "" 589 }, 590 { 591 "EventCode": "0x20130", 592 "EventName": "PM_MRK_INST_DECODED", 593 "BriefDescription": "marked instruction decoded", 594 "PublicDescription": "marked instruction decoded. Name from ISU?" 595 }, 596 { 597 "EventCode": "0x101e0", 598 "EventName": "PM_MRK_INST_DISP", 599 "BriefDescription": "The thread has dispatched a randomly sampled marked instruction", 600 "PublicDescription": "Marked Instruction dispatched" 601 }, 602 { 603 "EventCode": "0x30130", 604 "EventName": "PM_MRK_INST_FIN", 605 "BriefDescription": "marked instruction finished", 606 "PublicDescription": "marked instr finish any unit" 607 }, 608 { 609 "EventCode": "0x401e6", 610 "EventName": "PM_MRK_INST_FROM_L3MISS", 611 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet", 612 "PublicDescription": "n/a" 613 }, 614 { 615 "EventCode": "0x10132", 616 "EventName": "PM_MRK_INST_ISSUED", 617 "BriefDescription": "Marked instruction issued", 618 "PublicDescription": "" 619 }, 620 { 621 "EventCode": "0x40134", 622 "EventName": "PM_MRK_INST_TIMEO", 623 "BriefDescription": "marked Instruction finish timeout (instruction lost)", 624 "PublicDescription": "" 625 }, 626 { 627 "EventCode": "0x101e4", 628 "EventName": "PM_MRK_L1_ICACHE_MISS", 629 "BriefDescription": "sampled Instruction suffered an icache Miss", 630 "PublicDescription": "Marked L1 Icache Miss" 631 }, 632 { 633 "EventCode": "0x101ea", 634 "EventName": "PM_MRK_L1_RELOAD_VALID", 635 "BriefDescription": "Marked demand reload", 636 "PublicDescription": "" 637 }, 638 { 639 "EventCode": "0x20114", 640 "EventName": "PM_MRK_L2_RC_DISP", 641 "BriefDescription": "Marked Instruction RC dispatched in L2", 642 "PublicDescription": "" 643 }, 644 { 645 "EventCode": "0x3012a", 646 "EventName": "PM_MRK_L2_RC_DONE", 647 "BriefDescription": "Marked RC done", 648 "PublicDescription": "" 649 }, 650 { 651 "EventCode": "0x40116", 652 "EventName": "PM_MRK_LARX_FIN", 653 "BriefDescription": "Larx finished", 654 "PublicDescription": "" 655 }, 656 { 657 "EventCode": "0x1013e", 658 "EventName": "PM_MRK_LD_MISS_EXPOSED_CYC", 659 "BriefDescription": "Marked Load exposed Miss cycles", 660 "PublicDescription": "Marked Load exposed Miss (use edge detect to count #)" 661 }, 662 { 663 "EventCode": "0x201e2", 664 "EventName": "PM_MRK_LD_MISS_L1", 665 "BriefDescription": "Marked DL1 Demand Miss counted at exec time", 666 "PublicDescription": "" 667 }, 668 { 669 "EventCode": "0x4013e", 670 "EventName": "PM_MRK_LD_MISS_L1_CYC", 671 "BriefDescription": "Marked ld latency", 672 "PublicDescription": "" 673 }, 674 { 675 "EventCode": "0x40132", 676 "EventName": "PM_MRK_LSU_FIN", 677 "BriefDescription": "lsu marked instr finish", 678 "PublicDescription": "" 679 }, 680 { 681 "EventCode": "0x20112", 682 "EventName": "PM_MRK_NTF_FIN", 683 "BriefDescription": "Marked next to finish instruction finished", 684 "PublicDescription": "" 685 }, 686 { 687 "EventCode": "0x1d15e", 688 "EventName": "PM_MRK_RUN_CYC", 689 "BriefDescription": "Marked run cycles", 690 "PublicDescription": "" 691 }, 692 { 693 "EventCode": "0x3013e", 694 "EventName": "PM_MRK_STALL_CMPLU_CYC", 695 "BriefDescription": "Marked Group completion Stall", 696 "PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)" 697 }, 698 { 699 "EventCode": "0x3e158", 700 "EventName": "PM_MRK_STCX_FAIL", 701 "BriefDescription": "marked stcx failed", 702 "PublicDescription": "" 703 }, 704 { 705 "EventCode": "0x10134", 706 "EventName": "PM_MRK_ST_CMPL", 707 "BriefDescription": "marked store completed and sent to nest", 708 "PublicDescription": "Marked store completed" 709 }, 710 { 711 "EventCode": "0x30134", 712 "EventName": "PM_MRK_ST_CMPL_INT", 713 "BriefDescription": "marked store finished with intervention", 714 "PublicDescription": "marked store complete (data home) with intervention" 715 }, 716 { 717 "EventCode": "0x3f150", 718 "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", 719 "BriefDescription": "cycles to drain st from core to L2", 720 "PublicDescription": "" 721 }, 722 { 723 "EventCode": "0x3012c", 724 "EventName": "PM_MRK_ST_FWD", 725 "BriefDescription": "Marked st forwards", 726 "PublicDescription": "" 727 }, 728 { 729 "EventCode": "0x1f150", 730 "EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC", 731 "BriefDescription": "cycles from L2 rc disp to l2 rc completion", 732 "PublicDescription": "" 733 }, 734 { 735 "EventCode": "0x20138", 736 "EventName": "PM_MRK_ST_NEST", 737 "BriefDescription": "Marked store sent to nest", 738 "PublicDescription": "" 739 }, 740 { 741 "EventCode": "0x30132", 742 "EventName": "PM_MRK_VSU_FIN", 743 "BriefDescription": "VSU marked instr finish", 744 "PublicDescription": "vsu (fpu) marked instr finish" 745 }, 746 { 747 "EventCode": "0x3d15e", 748 "EventName": "PM_MULT_MRK", 749 "BriefDescription": "mult marked instr", 750 "PublicDescription": "" 751 }, 752 { 753 "EventCode": "0x15152", 754 "EventName": "PM_SYNC_MRK_BR_LINK", 755 "BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt", 756 "PublicDescription": "" 757 }, 758 { 759 "EventCode": "0x1515c", 760 "EventName": "PM_SYNC_MRK_BR_MPRED", 761 "BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt", 762 "PublicDescription": "" 763 }, 764 { 765 "EventCode": "0x15156", 766 "EventName": "PM_SYNC_MRK_FX_DIVIDE", 767 "BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt", 768 "PublicDescription": "" 769 }, 770 { 771 "EventCode": "0x15158", 772 "EventName": "PM_SYNC_MRK_L2HIT", 773 "BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt", 774 "PublicDescription": "" 775 }, 776 { 777 "EventCode": "0x1515a", 778 "EventName": "PM_SYNC_MRK_L2MISS", 779 "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt", 780 "PublicDescription": "" 781 }, 782 { 783 "EventCode": "0x15154", 784 "EventName": "PM_SYNC_MRK_L3MISS", 785 "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt", 786 "PublicDescription": "" 787 }, 788 { 789 "EventCode": "0x15150", 790 "EventName": "PM_SYNC_MRK_PROBE_NOP", 791 "BriefDescription": "Marked probeNops which can cause synchronous interrupts", 792 "PublicDescription": "" 793 } 794] 795