xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/instruction.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84) 
1*9d97138eSMitchell Horne[
2*9d97138eSMitchell Horne  {
3*9d97138eSMitchell Horne    "ArchStdEvent": "SW_INCR"
4*9d97138eSMitchell Horne  },
5*9d97138eSMitchell Horne  {
6*9d97138eSMitchell Horne    "ArchStdEvent": "INST_RETIRED"
7*9d97138eSMitchell Horne  },
8*9d97138eSMitchell Horne  {
9*9d97138eSMitchell Horne    "ArchStdEvent": "EXC_RETURN"
10*9d97138eSMitchell Horne  },
11*9d97138eSMitchell Horne  {
12*9d97138eSMitchell Horne    "ArchStdEvent": "CID_WRITE_RETIRED"
13*9d97138eSMitchell Horne  },
14*9d97138eSMitchell Horne  {
15*9d97138eSMitchell Horne    "ArchStdEvent": "INST_SPEC"
16*9d97138eSMitchell Horne  },
17*9d97138eSMitchell Horne  {
18*9d97138eSMitchell Horne    "ArchStdEvent": "LDREX_SPEC"
19*9d97138eSMitchell Horne  },
20*9d97138eSMitchell Horne  {
21*9d97138eSMitchell Horne    "ArchStdEvent": "STREX_SPEC"
22*9d97138eSMitchell Horne  },
23*9d97138eSMitchell Horne  {
24*9d97138eSMitchell Horne    "ArchStdEvent": "LD_SPEC"
25*9d97138eSMitchell Horne  },
26*9d97138eSMitchell Horne  {
27*9d97138eSMitchell Horne    "ArchStdEvent": "ST_SPEC"
28*9d97138eSMitchell Horne  },
29*9d97138eSMitchell Horne  {
30*9d97138eSMitchell Horne    "ArchStdEvent": "LDST_SPEC"
31*9d97138eSMitchell Horne  },
32*9d97138eSMitchell Horne  {
33*9d97138eSMitchell Horne    "ArchStdEvent": "DP_SPEC"
34*9d97138eSMitchell Horne  },
35*9d97138eSMitchell Horne  {
36*9d97138eSMitchell Horne    "ArchStdEvent": "ASE_SPEC"
37*9d97138eSMitchell Horne  },
38*9d97138eSMitchell Horne  {
39*9d97138eSMitchell Horne    "ArchStdEvent": "VFP_SPEC"
40*9d97138eSMitchell Horne  },
41*9d97138eSMitchell Horne  {
42*9d97138eSMitchell Horne    "ArchStdEvent": "PC_WRITE_SPEC"
43*9d97138eSMitchell Horne  },
44*9d97138eSMitchell Horne  {
45*9d97138eSMitchell Horne    "ArchStdEvent": "CRYPTO_SPEC"
46*9d97138eSMitchell Horne  },
47*9d97138eSMitchell Horne  {
48*9d97138eSMitchell Horne    "ArchStdEvent": "BR_IMMED_SPEC"
49*9d97138eSMitchell Horne  },
50*9d97138eSMitchell Horne  {
51*9d97138eSMitchell Horne    "ArchStdEvent": "BR_RETURN_SPEC"
52*9d97138eSMitchell Horne  },
53*9d97138eSMitchell Horne  {
54*9d97138eSMitchell Horne    "ArchStdEvent": "BR_INDIRECT_SPEC"
55*9d97138eSMitchell Horne  },
56*9d97138eSMitchell Horne  {
57*9d97138eSMitchell Horne    "ArchStdEvent": "ISB_SPEC"
58*9d97138eSMitchell Horne  },
59*9d97138eSMitchell Horne  {
60*9d97138eSMitchell Horne    "ArchStdEvent": "DSB_SPEC"
61*9d97138eSMitchell Horne  },
62*9d97138eSMitchell Horne  {
63*9d97138eSMitchell Horne    "ArchStdEvent": "DMB_SPEC"
64*9d97138eSMitchell Horne  },
65*9d97138eSMitchell Horne  {
66*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.",
67*9d97138eSMitchell Horne    "EventCode": "0x9F",
68*9d97138eSMitchell Horne    "EventName": "DCZVA_SPEC",
69*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction."
70*9d97138eSMitchell Horne  },
71*9d97138eSMitchell Horne  {
72*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed floating-point move operations.",
73*9d97138eSMitchell Horne    "EventCode": "0x105",
74*9d97138eSMitchell Horne    "EventName": "FP_MV_SPEC",
75*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed floating-point move operations."
76*9d97138eSMitchell Horne  },
77*9d97138eSMitchell Horne  {
78*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed operations that using predicate register.",
79*9d97138eSMitchell Horne    "EventCode": "0x108",
80*9d97138eSMitchell Horne    "EventName": "PRD_SPEC",
81*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed operations that using predicate register."
82*9d97138eSMitchell Horne  },
83*9d97138eSMitchell Horne  {
84*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed inter-element manipulation operations.",
85*9d97138eSMitchell Horne    "EventCode": "0x109",
86*9d97138eSMitchell Horne    "EventName": "IEL_SPEC",
87*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed inter-element manipulation operations."
88*9d97138eSMitchell Horne  },
89*9d97138eSMitchell Horne  {
90*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed inter-register manipulation operations.",
91*9d97138eSMitchell Horne    "EventCode": "0x10A",
92*9d97138eSMitchell Horne    "EventName": "IREG_SPEC",
93*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed inter-register manipulation operations."
94*9d97138eSMitchell Horne  },
95*9d97138eSMitchell Horne  {
96*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.",
97*9d97138eSMitchell Horne    "EventCode": "0x112",
98*9d97138eSMitchell Horne    "EventName": "FP_LD_SPEC",
99*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers."
100*9d97138eSMitchell Horne  },
101*9d97138eSMitchell Horne  {
102*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.",
103*9d97138eSMitchell Horne    "EventCode": "0x113",
104*9d97138eSMitchell Horne    "EventName": "FP_ST_SPEC",
105*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers."
106*9d97138eSMitchell Horne  },
107*9d97138eSMitchell Horne  {
108*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.",
109*9d97138eSMitchell Horne    "EventCode": "0x11A",
110*9d97138eSMitchell Horne    "EventName": "BC_LD_SPEC",
111*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations."
112*9d97138eSMitchell Horne  },
113*9d97138eSMitchell Horne  {
114*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.",
115*9d97138eSMitchell Horne    "EventCode": "0x121",
116*9d97138eSMitchell Horne    "EventName": "EFFECTIVE_INST_SPEC",
117*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction."
118*9d97138eSMitchell Horne  },
119*9d97138eSMitchell Horne  {
120*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.",
121*9d97138eSMitchell Horne    "EventCode": "0x123",
122*9d97138eSMitchell Horne    "EventName": "PRE_INDEX_SPEC",
123*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode."
124*9d97138eSMitchell Horne  },
125*9d97138eSMitchell Horne  {
126*9d97138eSMitchell Horne    "PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.",
127*9d97138eSMitchell Horne    "EventCode": "0x124",
128*9d97138eSMitchell Horne    "EventName": "POST_INDEX_SPEC",
129*9d97138eSMitchell Horne    "BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode."
130*9d97138eSMitchell Horne  }
131*9d97138eSMitchell Horne]
132