xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1[
2    {
3        "ArchStdEvent": "SW_INCR"
4    },
5    {
6        "ArchStdEvent": "INST_RETIRED"
7    },
8    {
9        "ArchStdEvent": "EXC_RETURN"
10    },
11    {
12        "ArchStdEvent": "CID_WRITE_RETIRED"
13    },
14    {
15        "ArchStdEvent": "INST_SPEC"
16    },
17    {
18        "ArchStdEvent": "TTBR_WRITE_RETIRED"
19    },
20    {
21        "ArchStdEvent": "BR_RETIRED"
22    },
23    {
24        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
25    },
26    {
27        "ArchStdEvent": "OP_RETIRED"
28    },
29    {
30        "ArchStdEvent": "OP_SPEC"
31    },
32    {
33        "ArchStdEvent": "LDREX_SPEC"
34    },
35    {
36        "ArchStdEvent": "STREX_PASS_SPEC"
37    },
38    {
39        "ArchStdEvent": "STREX_FAIL_SPEC"
40    },
41    {
42        "ArchStdEvent": "STREX_SPEC"
43    },
44    {
45        "ArchStdEvent": "LD_SPEC"
46    },
47    {
48        "ArchStdEvent": "ST_SPEC"
49    },
50    {
51        "ArchStdEvent": "DP_SPEC"
52    },
53    {
54        "ArchStdEvent": "ASE_SPEC"
55    },
56    {
57        "ArchStdEvent": "VFP_SPEC"
58    },
59    {
60        "ArchStdEvent": "PC_WRITE_SPEC"
61    },
62    {
63        "ArchStdEvent": "CRYPTO_SPEC"
64    },
65    {
66        "ArchStdEvent": "BR_IMMED_SPEC"
67    },
68    {
69        "ArchStdEvent": "BR_RETURN_SPEC"
70    },
71    {
72        "ArchStdEvent": "BR_INDIRECT_SPEC"
73    },
74    {
75        "ArchStdEvent": "ISB_SPEC"
76    },
77    {
78        "ArchStdEvent": "DSB_SPEC"
79    },
80    {
81        "ArchStdEvent": "DMB_SPEC"
82    },
83    {
84        "ArchStdEvent": "RC_LD_SPEC"
85    },
86    {
87        "ArchStdEvent": "RC_ST_SPEC"
88    },
89    {
90        "ArchStdEvent": "ASE_INST_SPEC"
91    },
92    {
93        "ArchStdEvent": "SVE_INST_SPEC"
94    },
95    {
96        "ArchStdEvent": "FP_HP_SPEC"
97    },
98    {
99        "ArchStdEvent": "FP_SP_SPEC"
100    },
101    {
102        "ArchStdEvent": "FP_DP_SPEC"
103    },
104    {
105        "ArchStdEvent": "SVE_PRED_SPEC"
106    },
107    {
108        "ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
109    },
110    {
111        "ArchStdEvent": "SVE_PRED_FULL_SPEC"
112    },
113    {
114        "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
115    },
116    {
117        "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
118    },
119    {
120        "ArchStdEvent": "SVE_LDFF_SPEC"
121    },
122    {
123        "ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
124    },
125    {
126        "ArchStdEvent": "FP_SCALE_OPS_SPEC"
127    },
128    {
129        "ArchStdEvent": "FP_FIXED_OPS_SPEC"
130    },
131    {
132        "ArchStdEvent": "ASE_SVE_INT8_SPEC"
133    },
134    {
135        "ArchStdEvent": "ASE_SVE_INT16_SPEC"
136    },
137    {
138        "ArchStdEvent": "ASE_SVE_INT32_SPEC"
139    },
140    {
141        "ArchStdEvent": "ASE_SVE_INT64_SPEC"
142    }
143]
144