xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/neoverse-n2/instruction.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84) 
1*9d97138eSMitchell Horne[
2*9d97138eSMitchell Horne    {
3*9d97138eSMitchell Horne        "ArchStdEvent": "SW_INCR"
4*9d97138eSMitchell Horne    },
5*9d97138eSMitchell Horne    {
6*9d97138eSMitchell Horne        "ArchStdEvent": "INST_RETIRED"
7*9d97138eSMitchell Horne    },
8*9d97138eSMitchell Horne    {
9*9d97138eSMitchell Horne        "ArchStdEvent": "EXC_RETURN"
10*9d97138eSMitchell Horne    },
11*9d97138eSMitchell Horne    {
12*9d97138eSMitchell Horne        "ArchStdEvent": "CID_WRITE_RETIRED"
13*9d97138eSMitchell Horne    },
14*9d97138eSMitchell Horne    {
15*9d97138eSMitchell Horne        "ArchStdEvent": "INST_SPEC"
16*9d97138eSMitchell Horne    },
17*9d97138eSMitchell Horne    {
18*9d97138eSMitchell Horne        "ArchStdEvent": "TTBR_WRITE_RETIRED"
19*9d97138eSMitchell Horne    },
20*9d97138eSMitchell Horne    {
21*9d97138eSMitchell Horne        "ArchStdEvent": "BR_RETIRED"
22*9d97138eSMitchell Horne    },
23*9d97138eSMitchell Horne    {
24*9d97138eSMitchell Horne        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
25*9d97138eSMitchell Horne    },
26*9d97138eSMitchell Horne    {
27*9d97138eSMitchell Horne        "ArchStdEvent": "OP_RETIRED"
28*9d97138eSMitchell Horne    },
29*9d97138eSMitchell Horne    {
30*9d97138eSMitchell Horne        "ArchStdEvent": "OP_SPEC"
31*9d97138eSMitchell Horne    },
32*9d97138eSMitchell Horne    {
33*9d97138eSMitchell Horne        "ArchStdEvent": "LDREX_SPEC"
34*9d97138eSMitchell Horne    },
35*9d97138eSMitchell Horne    {
36*9d97138eSMitchell Horne        "ArchStdEvent": "STREX_PASS_SPEC"
37*9d97138eSMitchell Horne    },
38*9d97138eSMitchell Horne    {
39*9d97138eSMitchell Horne        "ArchStdEvent": "STREX_FAIL_SPEC"
40*9d97138eSMitchell Horne    },
41*9d97138eSMitchell Horne    {
42*9d97138eSMitchell Horne        "ArchStdEvent": "STREX_SPEC"
43*9d97138eSMitchell Horne    },
44*9d97138eSMitchell Horne    {
45*9d97138eSMitchell Horne        "ArchStdEvent": "LD_SPEC"
46*9d97138eSMitchell Horne    },
47*9d97138eSMitchell Horne    {
48*9d97138eSMitchell Horne        "ArchStdEvent": "ST_SPEC"
49*9d97138eSMitchell Horne    },
50*9d97138eSMitchell Horne    {
51*9d97138eSMitchell Horne        "ArchStdEvent": "DP_SPEC"
52*9d97138eSMitchell Horne    },
53*9d97138eSMitchell Horne    {
54*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_SPEC"
55*9d97138eSMitchell Horne    },
56*9d97138eSMitchell Horne    {
57*9d97138eSMitchell Horne        "ArchStdEvent": "VFP_SPEC"
58*9d97138eSMitchell Horne    },
59*9d97138eSMitchell Horne    {
60*9d97138eSMitchell Horne        "ArchStdEvent": "PC_WRITE_SPEC"
61*9d97138eSMitchell Horne    },
62*9d97138eSMitchell Horne    {
63*9d97138eSMitchell Horne        "ArchStdEvent": "CRYPTO_SPEC"
64*9d97138eSMitchell Horne    },
65*9d97138eSMitchell Horne    {
66*9d97138eSMitchell Horne        "ArchStdEvent": "BR_IMMED_SPEC"
67*9d97138eSMitchell Horne    },
68*9d97138eSMitchell Horne    {
69*9d97138eSMitchell Horne        "ArchStdEvent": "BR_RETURN_SPEC"
70*9d97138eSMitchell Horne    },
71*9d97138eSMitchell Horne    {
72*9d97138eSMitchell Horne        "ArchStdEvent": "BR_INDIRECT_SPEC"
73*9d97138eSMitchell Horne    },
74*9d97138eSMitchell Horne    {
75*9d97138eSMitchell Horne        "ArchStdEvent": "ISB_SPEC"
76*9d97138eSMitchell Horne    },
77*9d97138eSMitchell Horne    {
78*9d97138eSMitchell Horne        "ArchStdEvent": "DSB_SPEC"
79*9d97138eSMitchell Horne    },
80*9d97138eSMitchell Horne    {
81*9d97138eSMitchell Horne        "ArchStdEvent": "DMB_SPEC"
82*9d97138eSMitchell Horne    },
83*9d97138eSMitchell Horne    {
84*9d97138eSMitchell Horne        "ArchStdEvent": "RC_LD_SPEC"
85*9d97138eSMitchell Horne    },
86*9d97138eSMitchell Horne    {
87*9d97138eSMitchell Horne        "ArchStdEvent": "RC_ST_SPEC"
88*9d97138eSMitchell Horne    },
89*9d97138eSMitchell Horne    {
90*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_INST_SPEC"
91*9d97138eSMitchell Horne    },
92*9d97138eSMitchell Horne    {
93*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_INST_SPEC"
94*9d97138eSMitchell Horne    },
95*9d97138eSMitchell Horne    {
96*9d97138eSMitchell Horne        "ArchStdEvent": "FP_HP_SPEC"
97*9d97138eSMitchell Horne    },
98*9d97138eSMitchell Horne    {
99*9d97138eSMitchell Horne        "ArchStdEvent": "FP_SP_SPEC"
100*9d97138eSMitchell Horne    },
101*9d97138eSMitchell Horne    {
102*9d97138eSMitchell Horne        "ArchStdEvent": "FP_DP_SPEC"
103*9d97138eSMitchell Horne    },
104*9d97138eSMitchell Horne    {
105*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_PRED_SPEC"
106*9d97138eSMitchell Horne    },
107*9d97138eSMitchell Horne    {
108*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_PRED_EMPTY_SPEC"
109*9d97138eSMitchell Horne    },
110*9d97138eSMitchell Horne    {
111*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_PRED_FULL_SPEC"
112*9d97138eSMitchell Horne    },
113*9d97138eSMitchell Horne    {
114*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC"
115*9d97138eSMitchell Horne    },
116*9d97138eSMitchell Horne    {
117*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC"
118*9d97138eSMitchell Horne    },
119*9d97138eSMitchell Horne    {
120*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_LDFF_SPEC"
121*9d97138eSMitchell Horne    },
122*9d97138eSMitchell Horne    {
123*9d97138eSMitchell Horne        "ArchStdEvent": "SVE_LDFF_FAULT_SPEC"
124*9d97138eSMitchell Horne    },
125*9d97138eSMitchell Horne    {
126*9d97138eSMitchell Horne        "ArchStdEvent": "FP_SCALE_OPS_SPEC"
127*9d97138eSMitchell Horne    },
128*9d97138eSMitchell Horne    {
129*9d97138eSMitchell Horne        "ArchStdEvent": "FP_FIXED_OPS_SPEC"
130*9d97138eSMitchell Horne    },
131*9d97138eSMitchell Horne    {
132*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_SVE_INT8_SPEC"
133*9d97138eSMitchell Horne    },
134*9d97138eSMitchell Horne    {
135*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_SVE_INT16_SPEC"
136*9d97138eSMitchell Horne    },
137*9d97138eSMitchell Horne    {
138*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_SVE_INT32_SPEC"
139*9d97138eSMitchell Horne    },
140*9d97138eSMitchell Horne    {
141*9d97138eSMitchell Horne        "ArchStdEvent": "ASE_SVE_INT64_SPEC"
142*9d97138eSMitchell Horne    }
143*9d97138eSMitchell Horne]
144