xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/neoverse-n2/cache.json (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e) 
1[
2    {
3        "ArchStdEvent": "L1I_CACHE_REFILL"
4    },
5    {
6        "ArchStdEvent": "L1I_TLB_REFILL"
7    },
8    {
9        "ArchStdEvent": "L1D_CACHE_REFILL"
10    },
11    {
12        "ArchStdEvent": "L1D_CACHE"
13    },
14    {
15        "ArchStdEvent": "L1D_TLB_REFILL"
16    },
17    {
18        "ArchStdEvent": "L1I_CACHE"
19    },
20    {
21        "ArchStdEvent": "L1D_CACHE_WB"
22    },
23    {
24        "ArchStdEvent": "L2D_CACHE"
25    },
26    {
27        "ArchStdEvent": "L2D_CACHE_REFILL"
28    },
29    {
30        "ArchStdEvent": "L2D_CACHE_WB"
31    },
32    {
33        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
34    },
35    {
36        "ArchStdEvent": "L1D_TLB"
37    },
38    {
39        "ArchStdEvent": "L1I_TLB"
40    },
41    {
42        "ArchStdEvent": "L3D_CACHE_ALLOCATE"
43    },
44    {
45        "ArchStdEvent": "L3D_CACHE_REFILL"
46    },
47    {
48        "ArchStdEvent": "L3D_CACHE"
49    },
50    {
51        "ArchStdEvent": "L2D_TLB_REFILL"
52    },
53    {
54        "ArchStdEvent": "L2D_TLB"
55    },
56    {
57        "ArchStdEvent": "DTLB_WALK"
58    },
59    {
60        "ArchStdEvent": "ITLB_WALK"
61    },
62    {
63        "ArchStdEvent": "LL_CACHE_RD"
64    },
65    {
66        "ArchStdEvent": "LL_CACHE_MISS_RD"
67    },
68    {
69        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
70    },
71    {
72        "ArchStdEvent": "L1D_CACHE_RD"
73    },
74    {
75        "ArchStdEvent": "L1D_CACHE_WR"
76    },
77    {
78        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
79    },
80    {
81        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
82    },
83    {
84        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
85    },
86    {
87        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
88    },
89    {
90        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
91    },
92    {
93        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
94    },
95    {
96        "ArchStdEvent": "L1D_CACHE_INVAL"
97    },
98    {
99        "ArchStdEvent": "L1D_TLB_REFILL_RD"
100    },
101    {
102        "ArchStdEvent": "L1D_TLB_REFILL_WR"
103    },
104    {
105        "ArchStdEvent": "L1D_TLB_RD"
106    },
107    {
108        "ArchStdEvent": "L1D_TLB_WR"
109    },
110    {
111        "ArchStdEvent": "L2D_CACHE_RD"
112    },
113    {
114        "ArchStdEvent": "L2D_CACHE_WR"
115    },
116    {
117        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
118    },
119    {
120        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
121    },
122    {
123        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
124    },
125    {
126        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
127    },
128    {
129        "ArchStdEvent": "L2D_CACHE_INVAL"
130    },
131    {
132        "ArchStdEvent": "L2D_TLB_REFILL_RD"
133    },
134    {
135        "ArchStdEvent": "L2D_TLB_REFILL_WR"
136    },
137    {
138        "ArchStdEvent": "L2D_TLB_RD"
139    },
140    {
141        "ArchStdEvent": "L2D_TLB_WR"
142    },
143    {
144        "ArchStdEvent": "L3D_CACHE_RD"
145    },
146    {
147        "ArchStdEvent": "L1I_CACHE_LMISS"
148    },
149    {
150        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
151    },
152    {
153        "ArchStdEvent": "L3D_CACHE_LMISS_RD"
154    }
155]
156