xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/neoverse-e1/cache.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84) 
1*9d97138eSMitchell Horne[
2*9d97138eSMitchell Horne    {
3*9d97138eSMitchell Horne        "ArchStdEvent": "L1I_CACHE_REFILL"
4*9d97138eSMitchell Horne    },
5*9d97138eSMitchell Horne    {
6*9d97138eSMitchell Horne        "ArchStdEvent": "L1I_TLB_REFILL"
7*9d97138eSMitchell Horne    },
8*9d97138eSMitchell Horne    {
9*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_REFILL"
10*9d97138eSMitchell Horne    },
11*9d97138eSMitchell Horne    {
12*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE"
13*9d97138eSMitchell Horne    },
14*9d97138eSMitchell Horne    {
15*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_TLB_REFILL"
16*9d97138eSMitchell Horne    },
17*9d97138eSMitchell Horne    {
18*9d97138eSMitchell Horne        "ArchStdEvent": "L1I_CACHE"
19*9d97138eSMitchell Horne    },
20*9d97138eSMitchell Horne    {
21*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_WB"
22*9d97138eSMitchell Horne    },
23*9d97138eSMitchell Horne    {
24*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE"
25*9d97138eSMitchell Horne    },
26*9d97138eSMitchell Horne    {
27*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_REFILL"
28*9d97138eSMitchell Horne    },
29*9d97138eSMitchell Horne    {
30*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_WB"
31*9d97138eSMitchell Horne    },
32*9d97138eSMitchell Horne    {
33*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_ALLOCATE"
34*9d97138eSMitchell Horne    },
35*9d97138eSMitchell Horne    {
36*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
37*9d97138eSMitchell Horne    },
38*9d97138eSMitchell Horne    {
39*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_TLB"
40*9d97138eSMitchell Horne    },
41*9d97138eSMitchell Horne    {
42*9d97138eSMitchell Horne        "ArchStdEvent": "L1I_TLB"
43*9d97138eSMitchell Horne    },
44*9d97138eSMitchell Horne    {
45*9d97138eSMitchell Horne        "ArchStdEvent": "L3D_CACHE_ALLOCATE"
46*9d97138eSMitchell Horne    },
47*9d97138eSMitchell Horne    {
48*9d97138eSMitchell Horne        "ArchStdEvent": "L3D_CACHE_REFILL"
49*9d97138eSMitchell Horne    },
50*9d97138eSMitchell Horne    {
51*9d97138eSMitchell Horne        "ArchStdEvent": "L3D_CACHE"
52*9d97138eSMitchell Horne    },
53*9d97138eSMitchell Horne    {
54*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_TLB_REFILL"
55*9d97138eSMitchell Horne    },
56*9d97138eSMitchell Horne    {
57*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_TLB"
58*9d97138eSMitchell Horne    },
59*9d97138eSMitchell Horne    {
60*9d97138eSMitchell Horne        "ArchStdEvent": "DTLB_WALK"
61*9d97138eSMitchell Horne    },
62*9d97138eSMitchell Horne    {
63*9d97138eSMitchell Horne        "ArchStdEvent": "ITLB_WALK"
64*9d97138eSMitchell Horne    },
65*9d97138eSMitchell Horne    {
66*9d97138eSMitchell Horne        "ArchStdEvent": "LL_CACHE_RD"
67*9d97138eSMitchell Horne    },
68*9d97138eSMitchell Horne    {
69*9d97138eSMitchell Horne        "ArchStdEvent": "LL_CACHE_MISS_RD"
70*9d97138eSMitchell Horne    },
71*9d97138eSMitchell Horne    {
72*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_RD"
73*9d97138eSMitchell Horne    },
74*9d97138eSMitchell Horne    {
75*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_WR"
76*9d97138eSMitchell Horne    },
77*9d97138eSMitchell Horne    {
78*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
79*9d97138eSMitchell Horne    },
80*9d97138eSMitchell Horne    {
81*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
82*9d97138eSMitchell Horne    },
83*9d97138eSMitchell Horne    {
84*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
85*9d97138eSMitchell Horne    },
86*9d97138eSMitchell Horne    {
87*9d97138eSMitchell Horne        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
88*9d97138eSMitchell Horne    },
89*9d97138eSMitchell Horne    {
90*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_RD"
91*9d97138eSMitchell Horne    },
92*9d97138eSMitchell Horne    {
93*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_WR"
94*9d97138eSMitchell Horne    },
95*9d97138eSMitchell Horne    {
96*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
97*9d97138eSMitchell Horne    },
98*9d97138eSMitchell Horne    {
99*9d97138eSMitchell Horne        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
100*9d97138eSMitchell Horne    },
101*9d97138eSMitchell Horne    {
102*9d97138eSMitchell Horne        "ArchStdEvent": "L3D_CACHE_RD"
103*9d97138eSMitchell Horne    },
104*9d97138eSMitchell Horne    {
105*9d97138eSMitchell Horne        "ArchStdEvent": "L3D_CACHE_REFILL_RD"
106*9d97138eSMitchell Horne    }
107*9d97138eSMitchell Horne]
108