1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd March 24, 2010 25.Dt PMC.WESTMEREUC 3 26.Os 27.Sh NAME 28.Nm pmc.westmere 29.Nd uncore measurement events for 30.Tn Intel 31.Tn Westmere 32family CPUs 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn Intel 39.Tn "Westmere" 40CPUs contain PMCs conforming to version 2 of the 41.Tn Intel 42performance measurement architecture. 43These CPUs contain two classes of PMCs: 44.Bl -tag -width "Li PMC_CLASS_UCP" 45.It Li PMC_CLASS_UCF 46Fixed-function counters that count only one hardware event per counter. 47.It Li PMC_CLASS_UCP 48Programmable counters that may be configured to count one of a defined 49set of hardware events. 50.El 51.Pp 52The number of PMCs available in each class and their widths need to be 53determined at run time by calling 54.Xr pmc_cpuinfo 3 . 55.Pp 56Intel Westmere PMCs are documented in 57.Rs 58.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 59.%T "Volume 3B: System Programming Guide, Part 2" 60.%N "Order Number: 253669-033US" 61.%D December 2009 62.%Q "Intel Corporation" 63.Re 64.Ss WESTMERE UNCORE FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.ucf 3 . 67Not all CPUs in this family implement fixed-function counters. 68.Ss WESTMERE UNCORE PROGRAMMABLE PMCS 69The programmable PMCs support the following capabilities: 70.Bl -column "PMC_CAP_INTERRUPT" "Support" 71.It Em Capability Ta Em Support 72.It PMC_CAP_CASCADE Ta \&No 73.It PMC_CAP_EDGE Ta Yes 74.It PMC_CAP_INTERRUPT Ta \&No 75.It PMC_CAP_INVERT Ta Yes 76.It PMC_CAP_READ Ta Yes 77.It PMC_CAP_PRECISE Ta \&No 78.It PMC_CAP_SYSTEM Ta \&No 79.It PMC_CAP_TAGGING Ta \&No 80.It PMC_CAP_THRESHOLD Ta Yes 81.It PMC_CAP_USER Ta \&No 82.It PMC_CAP_WRITE Ta Yes 83.El 84.Ss Event Qualifiers 85Event specifiers for these PMCs support the following common 86qualifiers: 87.Bl -tag -width indent 88.It Li cmask= Ns Ar value 89Configure the PMC to increment only if the number of configured 90events measured in a cycle is greater than or equal to 91.Ar value . 92.It Li edge 93Configure the PMC to count the number of de-asserted to asserted 94transitions of the conditions expressed by the other qualifiers. 95If specified, the counter will increment only once whenever a 96condition becomes true, irrespective of the number of clocks during 97which the condition remains true. 98.It Li inv 99Invert the sense of comparison when the 100.Dq Li cmask 101qualifier is present, making the counter increment when the number of 102events per cycle is less than the value specified by the 103.Dq Li cmask 104qualifier. 105.El 106.Ss Event Specifiers (Programmable PMCs) 107Westmere uncore programmable PMCs support the following events: 108.Bl -tag -width indent 109.It Li GQ_CYCLES_FULL.READ_TRACKER 110.Pq Event 00H , Umask 01H 111Uncore cycles Global Queue read tracker is full. 112.It Li GQ_CYCLES_FULL.WRITE_TRACKER 113.Pq Event 00H , Umask 02H 114Uncore cycles Global Queue write tracker is full. 115.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER 116.Pq Event 00H , Umask 04H 117Uncore cycles Global Queue peer probe tracker is full. 118The peer probe tracker queue tracks snoops from the IOH and remote sockets. 119.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER 120.Pq Event 01H , Umask 01H 121Uncore cycles were Global Queue read tracker has at least one valid entry. 122.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER 123.Pq Event 01H , Umask 02H 124Uncore cycles were Global Queue write tracker has at least one valid entry. 125.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER 126.Pq Event 01H , Umask 04H 127Uncore cycles were Global Queue peer probe tracker has at least one valid entry. 128The peer probe tracker queue tracks IOH and remote socket snoops. 129.It Li GQ_OCCUPANCY.READ_TRACKER 130.Pq Event 02H , Umask 01H 131Increments the number of queue entries (code read, data read, and RFOs) in 132the tread tracker. 133The GQ read tracker allocate to deallocate occupancy count is divided by the 134count to obtain the average read tracker latency. 135.It Li GQ_ALLOC.READ_TRACKER 136.Pq Event 03H , Umask 01H 137Counts the number of tread tracker allocate to deallocate entries. 138The GQ read tracker allocate to deallocate occupancy count is divided by 139the count to obtain the average read tracker latency. 140.It Li GQ_ALLOC.RT_L3_MISS 141.Pq Event 03H , Umask 02H 142Counts the number GQ read tracker entries for which a full cache line read 143has missed the L3. 144The GQ read tracker L3 miss to fill occupancy count is divided by this count 145to obtain the average cache line read L3 miss latency. 146The latency represents the time after which the L3 has determined that the 147cache line has missed. 148The time between a GQ read tracker allocation and the L3 determining that 149the cache line has missed is the average L3 hit latency. 150The total L3 cache line read miss latency is the hit latency + L3 miss 151latency. 152.It Li GQ_ALLOC.RT_TO_L3_RESP 153.Pq Event 03H , Umask 04H 154Counts the number of GQ read tracker entries that are allocated in the read 155tracker queue that hit or miss the L3. 156The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit latency. 157.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED 158.Pq Event 03H , Umask 08H 159Counts the number of GQ read tracker entries that are allocated in the read 160tracker, have missed in the L3 and have not acquired a Request Transaction ID. 161The GQ read tracker L3 miss to RTID acquired occupancy count is 162divided by this count to obtain the average latency for a read L3 miss to 163acquire an RTID. 164.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED 165.Pq Event 03H , Umask 10H 166Counts the number of GQ write tracker entries that are allocated in the 167write tracker, have missed in the L3 and have not acquired a Request 168Transaction ID. 169The GQ write tracker L3 miss to RTID occupancy count is divided by this count 170to obtain the average latency for a write L3 miss to acquire an RTID. 171.It Li GQ_ALLOC.WRITE_TRACKER 172.Pq Event 03H , Umask 20H 173Counts the number of GQ write tracker entries that are allocated in the write 174tracker queue that miss the L3. 175The GQ write tracker occupancy count 176is divided by the this count to obtain the average L3 write miss latency. 177.It Li GQ_ALLOC.PEER_PROBE_TRACKER 178.Pq Event 03H , Umask 40H 179Counts the number of GQ peer probe tracker (snoop) entries that are 180allocated in the peer probe tracker queue that miss the L3. 181The GQ peer probe occupancy count is divided by this count to obtain the average 182L3 peer probe miss latency. 183.It Li GQ_DATA.FROM_QPI 184.Pq Event 04H , Umask 01H 185Cycles Global Queue Quickpath Interface input data port is busy importing 186data from the Quickpath Interface. 187Each cycle the input port can transfer 8 or 16 bytes of data. 188.It Li GQ_DATA.FROM_QMC 189.Pq Event 04H , Umask 02H 190Cycles Global Queue Quickpath Memory Interface input data port is busy 191importing data from the Quickpath Memory Interface. 192Each cycle the input port can transfer 8 or 16 bytes of data. 193.It Li GQ_DATA.FROM_L3 194.Pq Event 04H , Umask 04H 195Cycles GQ L3 input data port is busy importing data from the Last Level Cache. 196Each cycle the input port can transfer 32 bytes of data. 197.It Li GQ_DATA.FROM_CORES_02 198.Pq Event 04H , Umask 08H 199Cycles GQ Core 0 and 2 input data port is busy importing data from processor 200cores 0 and 2. 201Each cycle the input port can transfer 32 bytes of data. 202.It Li GQ_DATA.FROM_CORES_13 203.Pq Event 04H , Umask 10H 204Cycles GQ Core 1 and 3 input data port is busy importing data from processor 205cores 1 and 3. 206Each cycle the input port can transfer 32 bytes of data. 207.It Li GQ_DATA.TO_QPI_QMC 208.Pq Event 05H , Umask 01H 209Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath 210Interface or Quickpath Memory Interface. 211Each cycle the output port can transfer 32 bytes of data. 212.It Li GQ_DATA.TO_L3 213.Pq Event 05H , Umask 02H 214Cycles GQ L3 output data port is busy sending data to the Last Level Cache. 215Each cycle the output port can transfer 32 bytes of data. 216.It Li GQ_DATA.TO_CORES 217.Pq Event 05H , Umask 04H 218Cycles GQ Core output data port is busy sending data to the Cores. 219Each cycle the output port can transfer 32 bytes of data. 220.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE 221.Pq Event 06H , Umask 01H 222Number of snoop responses to the local home that L3 does not have the 223referenced cache line. 224.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE 225.Pq Event 06H , Umask 02H 226Number of snoop responses to the local home that L3 has the referenced line 227cached in the S state. 228.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE 229.Pq Event 06H , Umask 04H 230Number of responses to code or data read snoops to the local home that the 231L3 has the referenced cache line in the E state. 232The L3 cache line state is changed to the S state and the line is forwarded 233to the local home in the S state. 234.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE 235.Pq Event 06H , Umask 08H 236Number of responses to read invalidate snoops to the local home that the L3 237has the referenced cache line in the M state. 238The L3 cache line state is invalidated and the line is forwarded to the 239local home in the M state. 240.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT 241.Pq Event 06H , Umask 10H 242Number of conflict snoop responses sent to the local home. 243.It Li SNP_RESP_TO_LOCAL_HOME.WB 244.Pq Event 06H , Umask 20H 245Number of responses to code or data read snoops to the local home that the 246L3 has the referenced line cached in the M state. 247.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE 248.Pq Event 07H , Umask 01H 249Number of snoop responses to a remote home that L3 does not have the 250referenced cache line. 251.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE 252.Pq Event 07H , Umask 02H 253Number of snoop responses to a remote home that L3 has the referenced line 254cached in the S state. 255.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE 256.Pq Event 07H , Umask 04H 257Number of responses to code or data read snoops to a remote home that the L3 258has the referenced cache line in the E state. 259The L3 cache line state is changed to the S state and the line is forwarded 260to the remote home in the S state. 261.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE 262.Pq Event 07H , Umask 08H 263Number of responses to read invalidate snoops to a remote home that the L3 264has the referenced cache line in the M state. 265The L3 cache line state is invalidated and the line is forwarded to the 266remote home in the M state. 267.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT 268.Pq Event 07H , Umask 10H 269Number of conflict snoop responses sent to the local home. 270.It Li SNP_RESP_TO_REMOTE_HOME.WB 271.Pq Event 07H , Umask 20H 272Number of responses to code or data read snoops to a remote home that the L3 273has the referenced line cached in the M state. 274.It Li SNP_RESP_TO_REMOTE_HOME.HITM 275.Pq Event 07H , Umask 24H 276Number of HITM snoop responses to a remote home. 277.It Li L3_HITS.READ 278.Pq Event 08H , Umask 01H 279Number of code read, data read and RFO requests that hit in the L3. 280.It Li L3_HITS.WRITE 281.Pq Event 08H , Umask 02H 282Number of writeback requests that hit in the L3. 283Writebacks from the cores will always result in L3 hits due to the 284inclusive property of the L3. 285.It Li L3_HITS.PROBE 286.Pq Event 08H , Umask 04H 287Number of snoops from IOH or remote sockets that hit in the L3. 288.It Li L3_HITS.ANY 289.Pq Event 08H , Umask 03H 290Number of reads and writes that hit the L3. 291.It Li L3_MISS.READ 292.Pq Event 09H , Umask 01H 293Number of code read, data read and RFO requests that miss the L3. 294.It Li L3_MISS.WRITE 295.Pq Event 09H , Umask 02H 296Number of writeback requests that miss the L3. 297Should always be zero as writebacks from the cores will always result in L3 hits due to the inclusive 298property of the L3. 299.It Li L3_MISS.PROBE 300.Pq Event 09H , Umask 04H 301Number of snoops from IOH or remote sockets that miss the L3. 302.It Li L3_MISS.ANY 303.Pq Event 09H , Umask 03H 304Number of reads and writes that miss the L3. 305.It Li L3_LINES_IN.M_STATE 306.Pq Event 0AH , Umask 01H 307Counts the number of L3 lines allocated in M state. 308The only time a cache line is allocated in the M state is when the 309line was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. 310.It Li L3_LINES_IN.E_STATE 311.Pq Event 0AH , Umask 02H 312Counts the number of L3 lines allocated in E state. 313.It Li L3_LINES_IN.S_STATE 314.Pq Event 0AH , Umask 04H 315Counts the number of L3 lines allocated in S state. 316.It Li L3_LINES_IN.F_STATE 317.Pq Event 0AH , Umask 08H 318Counts the number of L3 lines allocated in F state. 319.It Li L3_LINES_IN.ANY 320.Pq Event 0AH , Umask 0FH 321Counts the number of L3 lines allocated in any state. 322.It Li L3_LINES_OUT.M_STATE 323.Pq Event 0BH , Umask 01H 324Counts the number of L3 lines victimized that were in the M state. 325When the victim cache line is in M state, the line is written to its home cache agent 326which can be either local or remote. 327.It Li L3_LINES_OUT.E_STATE 328.Pq Event 0BH , Umask 02H 329Counts the number of L3 lines victimized that were in the E state. 330.It Li L3_LINES_OUT.S_STATE 331.Pq Event 0BH , Umask 04H 332Counts the number of L3 lines victimized that were in the S state. 333.It Li L3_LINES_OUT.I_STATE 334.Pq Event 0BH , Umask 08H 335Counts the number of L3 lines victimized that were in the I state. 336.It Li L3_LINES_OUT.F_STATE 337.Pq Event 0BH , Umask 10H 338Counts the number of L3 lines victimized that were in the F state. 339.It Li L3_LINES_OUT.ANY 340.Pq Event 0BH , Umask 1FH 341Counts the number of L3 lines victimized in any state. 342.It Li GQ_SNOOP.GOTO_S 343.Pq Event 0CH , Umask 01H 344Counts the number of remote snoops that have requested a cache line be set 345to the S state. 346.It Li GQ_SNOOP.GOTO_I 347.Pq Event 0CH , Umask 02H 348Counts the number of remote snoops that have requested a cache line be set 349to the I state. 350.It Li GQ_SNOOP.GOTO_S_HIT_E 351.Pq Event 0CH , Umask 04H 352Counts the number of remote snoops that have requested a cache line be set 353to the S state from E state. 354Requires writing MSR 301H with mask = 2H 355.It Li GQ_SNOOP.GOTO_S_HIT_F 356.Pq Event 0CH , Umask 04H 357Counts the number of remote snoops that have requested a cache line be set 358to the S state from F (forward) state. 359Requires writing MSR 301H with mask = 8H 360.It Li GQ_SNOOP.GOTO_S_HIT_M 361.Pq Event 0CH , Umask 04H 362Counts the number of remote snoops that have requested a cache line be set 363to the S state from M state. 364Requires writing MSR 301H with mask = 1H 365.It Li GQ_SNOOP.GOTO_S_HIT_S 366.Pq Event 0CH , Umask 04H 367Counts the number of remote snoops that have requested a cache line be set 368to the S state from S state. 369Requires writing MSR 301H with mask = 4H 370.It Li GQ_SNOOP.GOTO_I_HIT_E 371.Pq Event 0CH , Umask 08H 372Counts the number of remote snoops that have requested a cache line be set 373to the I state from E state. 374Requires writing MSR 301H with mask = 2H 375.It Li GQ_SNOOP.GOTO_I_HIT_F 376.Pq Event 0CH , Umask 08H 377Counts the number of remote snoops that have requested a cache line be set 378to the I state from F (forward) state. 379Requires writing MSR 301H with mask = 8H 380.It Li GQ_SNOOP.GOTO_I_HIT_M 381.Pq Event 0CH , Umask 08H 382Counts the number of remote snoops that have requested a cache line be set 383to the I state from M state. 384Requires writing MSR 301H with mask = 1H 385.It Li GQ_SNOOP.GOTO_I_HIT_S 386.Pq Event 0CH , Umask 08H 387Counts the number of remote snoops that have requested a cache line be set 388to the I state from S state. 389Requires writing MSR 301H with mask = 4H 390.It Li QHL_REQUESTS.IOH_READS 391.Pq Event 20H , Umask 01H 392Counts number of Quickpath Home Logic read requests from the IOH. 393.It Li QHL_REQUESTS.IOH_WRITES 394.Pq Event 20H , Umask 02H 395Counts number of Quickpath Home Logic write requests from the IOH. 396.It Li QHL_REQUESTS.REMOTE_READS 397.Pq Event 20H , Umask 04H 398Counts number of Quickpath Home Logic read requests from a remote socket. 399.It Li QHL_REQUESTS.REMOTE_WRITES 400.Pq Event 20H , Umask 08H 401Counts number of Quickpath Home Logic write requests from a remote socket. 402.It Li QHL_REQUESTS.LOCAL_READS 403.Pq Event 20H , Umask 10H 404Counts number of Quickpath Home Logic read requests from the local socket. 405.It Li QHL_REQUESTS.LOCAL_WRITES 406.Pq Event 20H , Umask 20H 407Counts number of Quickpath Home Logic write requests from the local socket. 408.It Li QHL_CYCLES_FULL.IOH 409.Pq Event 21H , Umask 01H 410Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. 411.It Li QHL_CYCLES_FULL.REMOTE 412.Pq Event 21H , Umask 02H 413Counts uclk cycles all entries in the Quickpath Home Logic remote tracker 414are full. 415.It Li QHL_CYCLES_FULL.LOCAL 416.Pq Event 21H , Umask 04H 417Counts uclk cycles all entries in the Quickpath Home Logic local tracker are 418full. 419.It Li QHL_CYCLES_NOT_EMPTY.IOH 420.Pq Event 22H , Umask 01H 421Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. 422.It Li QHL_CYCLES_NOT_EMPTY.REMOTE 423.Pq Event 22H , Umask 02H 424Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is 425busy. 426.It Li QHL_CYCLES_NOT_EMPTY.LOCAL 427.Pq Event 22H , Umask 04H 428Counts uclk cycles all entries in the Quickpath Home Logic local tracker is 429busy. 430.It Li QHL_OCCUPANCY.IOH 431.Pq Event 23H , Umask 01H 432QHL IOH tracker allocate to deallocate read occupancy. 433.It Li QHL_OCCUPANCY.REMOTE 434.Pq Event 23H , Umask 02H 435QHL remote tracker allocate to deallocate read occupancy. 436.It Li QHL_OCCUPANCY.LOCAL 437.Pq Event 23H , Umask 04H 438QHL local tracker allocate to deallocate read occupancy. 439.It Li QHL_ADDRESS_CONFLICTS.2WAY 440.Pq Event 24H , Umask 02H 441Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 conflicts. 442The AAT is a structure that tracks requests that are in conflict. 443The requests themselves are in the home tracker entries. 444The count is reported when an AAT entry deallocates. 445.It Li QHL_ADDRESS_CONFLICTS.3WAY 446.Pq Event 24H , Umask 04H 447Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 conflicts. 448The AAT is a structure that tracks requests that are in conflict. 449The requests themselves are in the home tracker entries. 450The count is reported when an AAT entry deallocates. 451.It Li QHL_CONFLICT_CYCLES.IOH 452.Pq Event 25H , Umask 01H 453Counts cycles the Quickpath Home Logic IOH Tracker contains two or more 454requests with an address conflict. 455A max of 3 requests can be in conflict. 456.It Li QHL_CONFLICT_CYCLES.REMOTE 457.Pq Event 25H , Umask 02H 458Counts cycles the Quickpath Home Logic Remote Tracker contains two or more 459requests with an address conflict. 460A max of 3 requests can be in conflict. 461.It Li QHL_CONFLICT_CYCLES.LOCAL 462.Pq Event 25H , Umask 04H 463Counts cycles the Quickpath Home Logic Local Tracker contains two or more 464requests with an address conflict. 465A max of 3 requests can be in conflict. 466.It Li QHL_TO_QMC_BYPASS 467.Pq Event 26H , Umask 01H 468Counts number or requests to the Quickpath Memory Controller that bypass the 469Quickpath Home Logic. 470All local accesses can be bypassed. 471For remote requests, only read requests can be bypassed. 472.It Li QMC_ISOC_FULL.READ.CH0 473.Pq Event 28H , Umask 01H 474Counts cycles all the entries in the DRAM channel 0 high priority queue are 475occupied with isochronous read requests. 476.It Li QMC_ISOC_FULL.READ.CH1 477.Pq Event 28H , Umask 02H 478Counts cycles all the entries in the DRAM channel 1 high priority queue are 479occupied with isochronous read requests. 480.It Li QMC_ISOC_FULL.READ.CH2 481.Pq Event 28H , Umask 04H 482Counts cycles all the entries in the DRAM channel 2 high priority queue are 483occupied with isochronous read requests. 484.It Li QMC_ISOC_FULL.WRITE.CH0 485.Pq Event 28H , Umask 08H 486Counts cycles all the entries in the DRAM channel 0 high priority queue are 487occupied with isochronous write requests. 488.It Li QMC_ISOC_FULL.WRITE.CH1 489.Pq Event 28H , Umask 10H 490Counts cycles all the entries in the DRAM channel 1 high priority queue are 491occupied with isochronous write requests. 492.It Li QMC_ISOC_FULL.WRITE.CH2 493.Pq Event 28H , Umask 20H 494Counts cycles all the entries in the DRAM channel 2 high priority queue are 495occupied with isochronous write requests. 496.It Li QMC_BUSY.READ.CH0 497.Pq Event 29H , Umask 01H 498Counts cycles where Quickpath Memory Controller has at least 1 outstanding 499read request to DRAM channel 0. 500.It Li QMC_BUSY.READ.CH1 501.Pq Event 29H , Umask 02H 502Counts cycles where Quickpath Memory Controller has at least 1 outstanding 503read request to DRAM channel 1. 504.It Li QMC_BUSY.READ.CH2 505.Pq Event 29H , Umask 04H 506Counts cycles where Quickpath Memory Controller has at least 1 outstanding 507read request to DRAM channel 2. 508.It Li QMC_BUSY.WRITE.CH0 509.Pq Event 29H , Umask 08H 510Counts cycles where Quickpath Memory Controller has at least 1 outstanding 511write request to DRAM channel 0. 512.It Li QMC_BUSY.WRITE.CH1 513.Pq Event 29H , Umask 10H 514Counts cycles where Quickpath Memory Controller has at least 1 outstanding 515write request to DRAM channel 1. 516.It Li QMC_BUSY.WRITE.CH2 517.Pq Event 29H , Umask 20H 518Counts cycles where Quickpath Memory Controller has at least 1 outstanding 519write request to DRAM channel 2. 520.It Li QMC_OCCUPANCY.CH0 521.Pq Event 2AH , Umask 01H 522IMC channel 0 normal read request occupancy. 523.It Li QMC_OCCUPANCY.CH1 524.Pq Event 2AH , Umask 02H 525IMC channel 1 normal read request occupancy. 526.It Li QMC_OCCUPANCY.CH2 527.Pq Event 2AH , Umask 04H 528IMC channel 2 normal read request occupancy. 529.It Li QMC_OCCUPANCY.ANY 530.Pq Event 2AH , Umask 07H 531Normal read request occupancy for any channel. 532.It Li QMC_ISSOC_OCCUPANCY.CH0 533.Pq Event 2BH , Umask 01H 534IMC channel 0 issoc read request occupancy. 535.It Li QMC_ISSOC_OCCUPANCY.CH1 536.Pq Event 2BH , Umask 02H 537IMC channel 1 issoc read request occupancy. 538.It Li QMC_ISSOC_OCCUPANCY.CH2 539.Pq Event 2BH , Umask 04H 540IMC channel 2 issoc read request occupancy. 541.It Li QMC_ISSOC_READS.ANY 542.Pq Event 2BH , Umask 07H 543IMC issoc read request occupancy. 544.It Li QMC_NORMAL_READS.CH0 545.Pq Event 2CH , Umask 01H 546Counts the number of Quickpath Memory Controller channel 0 medium and low 547priority read requests. 548The QMC channel 0 normal read occupancy divided by this count provides the 549average QMC channel 0 read latency. 550.It Li QMC_NORMAL_READS.CH1 551.Pq Event 2CH , Umask 02H 552Counts the number of Quickpath Memory Controller channel 1 medium and low 553priority read requests. 554The QMC channel 1 normal read occupancy divided by this count provides the 555average QMC channel 1 read latency. 556.It Li QMC_NORMAL_READS.CH2 557.Pq Event 2CH , Umask 04H 558Counts the number of Quickpath Memory Controller channel 2 medium and low 559priority read requests. 560The QMC channel 2 normal read occupancy divided by this count provides the 561average QMC channel 2 read latency. 562.It Li QMC_NORMAL_READS.ANY 563.Pq Event 2CH , Umask 07H 564Counts the number of Quickpath Memory Controller medium and low priority read requests. 565The QMC normal read occupancy divided by this count provides the average 566QMC read latency. 567.It Li QMC_HIGH_PRIORITY_READS.CH0 568.Pq Event 2DH , Umask 01H 569Counts the number of Quickpath Memory Controller channel 0 high priority 570isochronous read requests. 571.It Li QMC_HIGH_PRIORITY_READS.CH1 572.Pq Event 2DH , Umask 02H 573Counts the number of Quickpath Memory Controller channel 1 high priority 574isochronous read requests. 575.It Li QMC_HIGH_PRIORITY_READS.CH2 576.Pq Event 2DH , Umask 04H 577Counts the number of Quickpath Memory Controller channel 2 high priority 578isochronous read requests. 579.It Li QMC_HIGH_PRIORITY_READS.ANY 580.Pq Event 2DH , Umask 07H 581Counts the number of Quickpath Memory Controller high priority isochronous 582read requests. 583.It Li QMC_CRITICAL_PRIORITY_READS.CH0 584.Pq Event 2EH , Umask 01H 585Counts the number of Quickpath Memory Controller channel 0 critical priority 586isochronous read requests. 587.It Li QMC_CRITICAL_PRIORITY_READS.CH1 588.Pq Event 2EH , Umask 02H 589Counts the number of Quickpath Memory Controller channel 1 critical priority 590isochronous read requests. 591.It Li QMC_CRITICAL_PRIORITY_READS.CH2 592.Pq Event 2EH , Umask 04H 593Counts the number of Quickpath Memory Controller channel 2 critical priority 594isochronous read requests. 595.It Li QMC_CRITICAL_PRIORITY_READS.ANY 596.Pq Event 2EH , Umask 07H 597Counts the number of Quickpath Memory Controller critical priority 598isochronous read requests. 599.It Li QMC_WRITES.FULL.CH0 600.Pq Event 2FH , Umask 01H 601Counts number of full cache line writes to DRAM channel 0. 602.It Li QMC_WRITES.FULL.CH1 603.Pq Event 2FH , Umask 02H 604Counts number of full cache line writes to DRAM channel 1. 605.It Li QMC_WRITES.FULL.CH2 606.Pq Event 2FH , Umask 04H 607Counts number of full cache line writes to DRAM channel 2. 608.It Li QMC_WRITES.FULL.ANY 609.Pq Event 2FH , Umask 07H 610Counts number of full cache line writes to DRAM. 611.It Li QMC_WRITES.PARTIAL.CH0 612.Pq Event 2FH , Umask 08H 613Counts number of partial cache line writes to DRAM channel 0. 614.It Li QMC_WRITES.PARTIAL.CH1 615.Pq Event 2FH , Umask 10H 616Counts number of partial cache line writes to DRAM channel 1. 617.It Li QMC_WRITES.PARTIAL.CH2 618.Pq Event 2FH , Umask 20H 619Counts number of partial cache line writes to DRAM channel 2. 620.It Li QMC_WRITES.PARTIAL.ANY 621.Pq Event 2FH , Umask 38H 622Counts number of partial cache line writes to DRAM. 623.It Li QMC_CANCEL.CH0 624.Pq Event 30H , Umask 01H 625Counts number of DRAM channel 0 cancel requests. 626.It Li QMC_CANCEL.CH1 627.Pq Event 30H , Umask 02H 628Counts number of DRAM channel 1 cancel requests. 629.It Li QMC_CANCEL.CH2 630.Pq Event 30H , Umask 04H 631Counts number of DRAM channel 2 cancel requests. 632.It Li QMC_CANCEL.ANY 633.Pq Event 30H , Umask 07H 634Counts number of DRAM cancel requests. 635.It Li QMC_PRIORITY_UPDATES.CH0 636.Pq Event 31H , Umask 01H 637Counts number of DRAM channel 0 priority updates. 638A priority update occurs when an ISOC high or critical request is 639received by the QHL and there is a matching request with normal priority 640that has already been issued to the QMC. 641In this instance, the QHL will send a priority update to QMC to 642expedite the request. 643.It Li QMC_PRIORITY_UPDATES.CH1 644.Pq Event 31H , Umask 02H 645Counts number of DRAM channel 1 priority updates. 646A priority update occurs when an ISOC high or critical request is received 647by the QHL and there is a matching request with normal priority that has 648already been issued to the QMC. 649In this instance, the QHL will send a priority update to QMC to expedite the request. 650.It Li QMC_PRIORITY_UPDATES.CH2 651.Pq Event 31H , Umask 04H 652Counts number of DRAM channel 2 priority updates. 653A priority update occurs when an ISOC high or critical request is received 654by the QHL and there is a matching request with normal priority that has 655already been issued to the QMC. 656In this instance, the QHL will send a priority update to QMC to expedite the request. 657.It Li QMC_PRIORITY_UPDATES.ANY 658.Pq Event 31H , Umask 07H 659Counts number of DRAM priority updates. 660A priority update occurs when an ISOC high or critical request is received 661by the QHL and there is a matching request with normal priority that has already 662been issued to the QMC. 663In this instance, the QHL will send a priority update to QMC to expedite the request. 664.It Li IMC_RETRY.CH0 665.Pq Event 32H , Umask 01H 666Counts number of IMC DRAM channel 0 retries. 667DRAM retry only occurs when configured in RAS mode. 668.It Li IMC_RETRY.CH1 669.Pq Event 32H , Umask 02H 670Counts number of IMC DRAM channel 1 retries. 671DRAM retry only occurs when configured in RAS mode. 672.It Li IMC_RETRY.CH2 673.Pq Event 32H , Umask 04H 674Counts number of IMC DRAM channel 2 retries. 675DRAM retry only occurs when configured in RAS mode. 676.It Li IMC_RETRY.ANY 677.Pq Event 32H , Umask 07H 678Counts number of IMC DRAM retries from any channel. 679DRAM retry only occurs when configured in RAS mode. 680.It Li QHL_FRC_ACK_CNFLTS.IOH 681.Pq Event 33H , Umask 01H 682Counts number of Force Acknowledge Conflict messages sent by the Quickpath 683Home Logic to the IOH. 684.It Li QHL_FRC_ACK_CNFLTS.REMOTE 685.Pq Event 33H , Umask 02H 686Counts number of Force Acknowledge Conflict messages sent by the Quickpath 687Home Logic to the remote home. 688.It Li QHL_FRC_ACK_CNFLTS.LOCAL 689.Pq Event 33H , Umask 04H 690Counts number of Force Acknowledge Conflict messages sent by the Quickpath 691Home Logic to the local home. 692.It Li QHL_FRC_ACK_CNFLTS.ANY 693.Pq Event 33H , Umask 07H 694Counts number of Force Acknowledge Conflict messages sent by the Quickpath 695Home Logic. 696.It Li QHL_SLEEPS.IOH_ORDER 697.Pq Event 34H , Umask 01H 698Counts number of occurrences a request was put to sleep due to IOH ordering 699(write after read) conflicts. 700While in the sleep state, the request is not eligible to be scheduled to the QMC. 701.It Li QHL_SLEEPS.REMOTE_ORDER 702.Pq Event 34H , Umask 02H 703Counts number of occurrences a request was put to sleep due to remote socket 704ordering (write after read) conflicts. 705While in the sleep state, the request is not eligible to be scheduled to the QMC. 706.It Li QHL_SLEEPS.LOCAL_ORDER 707.Pq Event 34H , Umask 04H 708Counts number of occurrences a request was put to sleep due to local socket 709ordering (write after read) conflicts. 710While in the sleep state, the request is not eligible to be scheduled to the QMC. 711.It Li QHL_SLEEPS.IOH_CONFLICT 712.Pq Event 34H , Umask 08H 713Counts number of occurrences a request was put to sleep due to IOH address conflicts. 714While in the sleep state, the request is not eligible to be scheduled to the QMC. 715.It Li QHL_SLEEPS.REMOTE_CONFLICT 716.Pq Event 34H , Umask 10H 717Counts number of occurrences a request was put to sleep due to remote socket 718address conflicts. 719While in the sleep state, the request is not eligible to be scheduled to the QMC. 720.It Li QHL_SLEEPS.LOCAL_CONFLICT 721.Pq Event 34H , Umask 20H 722Counts number of occurrences a request was put to sleep due to local socket address conflicts. 723While in the sleep state, the request is not eligible to be scheduled to the QMC. 724.It Li ADDR_OPCODE_MATCH.IOH 725.Pq Event 35H , Umask 01H 726Counts number of requests from the IOH, address/opcode of request is 727qualified by mask value written to MSR 396H. 728The following mask values are supported: 7290: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 73040001D00_00000000H:RSPIWB 731Match opcode/address by writing MSR 396H with mask supported mask value. 732.It Li ADDR_OPCODE_MATCH.REMOTE 733.Pq Event 35H , Umask 02H 734Counts number of requests from the remote socket, address/opcode of request 735is qualified by mask value written to MSR 396H. 736The following mask values are supported: 7370: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 73840001D00_00000000H:RSPIWB 739Match opcode/address by writing MSR 396H with mask supported mask value. 740.It Li ADDR_OPCODE_MATCH.LOCAL 741.Pq Event 35H , Umask 04H 742Counts number of requests from the local socket, address/opcode of request 743is qualified by mask value written to MSR 396H. 744The following mask values are supported: 7450: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 74640001D00_00000000H:RSPIWB 747Match opcode/address by writing MSR 396H with mask supported mask value. 748.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 749.Pq Event 40H , Umask 01H 750Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled 751due to lack of a VNA and VN0 credit. 752Note that this event does not filter out when a flit would not have been selected 753for arbitration because another virtual channel is getting arbitrated. 754.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 755.Pq Event 40H , Umask 02H 756Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled 757due to lack of a VNA and VN0 credit. 758Note that this event does not filter out when a flit would not have been selected 759for arbitration because another virtual channel is getting arbitrated. 760.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 761.Pq Event 40H , Umask 04H 762Counts cycles the Quickpath outbound link 0 non-data response virtual 763channel is stalled due to lack of a VNA and VN0 credit. 764Note that this event does not filter out when a flit would not have been selected 765for arbitration because another virtual channel is getting arbitrated. 766.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 767.Pq Event 40H , Umask 08H 768Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled 769due to lack of a VNA and VN0 credit. 770Note that this event does not filter out when a flit would not have been selected 771for arbitration because another virtual channel is getting arbitrated. 772.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 773.Pq Event 40H , Umask 10H 774Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled 775due to lack of a VNA and VN0 credit. 776Note that this event does not filter out when a flit would not have been selected 777for arbitration because another virtual channel is getting arbitrated. 778.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 779.Pq Event 40H , Umask 20H 780Counts cycles the Quickpath outbound link 1 non-data response virtual 781channel is stalled due to lack of a VNA and VN0 credit. 782Note that this event does not filter out when a flit would not have been selected 783for arbitration because another virtual channel is getting arbitrated. 784.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 785.Pq Event 40H , Umask 07H 786Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 787to lack of a VNA and VN0 credit. 788Note that this event does not filter out when a flit would not have been selected 789for arbitration because another virtual channel is getting arbitrated. 790.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 791.Pq Event 40H , Umask 38H 792Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 793to lack of a VNA and VN0 credit. 794Note that this event does not filter out when a flit would not have been selected 795for arbitration because another virtual channel is getting arbitrated. 796.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 797.Pq Event 41H , Umask 01H 798Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is 799stalled due to lack of VNA and VN0 credits. 800Note that this event does not filter out when a flit would not have been selected 801for arbitration because another virtual channel is getting arbitrated. 802.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 803.Pq Event 41H , Umask 02H 804Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual 805channel is stalled due to lack of VNA and VN0 credits. 806Note that this event does not filter out when a flit would not have been selected 807for arbitration because another virtual channel is getting arbitrated. 808.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 809.Pq Event 41H , Umask 04H 810Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual 811channel is stalled due to lack of VNA and VN0 credits. 812Note that this event does not filter out when a flit would not have been selected 813for arbitration because another virtual channel is getting arbitrated. 814.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 815.Pq Event 41H , Umask 08H 816Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is 817stalled due to lack of VNA and VN0 credits. 818Note that this event does not filter out when a flit would not have been selected 819for arbitration because another virtual channel is getting arbitrated. 820.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 821.Pq Event 41H , Umask 10H 822Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual 823channel is stalled due to lack of VNA and VN0 credits. 824Note that this event does not filter out when a flit would not have been selected 825for arbitration because another virtual channel is getting arbitrated. 826.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 827.Pq Event 41H , Umask 20H 828Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual 829channel is stalled due to lack of VNA and VN0 credits. 830Note that this event does not filter out when a flit would not have been selected 831for arbitration because another virtual channel is getting arbitrated. 832.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 833.Pq Event 41H , Umask 07H 834Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 835to lack of VNA and VN0 credits. 836Note that this event does not filter out when a flit would not have been selected 837for arbitration because another virtual channel is getting arbitrated. 838.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 839.Pq Event 41H , Umask 38H 840Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 841to lack of VNA and VN0 credits. 842Note that this event does not filter out when a flit would not have been selected 843for arbitration because another virtual channel is getting arbitrated. 844.It Li QPI_TX_HEADER.FULL.LINK_0 845.Pq Event 42H , Umask 01H 846Number of cycles that the header buffer in the Quickpath Interface outbound 847link 0 is full. 848.It Li QPI_TX_HEADER.BUSY.LINK_0 849.Pq Event 42H , Umask 02H 850Number of cycles that the header buffer in the Quickpath Interface outbound 851link 0 is busy. 852.It Li QPI_TX_HEADER.FULL.LINK_1 853.Pq Event 42H , Umask 04H 854Number of cycles that the header buffer in the Quickpath Interface outbound 855link 1 is full. 856.It Li QPI_TX_HEADER.BUSY.LINK_1 857.Pq Event 42H , Umask 08H 858Number of cycles that the header buffer in the Quickpath Interface outbound 859link 1 is busy. 860.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 861.Pq Event 43H , Umask 01H 862Number of cycles that snoop packets incoming to the Quickpath Interface link 8630 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 864does not have any available entries. 865.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 866.Pq Event 43H , Umask 02H 867Number of cycles that snoop packets incoming to the Quickpath Interface link 8681 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 869does not have any available entries. 870.It Li DRAM_OPEN.CH0 871.Pq Event 60H , Umask 01H 872Counts number of DRAM Channel 0 open commands issued either for read or write. 873To read or write data, the referenced DRAM page must first be opened. 874.It Li DRAM_OPEN.CH1 875.Pq Event 60H , Umask 02H 876Counts number of DRAM Channel 1 open commands issued either for read or write. 877To read or write data, the referenced DRAM page must first be opened. 878.It Li DRAM_OPEN.CH2 879.Pq Event 60H , Umask 04H 880Counts number of DRAM Channel 2 open commands issued either for read or write. 881To read or write data, the referenced DRAM page must first be opened. 882.It Li DRAM_PAGE_CLOSE.CH0 883.Pq Event 61H , Umask 01H 884DRAM channel 0 command issued to CLOSE a page due to page idle timer expiration. 885Closing a page is done by issuing a precharge. 886.It Li DRAM_PAGE_CLOSE.CH1 887.Pq Event 61H , Umask 02H 888DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration. 889Closing a page is done by issuing a precharge. 890.It Li DRAM_PAGE_CLOSE.CH2 891.Pq Event 61H , Umask 04H 892DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration. 893Closing a page is done by issuing a precharge. 894.It Li DRAM_PAGE_MISS.CH0 895.Pq Event 62H , Umask 01H 896Counts the number of precharges (PRE) that were issued to DRAM channel 0 897because there was a page miss. 898A page miss refers to a situation in which a page is currently open and another 899page from the same bank needs to be opened. 900The new page experiences a page miss. 901Closing of the old page is done by issuing a precharge. 902.It Li DRAM_PAGE_MISS.CH1 903.Pq Event 62H , Umask 02H 904Counts the number of precharges (PRE) that were issued to DRAM channel 1 905because there was a page miss. 906A page miss refers to a situation in which a page is currently open and another 907page from the same bank needs to be opened. 908The new page experiences a page miss. 909Closing of the old page is done by issuing a precharge. 910.It Li DRAM_PAGE_MISS.CH2 911.Pq Event 62H , Umask 04H 912Counts the number of precharges (PRE) that were issued to DRAM channel 2 913because there was a page miss. 914A page miss refers to a situation in which a page is currently open and another 915page from the same bank needs to be opened. 916The new page experiences a page miss. 917Closing of the old page is done by issuing a precharge. 918.It Li DRAM_READ_CAS.CH0 919.Pq Event 63H , Umask 01H 920Counts the number of times a read CAS command was issued on DRAM channel 0. 921.It Li DRAM_READ_CAS.AUTOPRE_CH0 922.Pq Event 63H , Umask 02H 923Counts the number of times a read CAS command was issued on DRAM channel 0 924where the command issued used the auto-precharge (auto page close) mode. 925.It Li DRAM_READ_CAS.CH1 926.Pq Event 63H , Umask 04H 927Counts the number of times a read CAS command was issued on DRAM channel 1. 928.It Li DRAM_READ_CAS.AUTOPRE_CH1 929.Pq Event 63H , Umask 08H 930Counts the number of times a read CAS command was issued on DRAM channel 1 931where the command issued used the auto-precharge (auto page close) mode. 932.It Li DRAM_READ_CAS.CH2 933.Pq Event 63H , Umask 10H 934Counts the number of times a read CAS command was issued on DRAM channel 2. 935.It Li DRAM_READ_CAS.AUTOPRE_CH2 936.Pq Event 63H , Umask 20H 937Counts the number of times a read CAS command was issued on DRAM channel 2 938where the command issued used the auto-precharge (auto page close) mode. 939.It Li DRAM_WRITE_CAS.CH0 940.Pq Event 64H , Umask 01H 941Counts the number of times a write CAS command was issued on DRAM channel 0. 942.It Li DRAM_WRITE_CAS.AUTOPRE_CH0 943.Pq Event 64H , Umask 02H 944Counts the number of times a write CAS command was issued on DRAM channel 0 945where the command issued used the auto-precharge (auto page close) mode. 946.It Li DRAM_WRITE_CAS.CH1 947.Pq Event 64H , Umask 04H 948Counts the number of times a write CAS command was issued on DRAM channel 1. 949.It Li DRAM_WRITE_CAS.AUTOPRE_CH1 950.Pq Event 64H , Umask 08H 951Counts the number of times a write CAS command was issued on DRAM channel 1 952where the command issued used the auto-precharge (auto page close) mode. 953.It Li DRAM_WRITE_CAS.CH2 954.Pq Event 64H , Umask 10H 955Counts the number of times a write CAS command was issued on DRAM channel 2. 956.It Li DRAM_WRITE_CAS.AUTOPRE_CH2 957.Pq Event 64H , Umask 20H 958Counts the number of times a write CAS command was issued on DRAM channel 2 959where the command issued used the auto-precharge (auto page close) mode. 960.It Li DRAM_REFRESH.CH0 961.Pq Event 65H , Umask 01H 962Counts number of DRAM channel 0 refresh commands. 963DRAM loses data content over time. 964In order to keep correct data content, the data values have to be 965refreshed periodically. 966.It Li DRAM_REFRESH.CH1 967.Pq Event 65H , Umask 02H 968Counts number of DRAM channel 1 refresh commands. 969DRAM loses data content over time. 970In order to keep correct data content, the data values have to be refreshed periodically. 971.It Li DRAM_REFRESH.CH2 972.Pq Event 65H , Umask 04H 973Counts number of DRAM channel 2 refresh commands. 974DRAM loses data content over time. 975In order to keep correct data content, the data values have to be refreshed periodically. 976.It Li DRAM_PRE_ALL.CH0 977.Pq Event 66H , Umask 01H 978Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close 979all open pages in a rank. 980PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. 981.It Li DRAM_PRE_ALL.CH1 982.Pq Event 66H , Umask 02H 983Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close 984all open pages in a rank. 985PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. 986.It Li DRAM_PRE_ALL.CH2 987.Pq Event 66H , Umask 04H 988Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close 989all open pages in a rank. 990PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. 991.It Li DRAM_THERMAL_THROTTLED 992.Pq Event 67H , Umask 01H 993Uncore cycles DRAM was throttled due to its temperature being above the 994thermal throttling threshold. 995.It Li THERMAL_THROTTLING_TEMP.CORE_0 996.Pq Event 80H , Umask 01H 997Cycles that the PCU records that core 0 is above the thermal throttling 998threshold temperature. 999.It Li THERMAL_THROTTLING_TEMP.CORE_1 1000.Pq Event 80H , Umask 02H 1001Cycles that the PCU records that core 1 is above the thermal throttling 1002threshold temperature. 1003.It Li THERMAL_THROTTLING_TEMP.CORE_2 1004.Pq Event 80H , Umask 04H 1005Cycles that the PCU records that core 2 is above the thermal throttling 1006threshold temperature. 1007.It Li THERMAL_THROTTLING_TEMP.CORE_3 1008.Pq Event 80H , Umask 08H 1009Cycles that the PCU records that core 3 is above the thermal throttling 1010threshold temperature. 1011.It Li THERMAL_THROTTLED_TEMP.CORE_0 1012.Pq Event 81H , Umask 01H 1013Cycles that the PCU records that core 0 is in the power throttled state due 1014to cores temperature being above the thermal throttling threshold. 1015.It Li THERMAL_THROTTLED_TEMP.CORE_1 1016.Pq Event 81H , Umask 02H 1017Cycles that the PCU records that core 1 is in the power throttled state due 1018to cores temperature being above the thermal throttling threshold. 1019.It Li THERMAL_THROTTLED_TEMP.CORE_2 1020.Pq Event 81H , Umask 04H 1021Cycles that the PCU records that core 2 is in the power throttled state due 1022to cores temperature being above the thermal throttling threshold. 1023.It Li THERMAL_THROTTLED_TEMP.CORE_3 1024.Pq Event 81H , Umask 08H 1025Cycles that the PCU records that core 3 is in the power throttled state due 1026to cores temperature being above the thermal throttling threshold. 1027.It Li PROCHOT_ASSERTION 1028.Pq Event 82H , Umask 01H 1029Number of system assertions of PROCHOT indicating the entire processor has 1030exceeded the thermal limit. 1031.It Li THERMAL_THROTTLING_PROCHOT.CORE_0 1032.Pq Event 83H , Umask 01H 1033Cycles that the PCU records that core 0 is a low power state due to the 1034system asserting PROCHOT the entire processor has exceeded the thermal 1035limit. 1036.It Li THERMAL_THROTTLING_PROCHOT.CORE_1 1037.Pq Event 83H , Umask 02H 1038Cycles that the PCU records that core 1 is a low power state due to the 1039system asserting PROCHOT the entire processor has exceeded the thermal 1040limit. 1041.It Li THERMAL_THROTTLING_PROCHOT.CORE_2 1042.Pq Event 83H , Umask 04H 1043Cycles that the PCU records that core 2 is a low power state due to the 1044system asserting PROCHOT the entire processor has exceeded the thermal 1045limit. 1046.It Li THERMAL_THROTTLING_PROCHOT.CORE_3 1047.Pq Event 83H , Umask 08H 1048Cycles that the PCU records that core 3 is a low power state due to the 1049system asserting PROCHOT the entire processor has exceeded the thermal 1050limit. 1051.It Li TURBO_MODE.CORE_0 1052.Pq Event 84H , Umask 01H 1053Uncore cycles that core 0 is operating in turbo mode. 1054.It Li TURBO_MODE.CORE_1 1055.Pq Event 84H , Umask 02H 1056Uncore cycles that core 1 is operating in turbo mode. 1057.It Li TURBO_MODE.CORE_2 1058.Pq Event 84H , Umask 04H 1059Uncore cycles that core 2 is operating in turbo mode. 1060.It Li TURBO_MODE.CORE_3 1061.Pq Event 84H , Umask 08H 1062Uncore cycles that core 3 is operating in turbo mode. 1063.It Li CYCLES_UNHALTED_L3_FLL_ENABLE 1064.Pq Event 85H , Umask 02H 1065Uncore cycles that at least one core is unhalted and all L3 ways are 1066enabled. 1067.It Li CYCLES_UNHALTED_L3_FLL_DISABLE 1068.Pq Event 86H , Umask 01H 1069Uncore cycles that at least one core is unhalted and all L3 ways are 1070disabled. 1071.El 1072.Sh SEE ALSO 1073.Xr pmc 3 , 1074.Xr pmc.atom 3 , 1075.Xr pmc.core 3 , 1076.Xr pmc.corei7 3 , 1077.Xr pmc.corei7uc 3 , 1078.Xr pmc.iaf 3 , 1079.Xr pmc.k7 3 , 1080.Xr pmc.k8 3 , 1081.Xr pmc.soft 3 , 1082.Xr pmc.tsc 3 , 1083.Xr pmc.ucf 3 , 1084.Xr pmc.westmere 3 , 1085.Xr pmc_cpuinfo 3 , 1086.Xr pmclog 3 , 1087.Xr hwpmc 4 1088.Sh HISTORY 1089The 1090.Nm pmc 1091library first appeared in 1092.Fx 6.0 . 1093.Sh AUTHORS 1094The 1095.Lb libpmc 1096library was written by 1097.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1098