1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2010 27.Dt PMC.WESTMEREUC 3 28.Os 29.Sh NAME 30.Nm pmc.westmere 31.Nd uncore measurement events for 32.Tn Intel 33.Tn Westmere 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Westmere" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs contain two classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_UCP" 47.It Li PMC_CLASS_UCF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_UCP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Westmere PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss WESTMERE UNCORE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.ucf 3 . 69Not all CPUs in this family implement fixed-function counters. 70.Ss WESTMERE UNCORE PROGRAMMABLE PMCS 71The programmable PMCs support the following capabilities: 72.Bl -column "PMC_CAP_INTERRUPT" "Support" 73.It Em Capability Ta Em Support 74.It PMC_CAP_CASCADE Ta \&No 75.It PMC_CAP_EDGE Ta Yes 76.It PMC_CAP_INTERRUPT Ta \&No 77.It PMC_CAP_INVERT Ta Yes 78.It PMC_CAP_READ Ta Yes 79.It PMC_CAP_PRECISE Ta \&No 80.It PMC_CAP_SYSTEM Ta \&No 81.It PMC_CAP_TAGGING Ta \&No 82.It PMC_CAP_THRESHOLD Ta Yes 83.It PMC_CAP_USER Ta \&No 84.It PMC_CAP_WRITE Ta Yes 85.El 86.Ss Event Qualifiers 87Event specifiers for these PMCs support the following common 88qualifiers: 89.Bl -tag -width indent 90.It Li cmask= Ns Ar value 91Configure the PMC to increment only if the number of configured 92events measured in a cycle is greater than or equal to 93.Ar value . 94.It Li edge 95Configure the PMC to count the number of de-asserted to asserted 96transitions of the conditions expressed by the other qualifiers. 97If specified, the counter will increment only once whenever a 98condition becomes true, irrespective of the number of clocks during 99which the condition remains true. 100.It Li inv 101Invert the sense of comparison when the 102.Dq Li cmask 103qualifier is present, making the counter increment when the number of 104events per cycle is less than the value specified by the 105.Dq Li cmask 106qualifier. 107.El 108.Ss Event Specifiers (Programmable PMCs) 109Westmere uncore programmable PMCs support the following events: 110.Bl -tag -width indent 111.It Li GQ_CYCLES_FULL.READ_TRACKER 112.Pq Event 00H , Umask 01H 113Uncore cycles Global Queue read tracker is full. 114.It Li GQ_CYCLES_FULL.WRITE_TRACKER 115.Pq Event 00H , Umask 02H 116Uncore cycles Global Queue write tracker is full. 117.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER 118.Pq Event 00H , Umask 04H 119Uncore cycles Global Queue peer probe tracker is full. The peer probe 120tracker queue tracks snoops from the IOH and remote sockets. 121.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER 122.Pq Event 01H , Umask 01H 123Uncore cycles were Global Queue read tracker has at least one valid entry. 124.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER 125.Pq Event 01H , Umask 02H 126Uncore cycles were Global Queue write tracker has at least one valid entry. 127.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER 128.Pq Event 01H , Umask 04H 129Uncore cycles were Global Queue peer probe tracker has at least one valid 130entry. The peer probe tracker queue tracks IOH and remote socket snoops. 131.It Li GQ_OCCUPANCY.READ_TRACKER 132.Pq Event 02H , Umask 01H 133Increments the number of queue entries (code read, data read, and RFOs) in 134the tread tracker. The GQ read tracker allocate to deallocate occupancy 135count is divided by the count to obtain the average read tracker latency. 136.It Li GQ_ALLOC.READ_TRACKER 137.Pq Event 03H , Umask 01H 138Counts the number of tread tracker allocate to deallocate entries. The GQ 139read tracker allocate to deallocate occupancy count is divided by the count 140to obtain the average read tracker latency. 141.It Li GQ_ALLOC.RT_L3_MISS 142.Pq Event 03H , Umask 02H 143Counts the number GQ read tracker entries for which a full cache line read 144has missed the L3. The GQ read tracker L3 miss to fill occupancy count is 145divided by this count to obtain the average cache line read L3 miss latency. 146The latency represents the time after which the L3 has determined that the 147cache line has missed. The time between a GQ read tracker allocation and the 148L3 determining that the cache line has missed is the average L3 hit latency. 149The total L3 cache line read miss latency is the hit latency + L3 miss 150latency. 151.It Li GQ_ALLOC.RT_TO_L3_RESP 152.Pq Event 03H , Umask 04H 153Counts the number of GQ read tracker entries that are allocated in the read 154tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy 155count is divided by this count to obtain the average L3 hit latency. 156.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED 157.Pq Event 03H , Umask 08H 158Counts the number of GQ read tracker entries that are allocated in the read 159tracker, have missed in the L3 and have not acquired a Request Transaction 160ID. The GQ read tracker L3 miss to RTID acquired occupancy count is 161divided by this count to obtain the average latency for a read L3 miss to 162acquire an RTID. 163.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED 164.Pq Event 03H , Umask 10H 165Counts the number of GQ write tracker entries that are allocated in the 166write tracker, have missed in the L3 and have not acquired a Request 167Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is 168divided by this count to obtain the average latency for a write L3 miss to 169acquire an RTID. 170.It Li GQ_ALLOC.WRITE_TRACKER 171.Pq Event 03H , Umask 20H 172Counts the number of GQ write tracker entries that are allocated in the 173write tracker queue that miss the L3. The GQ write tracker occupancy count 174is divided by the this count to obtain the average L3 write miss latency. 175.It Li GQ_ALLOC.PEER_PROBE_TRACKER 176.Pq Event 03H , Umask 40H 177Counts the number of GQ peer probe tracker (snoop) entries that are 178allocated in the peer probe tracker queue that miss the L3. The GQ peer 179probe occupancy count is divided by this count to obtain the average L3 peer 180probe miss latency. 181.It Li GQ_DATA.FROM_QPI 182.Pq Event 04H , Umask 01H 183Cycles Global Queue Quickpath Interface input data port is busy importing 184data from the Quickpath Interface. Each cycle the input port can transfer 8 185or 16 bytes of data. 186.It Li GQ_DATA.FROM_QMC 187.Pq Event 04H , Umask 02H 188Cycles Global Queue Quickpath Memory Interface input data port is busy 189importing data from the Quickpath Memory Interface. Each cycle the input 190port can transfer 8 or 16 bytes of data. 191.It Li GQ_DATA.FROM_L3 192.Pq Event 04H , Umask 04H 193Cycles GQ L3 input data port is busy importing data from the Last Level 194Cache. Each cycle the input port can transfer 32 bytes of data. 195.It Li GQ_DATA.FROM_CORES_02 196.Pq Event 04H , Umask 08H 197Cycles GQ Core 0 and 2 input data port is busy importing data from processor 198cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. 199.It Li GQ_DATA.FROM_CORES_13 200.Pq Event 04H , Umask 10H 201Cycles GQ Core 1 and 3 input data port is busy importing data from processor 202cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. 203.It Li GQ_DATA.TO_QPI_QMC 204.Pq Event 05H , Umask 01H 205Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath 206Interface or Quickpath Memory Interface. Each cycle the output port can 207transfer 32 bytes of data. 208.It Li GQ_DATA.TO_L3 209.Pq Event 05H , Umask 02H 210Cycles GQ L3 output data port is busy sending data to the Last Level Cache. 211Each cycle the output port can transfer 32 bytes of data. 212.It Li GQ_DATA.TO_CORES 213.Pq Event 05H , Umask 04H 214Cycles GQ Core output data port is busy sending data to the Cores. Each 215cycle the output port can transfer 32 bytes of data. 216.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE 217.Pq Event 06H , Umask 01H 218Number of snoop responses to the local home that L3 does not have the 219referenced cache line. 220.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE 221.Pq Event 06H , Umask 02H 222Number of snoop responses to the local home that L3 has the referenced line 223cached in the S state. 224.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE 225.Pq Event 06H , Umask 04H 226Number of responses to code or data read snoops to the local home that the 227L3 has the referenced cache line in the E state. The L3 cache line state is 228changed to the S state and the line is forwarded to the local home in the S 229state. 230.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE 231.Pq Event 06H , Umask 08H 232Number of responses to read invalidate snoops to the local home that the L3 233has the referenced cache line in the M state. The L3 cache line state is 234invalidated and the line is forwarded to the local home in the M state. 235.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT 236.Pq Event 06H , Umask 10H 237Number of conflict snoop responses sent to the local home. 238.It Li SNP_RESP_TO_LOCAL_HOME.WB 239.Pq Event 06H , Umask 20H 240Number of responses to code or data read snoops to the local home that the 241L3 has the referenced line cached in the M state. 242.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE 243.Pq Event 07H , Umask 01H 244Number of snoop responses to a remote home that L3 does not have the 245referenced cache line. 246.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE 247.Pq Event 07H , Umask 02H 248Number of snoop responses to a remote home that L3 has the referenced line 249cached in the S state. 250.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE 251.Pq Event 07H , Umask 04H 252Number of responses to code or data read snoops to a remote home that the L3 253has the referenced cache line in the E state. The L3 cache line state is 254changed to the S state and the line is forwarded to the remote home in the S 255state. 256.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE 257.Pq Event 07H , Umask 08H 258Number of responses to read invalidate snoops to a remote home that the L3 259has the referenced cache line in the M state. The L3 cache line state is 260invalidated and the line is forwarded to the remote home in the M state. 261.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT 262.Pq Event 07H , Umask 10H 263Number of conflict snoop responses sent to the local home. 264.It Li SNP_RESP_TO_REMOTE_HOME.WB 265.Pq Event 07H , Umask 20H 266Number of responses to code or data read snoops to a remote home that the L3 267has the referenced line cached in the M state. 268.It Li SNP_RESP_TO_REMOTE_HOME.HITM 269.Pq Event 07H , Umask 24H 270Number of HITM snoop responses to a remote home. 271.It Li L3_HITS.READ 272.Pq Event 08H , Umask 01H 273Number of code read, data read and RFO requests that hit in the L3. 274.It Li L3_HITS.WRITE 275.Pq Event 08H , Umask 02H 276Number of writeback requests that hit in the L3. Writebacks from the cores 277will always result in L3 hits due to the inclusive property of the L3. 278.It Li L3_HITS.PROBE 279.Pq Event 08H , Umask 04H 280Number of snoops from IOH or remote sockets that hit in the L3. 281.It Li L3_HITS.ANY 282.Pq Event 08H , Umask 03H 283Number of reads and writes that hit the L3. 284.It Li L3_MISS.READ 285.Pq Event 09H , Umask 01H 286Number of code read, data read and RFO requests that miss the L3. 287.It Li L3_MISS.WRITE 288.Pq Event 09H , Umask 02H 289Number of writeback requests that miss the L3. Should always be zero as 290writebacks from the cores will always result in L3 hits due to the inclusive 291property of the L3. 292.It Li L3_MISS.PROBE 293.Pq Event 09H , Umask 04H 294Number of snoops from IOH or remote sockets that miss the L3. 295.It Li L3_MISS.ANY 296.Pq Event 09H , Umask 03H 297Number of reads and writes that miss the L3. 298.It Li L3_LINES_IN.M_STATE 299.Pq Event 0AH , Umask 01H 300Counts the number of L3 lines allocated in M state. The only time a cache 301line is allocated in the M state is when the line was forwarded in M state 302is forwarded due to a Snoop Read Invalidate Own request. 303.It Li L3_LINES_IN.E_STATE 304.Pq Event 0AH , Umask 02H 305Counts the number of L3 lines allocated in E state. 306.It Li L3_LINES_IN.S_STATE 307.Pq Event 0AH , Umask 04H 308Counts the number of L3 lines allocated in S state. 309.It Li L3_LINES_IN.F_STATE 310.Pq Event 0AH , Umask 08H 311Counts the number of L3 lines allocated in F state. 312.It Li L3_LINES_IN.ANY 313.Pq Event 0AH , Umask 0FH 314Counts the number of L3 lines allocated in any state. 315.It Li L3_LINES_OUT.M_STATE 316.Pq Event 0BH , Umask 01H 317Counts the number of L3 lines victimized that were in the M state. When the 318victim cache line is in M state, the line is written to its home cache agent 319which can be either local or remote. 320.It Li L3_LINES_OUT.E_STATE 321.Pq Event 0BH , Umask 02H 322Counts the number of L3 lines victimized that were in the E state. 323.It Li L3_LINES_OUT.S_STATE 324.Pq Event 0BH , Umask 04H 325Counts the number of L3 lines victimized that were in the S state. 326.It Li L3_LINES_OUT.I_STATE 327.Pq Event 0BH , Umask 08H 328Counts the number of L3 lines victimized that were in the I state. 329.It Li L3_LINES_OUT.F_STATE 330.Pq Event 0BH , Umask 10H 331Counts the number of L3 lines victimized that were in the F state. 332.It Li L3_LINES_OUT.ANY 333.Pq Event 0BH , Umask 1FH 334Counts the number of L3 lines victimized in any state. 335.It Li GQ_SNOOP.GOTO_S 336.Pq Event 0CH , Umask 01H 337Counts the number of remote snoops that have requested a cache line be set 338to the S state. 339.It Li GQ_SNOOP.GOTO_I 340.Pq Event 0CH , Umask 02H 341Counts the number of remote snoops that have requested a cache line be set 342to the I state. 343.It Li GQ_SNOOP.GOTO_S_HIT_E 344.Pq Event 0CH , Umask 04H 345Counts the number of remote snoops that have requested a cache line be set 346to the S state from E state. 347Requires writing MSR 301H with mask = 2H 348.It Li GQ_SNOOP.GOTO_S_HIT_F 349.Pq Event 0CH , Umask 04H 350Counts the number of remote snoops that have requested a cache line be set 351to the S state from F (forward) state. 352Requires writing MSR 301H with mask = 8H 353.It Li GQ_SNOOP.GOTO_S_HIT_M 354.Pq Event 0CH , Umask 04H 355Counts the number of remote snoops that have requested a cache line be set 356to the S state from M state. 357Requires writing MSR 301H with mask = 1H 358.It Li GQ_SNOOP.GOTO_S_HIT_S 359.Pq Event 0CH , Umask 04H 360Counts the number of remote snoops that have requested a cache line be set 361to the S state from S state. 362Requires writing MSR 301H with mask = 4H 363.It Li GQ_SNOOP.GOTO_I_HIT_E 364.Pq Event 0CH , Umask 08H 365Counts the number of remote snoops that have requested a cache line be set 366to the I state from E state. 367Requires writing MSR 301H with mask = 2H 368.It Li GQ_SNOOP.GOTO_I_HIT_F 369.Pq Event 0CH , Umask 08H 370Counts the number of remote snoops that have requested a cache line be set 371to the I state from F (forward) state. 372Requires writing MSR 301H with mask = 8H 373.It Li GQ_SNOOP.GOTO_I_HIT_M 374.Pq Event 0CH , Umask 08H 375Counts the number of remote snoops that have requested a cache line be set 376to the I state from M state. 377Requires writing MSR 301H with mask = 1H 378.It Li GQ_SNOOP.GOTO_I_HIT_S 379.Pq Event 0CH , Umask 08H 380Counts the number of remote snoops that have requested a cache line be set 381to the I state from S state. 382Requires writing MSR 301H with mask = 4H 383.It Li QHL_REQUESTS.IOH_READS 384.Pq Event 20H , Umask 01H 385Counts number of Quickpath Home Logic read requests from the IOH. 386.It Li QHL_REQUESTS.IOH_WRITES 387.Pq Event 20H , Umask 02H 388Counts number of Quickpath Home Logic write requests from the IOH. 389.It Li QHL_REQUESTS.REMOTE_READS 390.Pq Event 20H , Umask 04H 391Counts number of Quickpath Home Logic read requests from a remote socket. 392.It Li QHL_REQUESTS.REMOTE_WRITES 393.Pq Event 20H , Umask 08H 394Counts number of Quickpath Home Logic write requests from a remote socket. 395.It Li QHL_REQUESTS.LOCAL_READS 396.Pq Event 20H , Umask 10H 397Counts number of Quickpath Home Logic read requests from the local socket. 398.It Li QHL_REQUESTS.LOCAL_WRITES 399.Pq Event 20H , Umask 20H 400Counts number of Quickpath Home Logic write requests from the local socket. 401.It Li QHL_CYCLES_FULL.IOH 402.Pq Event 21H , Umask 01H 403Counts uclk cycles all entries in the Quickpath Home Logic IOH are full. 404.It Li QHL_CYCLES_FULL.REMOTE 405.Pq Event 21H , Umask 02H 406Counts uclk cycles all entries in the Quickpath Home Logic remote tracker 407are full. 408.It Li QHL_CYCLES_FULL.LOCAL 409.Pq Event 21H , Umask 04H 410Counts uclk cycles all entries in the Quickpath Home Logic local tracker are 411full. 412.It Li QHL_CYCLES_NOT_EMPTY.IOH 413.Pq Event 22H , Umask 01H 414Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy. 415.It Li QHL_CYCLES_NOT_EMPTY.REMOTE 416.Pq Event 22H , Umask 02H 417Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is 418busy. 419.It Li QHL_CYCLES_NOT_EMPTY.LOCAL 420.Pq Event 22H , Umask 04H 421Counts uclk cycles all entries in the Quickpath Home Logic local tracker is 422busy. 423.It Li QHL_OCCUPANCY.IOH 424.Pq Event 23H , Umask 01H 425QHL IOH tracker allocate to deallocate read occupancy. 426.It Li QHL_OCCUPANCY.REMOTE 427.Pq Event 23H , Umask 02H 428QHL remote tracker allocate to deallocate read occupancy. 429.It Li QHL_OCCUPANCY.LOCAL 430.Pq Event 23H , Umask 04H 431QHL local tracker allocate to deallocate read occupancy. 432.It Li QHL_ADDRESS_CONFLICTS.2WAY 433.Pq Event 24H , Umask 02H 434Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 435conflicts. The AAT is a structure that tracks requests that are in conflict. 436The requests themselves are in the home tracker entries. The count is 437reported when an AAT entry deallocates. 438.It Li QHL_ADDRESS_CONFLICTS.3WAY 439.Pq Event 24H , Umask 04H 440Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 441conflicts. The AAT is a structure that tracks requests that are in conflict. 442The requests themselves are in the home tracker entries. The count is 443reported when an AAT entry deallocates. 444.It Li QHL_CONFLICT_CYCLES.IOH 445.Pq Event 25H , Umask 01H 446Counts cycles the Quickpath Home Logic IOH Tracker contains two or more 447requests with an address conflict. A max of 3 requests can be in conflict. 448.It Li QHL_CONFLICT_CYCLES.REMOTE 449.Pq Event 25H , Umask 02H 450Counts cycles the Quickpath Home Logic Remote Tracker contains two or more 451requests with an address conflict. A max of 3 requests can be in conflict. 452.It Li QHL_CONFLICT_CYCLES.LOCAL 453.Pq Event 25H , Umask 04H 454Counts cycles the Quickpath Home Logic Local Tracker contains two or more 455requests with an address conflict. A max of 3 requests can be in conflict. 456.It Li QHL_TO_QMC_BYPASS 457.Pq Event 26H , Umask 01H 458Counts number or requests to the Quickpath Memory Controller that bypass the 459Quickpath Home Logic. All local accesses can be bypassed. For remote 460requests, only read requests can be bypassed. 461.It Li QMC_ISOC_FULL.READ.CH0 462.Pq Event 28H , Umask 01H 463Counts cycles all the entries in the DRAM channel 0 high priority queue are 464occupied with isochronous read requests. 465.It Li QMC_ISOC_FULL.READ.CH1 466.Pq Event 28H , Umask 02H 467Counts cycles all the entries in the DRAM channel 1 high priority queue are 468occupied with isochronous read requests. 469.It Li QMC_ISOC_FULL.READ.CH2 470.Pq Event 28H , Umask 04H 471Counts cycles all the entries in the DRAM channel 2 high priority queue are 472occupied with isochronous read requests. 473.It Li QMC_ISOC_FULL.WRITE.CH0 474.Pq Event 28H , Umask 08H 475Counts cycles all the entries in the DRAM channel 0 high priority queue are 476occupied with isochronous write requests. 477.It Li QMC_ISOC_FULL.WRITE.CH1 478.Pq Event 28H , Umask 10H 479Counts cycles all the entries in the DRAM channel 1 high priority queue are 480occupied with isochronous write requests. 481.It Li QMC_ISOC_FULL.WRITE.CH2 482.Pq Event 28H , Umask 20H 483Counts cycles all the entries in the DRAM channel 2 high priority queue are 484occupied with isochronous write requests. 485.It Li QMC_BUSY.READ.CH0 486.Pq Event 29H , Umask 01H 487Counts cycles where Quickpath Memory Controller has at least 1 outstanding 488read request to DRAM channel 0. 489.It Li QMC_BUSY.READ.CH1 490.Pq Event 29H , Umask 02H 491Counts cycles where Quickpath Memory Controller has at least 1 outstanding 492read request to DRAM channel 1. 493.It Li QMC_BUSY.READ.CH2 494.Pq Event 29H , Umask 04H 495Counts cycles where Quickpath Memory Controller has at least 1 outstanding 496read request to DRAM channel 2. 497.It Li QMC_BUSY.WRITE.CH0 498.Pq Event 29H , Umask 08H 499Counts cycles where Quickpath Memory Controller has at least 1 outstanding 500write request to DRAM channel 0. 501.It Li QMC_BUSY.WRITE.CH1 502.Pq Event 29H , Umask 10H 503Counts cycles where Quickpath Memory Controller has at least 1 outstanding 504write request to DRAM channel 1. 505.It Li QMC_BUSY.WRITE.CH2 506.Pq Event 29H , Umask 20H 507Counts cycles where Quickpath Memory Controller has at least 1 outstanding 508write request to DRAM channel 2. 509.It Li QMC_OCCUPANCY.CH0 510.Pq Event 2AH , Umask 01H 511IMC channel 0 normal read request occupancy. 512.It Li QMC_OCCUPANCY.CH1 513.Pq Event 2AH , Umask 02H 514IMC channel 1 normal read request occupancy. 515.It Li QMC_OCCUPANCY.CH2 516.Pq Event 2AH , Umask 04H 517IMC channel 2 normal read request occupancy. 518.It Li QMC_OCCUPANCY.ANY 519.Pq Event 2AH , Umask 07H 520Normal read request occupancy for any channel. 521.It Li QMC_ISSOC_OCCUPANCY.CH0 522.Pq Event 2BH , Umask 01H 523IMC channel 0 issoc read request occupancy. 524.It Li QMC_ISSOC_OCCUPANCY.CH1 525.Pq Event 2BH , Umask 02H 526IMC channel 1 issoc read request occupancy. 527.It Li QMC_ISSOC_OCCUPANCY.CH2 528.Pq Event 2BH , Umask 04H 529IMC channel 2 issoc read request occupancy. 530.It Li QMC_ISSOC_READS.ANY 531.Pq Event 2BH , Umask 07H 532IMC issoc read request occupancy. 533.It Li QMC_NORMAL_READS.CH0 534.Pq Event 2CH , Umask 01H 535Counts the number of Quickpath Memory Controller channel 0 medium and low 536priority read requests. The QMC channel 0 normal read occupancy divided by 537this count provides the average QMC channel 0 read latency. 538.It Li QMC_NORMAL_READS.CH1 539.Pq Event 2CH , Umask 02H 540Counts the number of Quickpath Memory Controller channel 1 medium and low 541priority read requests. The QMC channel 1 normal read occupancy divided by 542this count provides the average QMC channel 1 read latency. 543.It Li QMC_NORMAL_READS.CH2 544.Pq Event 2CH , Umask 04H 545Counts the number of Quickpath Memory Controller channel 2 medium and low 546priority read requests. The QMC channel 2 normal read occupancy divided by 547this count provides the average QMC channel 2 read latency. 548.It Li QMC_NORMAL_READS.ANY 549.Pq Event 2CH , Umask 07H 550Counts the number of Quickpath Memory Controller medium and low priority 551read requests. The QMC normal read occupancy divided by this count provides 552the average QMC read latency. 553.It Li QMC_HIGH_PRIORITY_READS.CH0 554.Pq Event 2DH , Umask 01H 555Counts the number of Quickpath Memory Controller channel 0 high priority 556isochronous read requests. 557.It Li QMC_HIGH_PRIORITY_READS.CH1 558.Pq Event 2DH , Umask 02H 559Counts the number of Quickpath Memory Controller channel 1 high priority 560isochronous read requests. 561.It Li QMC_HIGH_PRIORITY_READS.CH2 562.Pq Event 2DH , Umask 04H 563Counts the number of Quickpath Memory Controller channel 2 high priority 564isochronous read requests. 565.It Li QMC_HIGH_PRIORITY_READS.ANY 566.Pq Event 2DH , Umask 07H 567Counts the number of Quickpath Memory Controller high priority isochronous 568read requests. 569.It Li QMC_CRITICAL_PRIORITY_READS.CH0 570.Pq Event 2EH , Umask 01H 571Counts the number of Quickpath Memory Controller channel 0 critical priority 572isochronous read requests. 573.It Li QMC_CRITICAL_PRIORITY_READS.CH1 574.Pq Event 2EH , Umask 02H 575Counts the number of Quickpath Memory Controller channel 1 critical priority 576isochronous read requests. 577.It Li QMC_CRITICAL_PRIORITY_READS.CH2 578.Pq Event 2EH , Umask 04H 579Counts the number of Quickpath Memory Controller channel 2 critical priority 580isochronous read requests. 581.It Li QMC_CRITICAL_PRIORITY_READS.ANY 582.Pq Event 2EH , Umask 07H 583Counts the number of Quickpath Memory Controller critical priority 584isochronous read requests. 585.It Li QMC_WRITES.FULL.CH0 586.Pq Event 2FH , Umask 01H 587Counts number of full cache line writes to DRAM channel 0. 588.It Li QMC_WRITES.FULL.CH1 589.Pq Event 2FH , Umask 02H 590Counts number of full cache line writes to DRAM channel 1. 591.It Li QMC_WRITES.FULL.CH2 592.Pq Event 2FH , Umask 04H 593Counts number of full cache line writes to DRAM channel 2. 594.It Li QMC_WRITES.FULL.ANY 595.Pq Event 2FH , Umask 07H 596Counts number of full cache line writes to DRAM. 597.It Li QMC_WRITES.PARTIAL.CH0 598.Pq Event 2FH , Umask 08H 599Counts number of partial cache line writes to DRAM channel 0. 600.It Li QMC_WRITES.PARTIAL.CH1 601.Pq Event 2FH , Umask 10H 602Counts number of partial cache line writes to DRAM channel 1. 603.It Li QMC_WRITES.PARTIAL.CH2 604.Pq Event 2FH , Umask 20H 605Counts number of partial cache line writes to DRAM channel 2. 606.It Li QMC_WRITES.PARTIAL.ANY 607.Pq Event 2FH , Umask 38H 608Counts number of partial cache line writes to DRAM. 609.It Li QMC_CANCEL.CH0 610.Pq Event 30H , Umask 01H 611Counts number of DRAM channel 0 cancel requests. 612.It Li QMC_CANCEL.CH1 613.Pq Event 30H , Umask 02H 614Counts number of DRAM channel 1 cancel requests. 615.It Li QMC_CANCEL.CH2 616.Pq Event 30H , Umask 04H 617Counts number of DRAM channel 2 cancel requests. 618.It Li QMC_CANCEL.ANY 619.Pq Event 30H , Umask 07H 620Counts number of DRAM cancel requests. 621.It Li QMC_PRIORITY_UPDATES.CH0 622.Pq Event 31H , Umask 01H 623Counts number of DRAM channel 0 priority updates. A priority update occurs 624when an ISOC high or critical request is received by the QHL and there is a 625matching request with normal priority that has already been issued to the 626QMC. In this instance, the QHL will send a priority update to QMC to 627expedite the request. 628.It Li QMC_PRIORITY_UPDATES.CH1 629.Pq Event 31H , Umask 02H 630Counts number of DRAM channel 1 priority updates. A priority update occurs 631when an ISOC high or critical request is received by the QHL and there is a 632matching request with normal priority that has already been issued to the 633QMC. In this instance, the QHL will send a priority update to QMC to 634expedite the request. 635.It Li QMC_PRIORITY_UPDATES.CH2 636.Pq Event 31H , Umask 04H 637Counts number of DRAM channel 2 priority updates. A priority update occurs 638when an ISOC high or critical request is received by the QHL and there is a 639matching request with normal priority that has already been issued to the 640QMC. In this instance, the QHL will send a priority update to QMC to 641expedite the request. 642.It Li QMC_PRIORITY_UPDATES.ANY 643.Pq Event 31H , Umask 07H 644Counts number of DRAM priority updates. A priority update occurs when an 645ISOC high or critical request is received by the QHL and there is a matching 646request with normal priority that has already been issued to the QMC. In 647this instance, the QHL will send a priority update to QMC to expedite the 648request. 649.It Li IMC_RETRY.CH0 650.Pq Event 32H , Umask 01H 651Counts number of IMC DRAM channel 0 retries. DRAM retry only occurs when 652configured in RAS mode. 653.It Li IMC_RETRY.CH1 654.Pq Event 32H , Umask 02H 655Counts number of IMC DRAM channel 1 retries. DRAM retry only occurs when 656configured in RAS mode. 657.It Li IMC_RETRY.CH2 658.Pq Event 32H , Umask 04H 659Counts number of IMC DRAM channel 2 retries. DRAM retry only occurs when 660configured in RAS mode. 661.It Li IMC_RETRY.ANY 662.Pq Event 32H , Umask 07H 663Counts number of IMC DRAM retries from any channel. DRAM retry only occurs 664when configured in RAS mode. 665.It Li QHL_FRC_ACK_CNFLTS.IOH 666.Pq Event 33H , Umask 01H 667Counts number of Force Acknowledge Conflict messages sent by the Quickpath 668Home Logic to the IOH. 669.It Li QHL_FRC_ACK_CNFLTS.REMOTE 670.Pq Event 33H , Umask 02H 671Counts number of Force Acknowledge Conflict messages sent by the Quickpath 672Home Logic to the remote home. 673.It Li QHL_FRC_ACK_CNFLTS.LOCAL 674.Pq Event 33H , Umask 04H 675Counts number of Force Acknowledge Conflict messages sent by the Quickpath 676Home Logic to the local home. 677.It Li QHL_FRC_ACK_CNFLTS.ANY 678.Pq Event 33H , Umask 07H 679Counts number of Force Acknowledge Conflict messages sent by the Quickpath 680Home Logic. 681.It Li QHL_SLEEPS.IOH_ORDER 682.Pq Event 34H , Umask 01H 683Counts number of occurrences a request was put to sleep due to IOH ordering 684(write after read) conflicts. While in the sleep state, the request is not 685eligible to be scheduled to the QMC. 686.It Li QHL_SLEEPS.REMOTE_ORDER 687.Pq Event 34H , Umask 02H 688Counts number of occurrences a request was put to sleep due to remote socket 689ordering (write after read) conflicts. While in the sleep state, the request 690is not eligible to be scheduled to the QMC. 691.It Li QHL_SLEEPS.LOCAL_ORDER 692.Pq Event 34H , Umask 04H 693Counts number of occurrences a request was put to sleep due to local socket 694ordering (write after read) conflicts. While in the sleep state, the request 695is not eligible to be scheduled to the QMC. 696.It Li QHL_SLEEPS.IOH_CONFLICT 697.Pq Event 34H , Umask 08H 698Counts number of occurrences a request was put to sleep due to IOH address 699conflicts. While in the sleep state, the request is not eligible to be 700scheduled to the QMC. 701.It Li QHL_SLEEPS.REMOTE_CONFLICT 702.Pq Event 34H , Umask 10H 703Counts number of occurrences a request was put to sleep due to remote socket 704address conflicts. While in the sleep state, the request is not eligible to 705be scheduled to the QMC. 706.It Li QHL_SLEEPS.LOCAL_CONFLICT 707.Pq Event 34H , Umask 20H 708Counts number of occurrences a request was put to sleep due to local socket 709address conflicts. While in the sleep state, the request is not eligible to 710be scheduled to the QMC. 711.It Li ADDR_OPCODE_MATCH.IOH 712.Pq Event 35H , Umask 01H 713Counts number of requests from the IOH, address/opcode of request is 714qualified by mask value written to MSR 396H. The following mask values are 715supported: 7160: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 71740001D00_00000000H:RSPIWB 718Match opcode/address by writing MSR 396H with mask supported mask value. 719.It Li ADDR_OPCODE_MATCH.REMOTE 720.Pq Event 35H , Umask 02H 721Counts number of requests from the remote socket, address/opcode of request 722is qualified by mask value written to MSR 396H. The following mask values 723are supported: 7240: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 72540001D00_00000000H:RSPIWB 726Match opcode/address by writing MSR 396H with mask supported mask value. 727.It Li ADDR_OPCODE_MATCH.LOCAL 728.Pq Event 35H , Umask 04H 729Counts number of requests from the local socket, address/opcode of request 730is qualified by mask value written to MSR 396H. The following mask values 731are supported: 7320: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 73340001D00_00000000H:RSPIWB 734Match opcode/address by writing MSR 396H with mask supported mask value. 735.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 736.Pq Event 40H , Umask 01H 737Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled 738due to lack of a VNA and VN0 credit. Note that this event does not filter 739out when a flit would not have been selected for arbitration because another 740virtual channel is getting arbitrated. 741.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 742.Pq Event 40H , Umask 02H 743Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled 744due to lack of a VNA and VN0 credit. Note that this event does not filter 745out when a flit would not have been selected for arbitration because another 746virtual channel is getting arbitrated. 747.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 748.Pq Event 40H , Umask 04H 749Counts cycles the Quickpath outbound link 0 non-data response virtual 750channel is stalled due to lack of a VNA and VN0 credit. Note that this event 751does not filter out when a flit would not have been selected for arbitration 752because another virtual channel is getting arbitrated. 753.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 754.Pq Event 40H , Umask 08H 755Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled 756due to lack of a VNA and VN0 credit. Note that this event does not filter 757out when a flit would not have been selected for arbitration because another 758virtual channel is getting arbitrated. 759.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 760.Pq Event 40H , Umask 10H 761Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled 762due to lack of a VNA and VN0 credit. Note that this event does not filter 763out when a flit would not have been selected for arbitration because another 764virtual channel is getting arbitrated. 765.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 766.Pq Event 40H , Umask 20H 767Counts cycles the Quickpath outbound link 1 non-data response virtual 768channel is stalled due to lack of a VNA and VN0 credit. Note that this event 769does not filter out when a flit would not have been selected for arbitration 770because another virtual channel is getting arbitrated. 771.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 772.Pq Event 40H , Umask 07H 773Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 774to lack of a VNA and VN0 credit. Note that this event does not filter out 775when a flit would not have been selected for arbitration because another 776virtual channel is getting arbitrated. 777.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 778.Pq Event 40H , Umask 38H 779Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 780to lack of a VNA and VN0 credit. Note that this event does not filter out 781when a flit would not have been selected for arbitration because another 782virtual channel is getting arbitrated. 783.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 784.Pq Event 41H , Umask 01H 785Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is 786stalled due to lack of VNA and VN0 credits. Note that this event does not 787filter out when a flit would not have been selected for arbitration because 788another virtual channel is getting arbitrated. 789.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 790.Pq Event 41H , Umask 02H 791Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual 792channel is stalled due to lack of VNA and VN0 credits. Note that this event 793does not filter out when a flit would not have been selected for arbitration 794because another virtual channel is getting arbitrated. 795.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 796.Pq Event 41H , Umask 04H 797Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual 798channel is stalled due to lack of VNA and VN0 credits. Note that this event 799does not filter out when a flit would not have been selected for arbitration 800because another virtual channel is getting arbitrated. 801.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 802.Pq Event 41H , Umask 08H 803Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is 804stalled due to lack of VNA and VN0 credits. Note that this event does not 805filter out when a flit would not have been selected for arbitration because 806another virtual channel is getting arbitrated. 807.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 808.Pq Event 41H , Umask 10H 809Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual 810channel is stalled due to lack of VNA and VN0 credits. Note that this event 811does not filter out when a flit would not have been selected for arbitration 812because another virtual channel is getting arbitrated. 813.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 814.Pq Event 41H , Umask 20H 815Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual 816channel is stalled due to lack of VNA and VN0 credits. Note that this event 817does not filter out when a flit would not have been selected for arbitration 818because another virtual channel is getting arbitrated. 819.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 820.Pq Event 41H , Umask 07H 821Counts cycles the Quickpath outbound link 0 virtual channels are stalled due 822to lack of VNA and VN0 credits. Note that this event does not filter out 823when a flit would not have been selected for arbitration because another 824virtual channel is getting arbitrated. 825.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 826.Pq Event 41H , Umask 38H 827Counts cycles the Quickpath outbound link 1 virtual channels are stalled due 828to lack of VNA and VN0 credits. Note that this event does not filter out 829when a flit would not have been selected for arbitration because another 830virtual channel is getting arbitrated. 831.It Li QPI_TX_HEADER.FULL.LINK_0 832.Pq Event 42H , Umask 01H 833Number of cycles that the header buffer in the Quickpath Interface outbound 834link 0 is full. 835.It Li QPI_TX_HEADER.BUSY.LINK_0 836.Pq Event 42H , Umask 02H 837Number of cycles that the header buffer in the Quickpath Interface outbound 838link 0 is busy. 839.It Li QPI_TX_HEADER.FULL.LINK_1 840.Pq Event 42H , Umask 04H 841Number of cycles that the header buffer in the Quickpath Interface outbound 842link 1 is full. 843.It Li QPI_TX_HEADER.BUSY.LINK_1 844.Pq Event 42H , Umask 08H 845Number of cycles that the header buffer in the Quickpath Interface outbound 846link 1 is busy. 847.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 848.Pq Event 43H , Umask 01H 849Number of cycles that snoop packets incoming to the Quickpath Interface link 8500 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 851does not have any available entries. 852.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 853.Pq Event 43H , Umask 02H 854Number of cycles that snoop packets incoming to the Quickpath Interface link 8551 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT) 856does not have any available entries. 857.It Li DRAM_OPEN.CH0 858.Pq Event 60H , Umask 01H 859Counts number of DRAM Channel 0 open commands issued either for read or 860write. To read or write data, the referenced DRAM page must first be opened. 861.It Li DRAM_OPEN.CH1 862.Pq Event 60H , Umask 02H 863Counts number of DRAM Channel 1 open commands issued either for read or 864write. To read or write data, the referenced DRAM page must first be opened. 865.It Li DRAM_OPEN.CH2 866.Pq Event 60H , Umask 04H 867Counts number of DRAM Channel 2 open commands issued either for read or 868write. To read or write data, the referenced DRAM page must first be opened. 869.It Li DRAM_PAGE_CLOSE.CH0 870.Pq Event 61H , Umask 01H 871DRAM channel 0 command issued to CLOSE a page due to page idle timer 872expiration. Closing a page is done by issuing a precharge. 873.It Li DRAM_PAGE_CLOSE.CH1 874.Pq Event 61H , Umask 02H 875DRAM channel 1 command issued to CLOSE a page due to page idle timer 876expiration. Closing a page is done by issuing a precharge. 877.It Li DRAM_PAGE_CLOSE.CH2 878.Pq Event 61H , Umask 04H 879DRAM channel 2 command issued to CLOSE a page due to page idle timer 880expiration. Closing a page is done by issuing a precharge. 881.It Li DRAM_PAGE_MISS.CH0 882.Pq Event 62H , Umask 01H 883Counts the number of precharges (PRE) that were issued to DRAM channel 0 884because there was a page miss. A page miss refers to a situation in which a 885page is currently open and another page from the same bank needs to be 886opened. The new page experiences a page miss. Closing of the old page is 887done by issuing a precharge. 888.It Li DRAM_PAGE_MISS.CH1 889.Pq Event 62H , Umask 02H 890Counts the number of precharges (PRE) that were issued to DRAM channel 1 891because there was a page miss. A page miss refers to a situation in which a 892page is currently open and another page from the same bank needs to be 893opened. The new page experiences a page miss. Closing of the old page is 894done by issuing a precharge. 895.It Li DRAM_PAGE_MISS.CH2 896.Pq Event 62H , Umask 04H 897Counts the number of precharges (PRE) that were issued to DRAM channel 2 898because there was a page miss. A page miss refers to a situation in which a 899page is currently open and another page from the same bank needs to be 900opened. The new page experiences a page miss. Closing of the old page is 901done by issuing a precharge. 902.It Li DRAM_READ_CAS.CH0 903.Pq Event 63H , Umask 01H 904Counts the number of times a read CAS command was issued on DRAM channel 0. 905.It Li DRAM_READ_CAS.AUTOPRE_CH0 906.Pq Event 63H , Umask 02H 907Counts the number of times a read CAS command was issued on DRAM channel 0 908where the command issued used the auto-precharge (auto page close) mode. 909.It Li DRAM_READ_CAS.CH1 910.Pq Event 63H , Umask 04H 911Counts the number of times a read CAS command was issued on DRAM channel 1. 912.It Li DRAM_READ_CAS.AUTOPRE_CH1 913.Pq Event 63H , Umask 08H 914Counts the number of times a read CAS command was issued on DRAM channel 1 915where the command issued used the auto-precharge (auto page close) mode. 916.It Li DRAM_READ_CAS.CH2 917.Pq Event 63H , Umask 10H 918Counts the number of times a read CAS command was issued on DRAM channel 2. 919.It Li DRAM_READ_CAS.AUTOPRE_CH2 920.Pq Event 63H , Umask 20H 921Counts the number of times a read CAS command was issued on DRAM channel 2 922where the command issued used the auto-precharge (auto page close) mode. 923.It Li DRAM_WRITE_CAS.CH0 924.Pq Event 64H , Umask 01H 925Counts the number of times a write CAS command was issued on DRAM channel 0. 926.It Li DRAM_WRITE_CAS.AUTOPRE_CH0 927.Pq Event 64H , Umask 02H 928Counts the number of times a write CAS command was issued on DRAM channel 0 929where the command issued used the auto-precharge (auto page close) mode. 930.It Li DRAM_WRITE_CAS.CH1 931.Pq Event 64H , Umask 04H 932Counts the number of times a write CAS command was issued on DRAM channel 1. 933.It Li DRAM_WRITE_CAS.AUTOPRE_CH1 934.Pq Event 64H , Umask 08H 935Counts the number of times a write CAS command was issued on DRAM channel 1 936where the command issued used the auto-precharge (auto page close) mode. 937.It Li DRAM_WRITE_CAS.CH2 938.Pq Event 64H , Umask 10H 939Counts the number of times a write CAS command was issued on DRAM channel 2. 940.It Li DRAM_WRITE_CAS.AUTOPRE_CH2 941.Pq Event 64H , Umask 20H 942Counts the number of times a write CAS command was issued on DRAM channel 2 943where the command issued used the auto-precharge (auto page close) mode. 944.It Li DRAM_REFRESH.CH0 945.Pq Event 65H , Umask 01H 946Counts number of DRAM channel 0 refresh commands. DRAM loses data content 947over time. In order to keep correct data content, the data values have to be 948refreshed periodically. 949.It Li DRAM_REFRESH.CH1 950.Pq Event 65H , Umask 02H 951Counts number of DRAM channel 1 refresh commands. DRAM loses data content 952over time. In order to keep correct data content, the data values have to be 953refreshed periodically. 954.It Li DRAM_REFRESH.CH2 955.Pq Event 65H , Umask 04H 956Counts number of DRAM channel 2 refresh commands. DRAM loses data content 957over time. In order to keep correct data content, the data values have to be 958refreshed periodically. 959.It Li DRAM_PRE_ALL.CH0 960.Pq Event 66H , Umask 01H 961Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close 962all open pages in a rank. PREALL is issued when the DRAM needs to be 963refreshed or needs to go into a power down mode. 964.It Li DRAM_PRE_ALL.CH1 965.Pq Event 66H , Umask 02H 966Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close 967all open pages in a rank. PREALL is issued when the DRAM needs to be 968refreshed or needs to go into a power down mode. 969.It Li DRAM_PRE_ALL.CH2 970.Pq Event 66H , Umask 04H 971Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close 972all open pages in a rank. PREALL is issued when the DRAM needs to be 973refreshed or needs to go into a power down mode. 974.It Li DRAM_THERMAL_THROTTLED 975.Pq Event 67H , Umask 01H 976Uncore cycles DRAM was throttled due to its temperature being above the 977thermal throttling threshold. 978.It Li THERMAL_THROTTLING_TEMP.CORE_0 979.Pq Event 80H , Umask 01H 980Cycles that the PCU records that core 0 is above the thermal throttling 981threshold temperature. 982.It Li THERMAL_THROTTLING_TEMP.CORE_1 983.Pq Event 80H , Umask 02H 984Cycles that the PCU records that core 1 is above the thermal throttling 985threshold temperature. 986.It Li THERMAL_THROTTLING_TEMP.CORE_2 987.Pq Event 80H , Umask 04H 988Cycles that the PCU records that core 2 is above the thermal throttling 989threshold temperature. 990.It Li THERMAL_THROTTLING_TEMP.CORE_3 991.Pq Event 80H , Umask 08H 992Cycles that the PCU records that core 3 is above the thermal throttling 993threshold temperature. 994.It Li THERMAL_THROTTLED_TEMP.CORE_0 995.Pq Event 81H , Umask 01H 996Cycles that the PCU records that core 0 is in the power throttled state due 997to cores temperature being above the thermal throttling threshold. 998.It Li THERMAL_THROTTLED_TEMP.CORE_1 999.Pq Event 81H , Umask 02H 1000Cycles that the PCU records that core 1 is in the power throttled state due 1001to cores temperature being above the thermal throttling threshold. 1002.It Li THERMAL_THROTTLED_TEMP.CORE_2 1003.Pq Event 81H , Umask 04H 1004Cycles that the PCU records that core 2 is in the power throttled state due 1005to cores temperature being above the thermal throttling threshold. 1006.It Li THERMAL_THROTTLED_TEMP.CORE_3 1007.Pq Event 81H , Umask 08H 1008Cycles that the PCU records that core 3 is in the power throttled state due 1009to cores temperature being above the thermal throttling threshold. 1010.It Li PROCHOT_ASSERTION 1011.Pq Event 82H , Umask 01H 1012Number of system assertions of PROCHOT indicating the entire processor has 1013exceeded the thermal limit. 1014.It Li THERMAL_THROTTLING_PROCHOT.CORE_0 1015.Pq Event 83H , Umask 01H 1016Cycles that the PCU records that core 0 is a low power state due to the 1017system asserting PROCHOT the entire processor has exceeded the thermal 1018limit. 1019.It Li THERMAL_THROTTLING_PROCHOT.CORE_1 1020.Pq Event 83H , Umask 02H 1021Cycles that the PCU records that core 1 is a low power state due to the 1022system asserting PROCHOT the entire processor has exceeded the thermal 1023limit. 1024.It Li THERMAL_THROTTLING_PROCHOT.CORE_2 1025.Pq Event 83H , Umask 04H 1026Cycles that the PCU records that core 2 is a low power state due to the 1027system asserting PROCHOT the entire processor has exceeded the thermal 1028limit. 1029.It Li THERMAL_THROTTLING_PROCHOT.CORE_3 1030.Pq Event 83H , Umask 08H 1031Cycles that the PCU records that core 3 is a low power state due to the 1032system asserting PROCHOT the entire processor has exceeded the thermal 1033limit. 1034.It Li TURBO_MODE.CORE_0 1035.Pq Event 84H , Umask 01H 1036Uncore cycles that core 0 is operating in turbo mode. 1037.It Li TURBO_MODE.CORE_1 1038.Pq Event 84H , Umask 02H 1039Uncore cycles that core 1 is operating in turbo mode. 1040.It Li TURBO_MODE.CORE_2 1041.Pq Event 84H , Umask 04H 1042Uncore cycles that core 2 is operating in turbo mode. 1043.It Li TURBO_MODE.CORE_3 1044.Pq Event 84H , Umask 08H 1045Uncore cycles that core 3 is operating in turbo mode. 1046.It Li CYCLES_UNHALTED_L3_FLL_ENABLE 1047.Pq Event 85H , Umask 02H 1048Uncore cycles that at least one core is unhalted and all L3 ways are 1049enabled. 1050.It Li CYCLES_UNHALTED_L3_FLL_DISABLE 1051.Pq Event 86H , Umask 01H 1052Uncore cycles that at least one core is unhalted and all L3 ways are 1053disabled. 1054.El 1055.Sh SEE ALSO 1056.Xr pmc 3 , 1057.Xr pmc.atom 3 , 1058.Xr pmc.core 3 , 1059.Xr pmc.corei7 3 , 1060.Xr pmc.corei7uc 3 , 1061.Xr pmc.iaf 3 , 1062.Xr pmc.k7 3 , 1063.Xr pmc.k8 3 , 1064.Xr pmc.p4 3 , 1065.Xr pmc.p5 3 , 1066.Xr pmc.p6 3 , 1067.Xr pmc.soft 3 , 1068.Xr pmc.tsc 3 , 1069.Xr pmc.ucf 3 , 1070.Xr pmc.westmere 3 , 1071.Xr pmc_cpuinfo 3 , 1072.Xr pmclog 3 , 1073.Xr hwpmc 4 1074.Sh HISTORY 1075The 1076.Nm pmc 1077library first appeared in 1078.Fx 6.0 . 1079.Sh AUTHORS 1080The 1081.Lb libpmc 1082library was written by 1083.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1084