1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd February 25, 2012 27.Dt PMC.WESTMERE 3 28.Os 29.Sh NAME 30.Nm pmc.westmere 31.Nd measurement events for 32.Tn Intel 33.Tn Westmere 34family CPUs 35.Sh LIBRARY 36.Lb libpmc 37.Sh SYNOPSIS 38.In pmc.h 39.Sh DESCRIPTION 40.Tn Intel 41.Tn "Westmere" 42CPUs contain PMCs conforming to version 2 of the 43.Tn Intel 44performance measurement architecture. 45These CPUs may contain up to three classes of PMCs: 46.Bl -tag -width "Li PMC_CLASS_IAP" 47.It Li PMC_CLASS_IAF 48Fixed-function counters that count only one hardware event per counter. 49.It Li PMC_CLASS_IAP 50Programmable counters that may be configured to count one of a defined 51set of hardware events. 52.El 53.Pp 54The number of PMCs available in each class and their widths need to be 55determined at run time by calling 56.Xr pmc_cpuinfo 3 . 57.Pp 58Intel Westmere PMCs are documented in 59.Rs 60.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 61.%T "Volume 3B: System Programming Guide, Part 2" 62.%N "Order Number: 253669-033US" 63.%D December 2009 64.%Q "Intel Corporation" 65.Re 66.Ss WESTMERE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss WESTMERE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li rsp= Ns Ar value 90Configure the Off-core Response bits. 91.Bl -tag -width indent 92.It Li DMND_DATA_RD 93Counts the number of demand and DCU prefetch data reads of full 94and partial cachelines as well as demand data page table entry 95cacheline reads. 96Does not count L2 data read prefetches or 97instruction fetches. 98.It Li DMND_RFO 99Counts the number of demand and DCU prefetch reads for ownership 100(RFO) requests generated by a write to data cacheline. 101Does not count L2 RFO. 102.It Li DMND_IFETCH 103Counts the number of demand and DCU prefetch instruction cacheline 104reads. 105Does not count L2 code read prefetches. 106WB 107Counts the number of writeback (modified to exclusive) transactions. 108.It Li PF_DATA_RD 109Counts the number of data cacheline reads generated by L2 prefetchers. 110.It Li PF_RFO 111Counts the number of RFO requests generated by L2 prefetchers. 112.It Li PF_IFETCH 113Counts the number of code reads generated by L2 prefetchers. 114.It Li OTHER 115Counts one of the following transaction types, including L3 invalidate, 116I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 117lock, unlock, split lock. 118.It Li UNCORE_HIT 119L3 Hit: local or remote home requests that hit L3 cache in the uncore 120with no coherency actions required (snooping). 121.It Li OTHER_CORE_HIT_SNP 122L3 Hit: local or remote home requests that hit L3 cache in the uncore 123and was serviced by another core with a cross core snoop where no modified 124copies were found (clean). 125.It Li OTHER_CORE_HITM 126L3 Hit: local or remote home requests that hit L3 cache in the uncore 127and was serviced by another core with a cross core snoop where modified 128copies were found (HITM). 129.It Li REMOTE_CACHE_FWD 130L3 Miss: local homed requests that missed the L3 cache and was serviced 131by forwarded data following a cross package snoop where no modified 132copies found. (Remote home requests are not counted) 133.It Li REMOTE_DRAM 134L3 Miss: remote home requests that missed the L3 cache and were serviced 135by remote DRAM. 136.It Li LOCAL_DRAM 137L3 Miss: local home requests that missed the L3 cache and were serviced 138by local DRAM. 139.It Li NON_DRAM 140Non-DRAM requests that were serviced by IOH. 141.El 142.It Li cmask= Ns Ar value 143Configure the PMC to increment only if the number of configured 144events measured in a cycle is greater than or equal to 145.Ar value . 146.It Li edge 147Configure the PMC to count the number of de-asserted to asserted 148transitions of the conditions expressed by the other qualifiers. 149If specified, the counter will increment only once whenever a 150condition becomes true, irrespective of the number of clocks during 151which the condition remains true. 152.It Li inv 153Invert the sense of comparison when the 154.Dq Li cmask 155qualifier is present, making the counter increment when the number of 156events per cycle is less than the value specified by the 157.Dq Li cmask 158qualifier. 159.It Li os 160Configure the PMC to count events happening at processor privilege 161level 0. 162.It Li usr 163Configure the PMC to count events occurring at privilege levels 1, 2 164or 3. 165.El 166.Pp 167If neither of the 168.Dq Li os 169or 170.Dq Li usr 171qualifiers are specified, the default is to enable both. 172.Ss Event Specifiers (Programmable PMCs) 173Westmere programmable PMCs support the following events: 174.Bl -tag -width indent 175.It Li LOAD_BLOCK.OVERLAP_STORE 176.Pq Event 03H , Umask 02H 177Loads that partially overlap an earlier store 178.It Li SB_DRAIN.ANY 179.Pq Event 04H , Umask 07H 180All Store buffer stall cycles 181.It Li MISALIGN_MEMORY.STORE 182.Pq Event 05H , Umask 02H 183All store referenced with misaligned address 184.It Li STORE_BLOCKS.AT_RET 185.Pq Event 06H , Umask 04H 186Counts number of loads delayed with at-Retirement block code. 187The following 188loads need to be executed at retirement and wait for all senior stores on 189the same thread to be drained: load splitting across 4K boundary (page 190split), load accessing uncacheable (UC or USWC) memory, load lock, and load 191with page table in UC or USWC memory region. 192.It Li STORE_BLOCKS.L1D_BLOCK 193.Pq Event 06H , Umask 08H 194Cacheable loads delayed with L1D block code 195.It Li PARTIAL_ADDRESS_ALIAS 196.Pq Event 07H , Umask 01H 197Counts false dependency due to partial address aliasing 198.It Li DTLB_LOAD_MISSES.ANY 199.Pq Event 08H , Umask 01H 200Counts all load misses that cause a page walk 201.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 202.Pq Event 08H , Umask 02H 203Counts number of completed page walks due to load miss in the STLB. 204.It Li DTLB_LOAD_MISSES.WALK_CYCLES 205.Pq Event 08H , Umask 04H 206Cycles PMH is busy with a page walk due to a load miss in the STLB. 207.It Li DTLB_LOAD_MISSES.STLB_HIT 208.Pq Event 08H , Umask 10H 209Number of cache load STLB hits 210.It Li DTLB_LOAD_MISSES.PDE_MISS 211.Pq Event 08H , Umask 20H 212Number of DTLB cache load misses where the low part of the linear to 213physical address translation was missed. 214.It Li MEM_INST_RETIRED.LOADS 215.Pq Event 0BH , Umask 01H 216Counts the number of instructions with an architecturally-visible store 217retired on the architected path. 218In conjunction with ld_lat facility 219.It Li MEM_INST_RETIRED.STORES 220.Pq Event 0BH , Umask 02H 221Counts the number of instructions with an architecturally-visible store 222retired on the architected path. 223In conjunction with ld_lat facility 224.It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD 225.Pq Event 0BH , Umask 10H 226Counts the number of instructions exceeding the latency specified with 227ld_lat facility. 228In conjunction with ld_lat facility 229.It Li MEM_STORE_RETIRED.DTLB_MISS 230.Pq Event 0CH , Umask 01H 231The event counts the number of retired stores that missed the DTLB. 232The DTLB miss is not counted if the store operation causes a fault. 233Does not counter prefetches. 234Counts both primary and secondary misses to the TLB 235.It Li UOPS_ISSUED.ANY 236.Pq Event 0EH , Umask 01H 237Counts the number of Uops issued by the Register Allocation Table to the 238Reservation Station, i.e. the UOPs issued from the front end to the back 239end. 240.It Li UOPS_ISSUED.STALLED_CYCLES 241.Pq Event 0EH , Umask 01H 242Counts the number of cycles no Uops issued by the Register Allocation Table 243to the Reservation Station, i.e. the UOPs issued from the front end to the 244back end. 245set invert=1, cmask = 1 246.It Li UOPS_ISSUED.FUSED 247.Pq Event 0EH , Umask 02H 248Counts the number of fused Uops that were issued from the Register 249Allocation Table to the Reservation Station. 250.It Li MEM_UNCORE_RETIRED.LOCAL_HITM 251.Pq Event 0FH , Umask 02H 252Load instructions retired that HIT modified data in sibling core (Precise 253Event) 254.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT 255.Pq Event 0FH , Umask 08H 256Load instructions retired local dram and remote cache HIT data sources 257(Precise Event) 258.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM 259.Pq Event 0FH , Umask 10H 260Load instructions retired with a data source of local DRAM or locally homed 261remote cache HITM (Precise Event) 262.It Li MEM_UNCORE_RETIRED.REMOTE_DRAM 263.Pq Event 0FH , Umask 20H 264Load instructions retired remote DRAM and remote home-remote cache HITM 265(Precise Event) 266.It Li MEM_UNCORE_RETIRED.UNCACHEABLE 267.Pq Event 0FH , Umask 80H 268Load instructions retired I/O (Precise Event) 269.It Li FP_COMP_OPS_EXE.X87 270.Pq Event 10H , Umask 01H 271Counts the number of FP Computational Uops Executed. 272The number of FADD, 273FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer 274DIVs, and IDIVs. 275This event does not distinguish an FADD used in the middle 276of a transcendental flow from a separate FADD instruction. 277.It Li FP_COMP_OPS_EXE.MMX 278.Pq Event 10H , Umask 02H 279Counts number of MMX Uops executed. 280.It Li FP_COMP_OPS_EXE.SSE_FP 281.Pq Event 10H , Umask 04H 282Counts number of SSE and SSE2 FP uops executed. 283.It Li FP_COMP_OPS_EXE.SSE2_INTEGER 284.Pq Event 10H , Umask 08H 285Counts number of SSE2 integer uops executed. 286.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED 287.Pq Event 10H , Umask 10H 288Counts number of SSE FP packed uops executed. 289.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR 290.Pq Event 10H , Umask 20H 291Counts number of SSE FP scalar uops executed. 292.It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION 293.Pq Event 10H , Umask 40H 294Counts number of SSE* FP single precision uops executed. 295.It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION 296.Pq Event 10H , Umask 80H 297Counts number of SSE* FP double precision uops executed. 298.It Li SIMD_INT_128.PACKED_MPY 299.Pq Event 12H , Umask 01H 300Counts number of 128 bit SIMD integer multiply operations. 301.It Li SIMD_INT_128.PACKED_SHIFT 302.Pq Event 12H , Umask 02H 303Counts number of 128 bit SIMD integer shift operations. 304.It Li SIMD_INT_128.PACK 305.Pq Event 12H , Umask 04H 306Counts number of 128 bit SIMD integer pack operations. 307.It Li SIMD_INT_128.UNPACK 308.Pq Event 12H , Umask 08H 309Counts number of 128 bit SIMD integer unpack operations. 310.It Li SIMD_INT_128.PACKED_LOGICAL 311.Pq Event 12H , Umask 10H 312Counts number of 128 bit SIMD integer logical operations. 313.It Li SIMD_INT_128.PACKED_ARITH 314.Pq Event 12H , Umask 20H 315Counts number of 128 bit SIMD integer arithmetic operations. 316.It Li SIMD_INT_128.SHUFFLE_MOVE 317.Pq Event 12H , Umask 40H 318Counts number of 128 bit SIMD integer shuffle and move operations. 319.It Li LOAD_DISPATCH.RS 320.Pq Event 13H , Umask 01H 321Counts number of loads dispatched from the Reservation Station that bypass 322the Memory Order Buffer. 323.It Li LOAD_DISPATCH.RS_DELAYED 324.Pq Event 13H , Umask 02H 325Counts the number of delayed RS dispatches at the stage latch. 326If an RS dispatch can not bypass to LB, it has another chance to dispatch 327from the one-cycle delayed staging latch before it is written into the LB. 328.It Li LOAD_DISPATCH.MOB 329.Pq Event 13H , Umask 04H 330Counts the number of loads dispatched from the Reservation Station to the 331Memory Order Buffer. 332.It Li LOAD_DISPATCH.ANY 333.Pq Event 13H , Umask 07H 334Counts all loads dispatched from the Reservation Station. 335.It Li ARITH.CYCLES_DIV_BUSY 336.Pq Event 14H , Umask 01H 337Counts the number of cycles the divider is busy executing divide or square 338root operations. 339The divide can be integer, X87 or Streaming SIMD Extensions (SSE). 340The square root operation can be either X87 or SSE. 341Set 'edge =1, invert=1, cmask=1' to count the number of divides. 342Count may be incorrect When SMT is on 343.It Li ARITH.MUL 344.Pq Event 14H , Umask 02H 345Counts the number of multiply operations executed. 346This includes integer as 347well as floating point multiply operations but excludes DPPS mul and MPSAD. 348Count may be incorrect When SMT is on 349.It Li INST_QUEUE_WRITES 350.Pq Event 17H , Umask 01H 351Counts the number of instructions written into the instruction queue every 352cycle. 353.It Li INST_DECODED.DEC0 354.Pq Event 18H , Umask 01H 355Counts number of instructions that require decoder 0 to be decoded. 356Usually, this means that the instruction maps to more than 1 uop 357.It Li TWO_UOP_INSTS_DECODED 358.Pq Event 19H , Umask 01H 359An instruction that generates two uops was decoded 360.It Li INST_QUEUE_WRITE_CYCLES 361.Pq Event 1EH , Umask 01H 362This event counts the number of cycles during which instructions are written 363to the instruction queue. 364Dividing this counter by the number of 365instructions written to the instruction queue (INST_QUEUE_WRITES) yields the 366average number of instructions decoded each cycle. 367If this number is less 368than four and the pipe stalls, this indicates that the decoder is failing to 369decode enough instructions per cycle to sustain the 4-wide pipeline. 370If SSE* instructions that are 6 bytes or longer arrive one after another, 371then front end throughput may limit execution speed. 372In such case, 373.It Li LSD_OVERFLOW 374.Pq Event 20H , Umask 01H 375Number of loops that can not stream from the instruction queue. 376.It Li L2_RQSTS.LD_HIT 377.Pq Event 24H , Umask 01H 378Counts number of loads that hit the L2 cache. 379L2 loads include both L1D demand misses as well as L1D prefetches. 380L2 loads can be rejected for various reasons. 381Only non rejected loads are counted. 382.It Li L2_RQSTS.LD_MISS 383.Pq Event 24H , Umask 02H 384Counts the number of loads that miss the L2 cache. 385L2 loads include both L1D demand misses as well as L1D prefetches. 386.It Li L2_RQSTS.LOADS 387.Pq Event 24H , Umask 03H 388Counts all L2 load requests. 389L2 loads include both L1D demand misses as well as L1D prefetches. 390.It Li L2_RQSTS.RFO_HIT 391.Pq Event 24H , Umask 04H 392Counts the number of store RFO requests that hit the L2 cache. 393L2 RFO requests include both L1D demand RFO misses as well as L1D RFO 394prefetches. 395Count includes WC memory requests, where the data is not fetched but the 396permission to write the line is required. 397.It Li L2_RQSTS.RFO_MISS 398.Pq Event 24H , Umask 08H 399Counts the number of store RFO requests that miss the L2 cache. 400L2 RFO requests include both L1D demand RFO misses as well as L1D RFO 401prefetches. 402.It Li L2_RQSTS.RFOS 403.Pq Event 24H , Umask 0CH 404Counts all L2 store RFO requests. 405L2 RFO requests include both L1D demand 406RFO misses as well as L1D RFO prefetches. 407.It Li L2_RQSTS.IFETCH_HIT 408.Pq Event 24H , Umask 10H 409Counts number of instruction fetches that hit the L2 cache. 410L2 instruction fetches include both L1I demand misses as well as L1I 411instruction prefetches. 412.It Li L2_RQSTS.IFETCH_MISS 413.Pq Event 24H , Umask 20H 414Counts number of instruction fetches that miss the L2 cache. 415L2 instruction fetches include both L1I demand misses as well as L1I 416instruction prefetches. 417.It Li L2_RQSTS.IFETCHES 418.Pq Event 24H , Umask 30H 419Counts all instruction fetches. 420L2 instruction fetches include both L1I 421demand misses as well as L1I instruction prefetches. 422.It Li L2_RQSTS.PREFETCH_HIT 423.Pq Event 24H , Umask 40H 424Counts L2 prefetch hits for both code and data. 425.It Li L2_RQSTS.PREFETCH_MISS 426.Pq Event 24H , Umask 80H 427Counts L2 prefetch misses for both code and data. 428.It Li L2_RQSTS.PREFETCHES 429.Pq Event 24H , Umask C0H 430Counts all L2 prefetches for both code and data. 431.It Li L2_RQSTS.MISS 432.Pq Event 24H , Umask AAH 433Counts all L2 misses for both code and data. 434.It Li L2_RQSTS.REFERENCES 435.Pq Event 24H , Umask FFH 436Counts all L2 requests for both code and data. 437.It Li L2_DATA_RQSTS.DEMAND.I_STATE 438.Pq Event 26H , Umask 01H 439Counts number of L2 data demand loads where the cache line to be loaded is 440in the I (invalid) state, i.e. a cache miss. 441L2 demand loads are both L1D demand misses and L1D prefetches. 442.It Li L2_DATA_RQSTS.DEMAND.S_STATE 443.Pq Event 26H , Umask 02H 444Counts number of L2 data demand loads where the cache line to be loaded is 445in the S (shared) state. 446L2 demand loads are both L1D demand misses and L1D 447prefetches. 448.It Li L2_DATA_RQSTS.DEMAND.E_STATE 449.Pq Event 26H , Umask 04H 450Counts number of L2 data demand loads where the cache line to be loaded is 451in the E (exclusive) state. 452L2 demand loads are both L1D demand misses and 453L1D prefetches. 454.It Li L2_DATA_RQSTS.DEMAND.M_STATE 455.Pq Event 26H , Umask 08H 456Counts number of L2 data demand loads where the cache line to be loaded is 457in the M (modified) state. 458L2 demand loads are both L1D demand misses and 459L1D prefetches. 460.It Li L2_DATA_RQSTS.DEMAND.MESI 461.Pq Event 26H , Umask 0FH 462Counts all L2 data demand requests. 463L2 demand loads are both L1D demand 464misses and L1D prefetches. 465.It Li L2_DATA_RQSTS.PREFETCH.I_STATE 466.Pq Event 26H , Umask 10H 467Counts number of L2 prefetch data loads where the cache line to be loaded is 468in the I (invalid) state, i.e. a cache miss. 469.It Li L2_DATA_RQSTS.PREFETCH.S_STATE 470.Pq Event 26H , Umask 20H 471Counts number of L2 prefetch data loads where the cache line to be loaded is 472in the S (shared) state. 473A prefetch RFO will miss on an S state line, while 474a prefetch read will hit on an S state line. 475.It Li L2_DATA_RQSTS.PREFETCH.E_STATE 476.Pq Event 26H , Umask 40H 477Counts number of L2 prefetch data loads where the cache line to be loaded is 478in the E (exclusive) state. 479.It Li L2_DATA_RQSTS.PREFETCH.M_STATE 480.Pq Event 26H , Umask 80H 481Counts number of L2 prefetch data loads where the cache line to be loaded is 482in the M (modified) state. 483.It Li L2_DATA_RQSTS.PREFETCH.MESI 484.Pq Event 26H , Umask F0H 485Counts all L2 prefetch requests. 486.It Li L2_DATA_RQSTS.ANY 487.Pq Event 26H , Umask FFH 488Counts all L2 data requests. 489.It Li L2_WRITE.RFO.I_STATE 490.Pq Event 27H , Umask 01H 491Counts number of L2 demand store RFO requests where the cache line to be 492loaded is in the I (invalid) state, i.e, a cache miss. 493The L1D prefetcher 494does not issue a RFO prefetch. 495This is a demand RFO request 496.It Li L2_WRITE.RFO.S_STATE 497.Pq Event 27H , Umask 02H 498Counts number of L2 store RFO requests where the cache line to be loaded is 499in the S (shared) state. 500The L1D prefetcher does not issue a RFO prefetch. 501This is a demand RFO request. 502.It Li L2_WRITE.RFO.M_STATE 503.Pq Event 27H , Umask 08H 504Counts number of L2 store RFO requests where the cache line to be loaded is 505in the M (modified) state. 506The L1D prefetcher does not issue a RFO prefetch. 507This is a demand RFO request. 508.It Li L2_WRITE.RFO.HIT 509.Pq Event 27H , Umask 0EH 510Counts number of L2 store RFO requests where the cache line to be loaded is 511in either the S, E or M states. 512The L1D prefetcher does not issue a RFO 513prefetch. 514This is a demand RFO request 515.It Li L2_WRITE.RFO.MESI 516.Pq Event 27H , Umask 0FH 517Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO 518prefetch. 519This is a demand RFO request. 520.It Li L2_WRITE.LOCK.I_STATE 521.Pq Event 27H , Umask 10H 522Counts number of L2 demand lock RFO requests where the cache line to be 523loaded is in the I (invalid) state, i.e. a cache miss. 524.It Li L2_WRITE.LOCK.S_STATE 525.Pq Event 27H , Umask 20H 526Counts number of L2 lock RFO requests where the cache line to be loaded is 527in the S (shared) state. 528.It Li L2_WRITE.LOCK.E_STATE 529.Pq Event 27H , Umask 40H 530Counts number of L2 demand lock RFO requests where the cache line to be 531loaded is in the E (exclusive) state. 532.It Li L2_WRITE.LOCK.M_STATE 533.Pq Event 27H , Umask 80H 534Counts number of L2 demand lock RFO requests where the cache line to be 535loaded is in the M (modified) state. 536.It Li L2_WRITE.LOCK.HIT 537.Pq Event 27H , Umask E0H 538Counts number of L2 demand lock RFO requests where the cache line to be 539loaded is in either the S, E, or M state. 540.It Li L2_WRITE.LOCK.MESI 541.Pq Event 27H , Umask F0H 542Counts all L2 demand lock RFO requests. 543.It Li L1D_WB_L2.I_STATE 544.Pq Event 28H , Umask 01H 545Counts number of L1 writebacks to the L2 where the cache line to be written 546is in the I (invalid) state, i.e. a cache miss. 547.It Li L1D_WB_L2.S_STATE 548.Pq Event 28H , Umask 02H 549Counts number of L1 writebacks to the L2 where the cache line to be written 550is in the S state. 551.It Li L1D_WB_L2.E_STATE 552.Pq Event 28H , Umask 04H 553Counts number of L1 writebacks to the L2 where the cache line to be written 554is in the E (exclusive) state. 555.It Li L1D_WB_L2.M_STATE 556.Pq Event 28H , Umask 08H 557Counts number of L1 writebacks to the L2 where the cache line to be written 558is in the M (modified) state. 559.It Li L1D_WB_L2.MESI 560.Pq Event 28H , Umask 0FH 561Counts all L1 writebacks to the L2. 562.It Li L3_LAT_CACHE.REFERENCE 563.Pq Event 2EH , Umask 02H 564Counts uncore Last Level Cache references. 565Because cache hierarchy, cache 566sizes and other implementation-specific characteristics; value comparison to 567estimate performance differences is not recommended. 568See Table A-1. 569.It Li L3_LAT_CACHE.MISS 570.Pq Event 2EH , Umask 01H 571Counts uncore Last Level Cache misses. 572Because cache hierarchy, cache sizes 573and other implementation-specific characteristics; value comparison to 574estimate performance differences is not recommended. 575See Table A-1. 576.It Li CPU_CLK_UNHALTED.THREAD_P 577.Pq Event 3CH , Umask 00H 578Counts the number of thread cycles while the thread is not in a halt state. 579The thread enters the halt state when it is running the HLT instruction. 580The core frequency may change from time to time due to power or thermal 581throttling. 582see Table A-1 583.It Li CPU_CLK_UNHALTED.REF_P 584.Pq Event 3CH , Umask 01H 585Increments at the frequency of TSC when not halted. 586see Table A-1 587.It Li DTLB_MISSES.ANY 588.Pq Event 49H , Umask 01H 589Counts the number of misses in the STLB which causes a page walk. 590.It Li DTLB_MISSES.WALK_COMPLETED 591.Pq Event 49H , Umask 02H 592Counts number of misses in the STLB which resulted in a completed page walk. 593.It Li DTLB_MISSES.WALK_CYCLES 594.Pq Event 49H , Umask 04H 595Counts cycles of page walk due to misses in the STLB. 596.It Li DTLB_MISSES.STLB_HIT 597.Pq Event 49H , Umask 10H 598Counts the number of DTLB first level misses that hit in the second level 599TLB. 600This event is only relevant if the core contains multiple DTLB levels. 601.It Li DTLB_MISSES.LARGE_WALK_COMPLETED 602.Pq Event 49H , Umask 80H 603Counts number of completed large page walks due to misses in the STLB. 604.It Li LOAD_HIT_PRE 605.Pq Event 4CH , Umask 01H 606Counts load operations sent to the L1 data cache while a previous SSE 607prefetch instruction to the same cache line has started prefetching but has 608not yet finished. 609.It Li L1D_PREFETCH.REQUESTS 610.Pq Event 4EH , Umask 01H 611Counts number of hardware prefetch requests dispatched out of the prefetch 612FIFO. 613.It Li L1D_PREFETCH.MISS 614.Pq Event 4EH , Umask 02H 615Counts number of hardware prefetch requests that miss the L1D. 616There are two 617prefetchers in the L1D. 618A streamer, which predicts lines sequentially after 619this one should be fetched, and the IP prefetcher that remembers access 620patterns for the current instruction. 621The streamer prefetcher stops on an 622L1D hit, while the IP prefetcher does not. 623.It Li L1D_PREFETCH.TRIGGERS 624.Pq Event 4EH , Umask 04H 625Counts number of prefetch requests triggered by the Finite State Machine and 626pushed into the prefetch FIFO. 627Some of the prefetch requests are dropped due 628to overwrites or competition between the IP index prefetcher and streamer 629prefetcher. 630The prefetch FIFO contains 4 entries. 631.It Li EPT.WALK_CYCLES 632.Pq Event 4FH , Umask 10H 633Counts Extended Page walk cycles. 634.It Li L1D.REPL 635.Pq Event 51H , Umask 01H 636Counts the number of lines brought into the L1 data cache. 637Counter 0, 1 only. 638.It Li L1D.M_REPL 639.Pq Event 51H , Umask 02H 640Counts the number of modified lines brought into the L1 data cache. 641Counter 0, 1 only. 642.It Li L1D.M_EVICT 643.Pq Event 51H , Umask 04H 644Counts the number of modified lines evicted from the L1 data cache due to 645replacement. 646Counter 0, 1 only. 647.It Li L1D.M_SNOOP_EVICT 648.Pq Event 51H , Umask 08H 649Counts the number of modified lines evicted from the L1 data cache due to 650snoop HITM intervention. 651Counter 0, 1 only 652.It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT 653.Pq Event 52H , Umask 01H 654Counts the number of cacheable load lock speculated instructions accepted 655into the fill buffer. 656.It Li L1D_CACHE_LOCK_FB_HIT 657.Pq Event 53H , Umask 01H 658Counts the number of cacheable load lock speculated or retired instructions 659accepted into the fill buffer. 660.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA 661.Pq Event 60H , Umask 01H 662Counts weighted cycles of offcore demand data read requests. 663Does not include L2 prefetch requests. 664Counter 0. 665.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE 666.Pq Event 60H , Umask 02H 667Counts weighted cycles of offcore demand code read requests. 668Does not include L2 prefetch requests. 669Counter 0. 670.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO 671.Pq Event 60H , Umask 04H 672Counts weighted cycles of offcore demand RFO requests. 673Does not include L2 prefetch requests. 674Counter 0. 675.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 676.Pq Event 60H , Umask 08H 677Counts weighted cycles of offcore read requests of any kind. 678Include L2 prefetch requests. 679Counter 0. 680.It Li CACHE_LOCK_CYCLES.L1D_L2 681.Pq Event 63H , Umask 01H 682Cycle count during which the L1D and L2 are locked. 683A lock is asserted when 684there is a locked memory access, due to uncacheable memory, a locked 685operation that spans two cache lines, or a page walk from an uncacheable 686page table. 687Counter 0, 1 only. 688L1D and L2 locks have a very high performance penalty and 689it is highly recommended to avoid such accesses. 690.It Li CACHE_LOCK_CYCLES.L1D 691.Pq Event 63H , Umask 02H 692Counts the number of cycles that cacheline in the L1 data cache unit is 693locked. 694Counter 0, 1 only. 695.It Li IO_TRANSACTIONS 696.Pq Event 6CH , Umask 01H 697Counts the number of completed I/O transactions. 698.It Li L1I.HITS 699.Pq Event 80H , Umask 01H 700Counts all instruction fetches that hit the L1 instruction cache. 701.It Li L1I.MISSES 702.Pq Event 80H , Umask 02H 703Counts all instruction fetches that miss the L1I cache. 704This includes 705instruction cache misses, streaming buffer misses, victim cache misses and 706uncacheable fetches. 707An instruction fetch miss is counted only once and not 708once for every cycle it is outstanding. 709.It Li L1I.READS 710.Pq Event 80H , Umask 03H 711Counts all instruction fetches, including uncacheable fetches that bypass 712the L1I. 713.It Li L1I.CYCLES_STALLED 714.Pq Event 80H , Umask 04H 715Cycle counts for which an instruction fetch stalls due to a L1I cache miss, 716ITLB miss or ITLB fault. 717.It Li LARGE_ITLB.HIT 718.Pq Event 82H , Umask 01H 719Counts number of large ITLB hits. 720.It Li ITLB_MISSES.ANY 721.Pq Event 85H , Umask 01H 722Counts the number of misses in all levels of the ITLB which causes a page 723walk. 724.It Li ITLB_MISSES.WALK_COMPLETED 725.Pq Event 85H , Umask 02H 726Counts number of misses in all levels of the ITLB which resulted in a 727completed page walk. 728.It Li ITLB_MISSES.WALK_CYCLES 729.Pq Event 85H , Umask 04H 730Counts ITLB miss page walk cycles. 731.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 732.Pq Event 85H , Umask 80H 733Counts number of completed large page walks due to misses in the STLB. 734.It Li ILD_STALL.LCP 735.Pq Event 87H , Umask 01H 736Cycles Instruction Length Decoder stalls due to length changing prefixes: 73766, 67 or REX.W (for EM64T) instructions which change the length of the 738decoded instruction. 739.It Li ILD_STALL.MRU 740.Pq Event 87H , Umask 02H 741Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) 742Most Recently Used (MRU) bypass. 743.It Li ILD_STALL.IQ_FULL 744.Pq Event 87H , Umask 04H 745Stall cycles due to a full instruction queue. 746.It Li ILD_STALL.REGEN 747.Pq Event 87H , Umask 08H 748Counts the number of regen stalls. 749.It Li ILD_STALL.ANY 750.Pq Event 87H , Umask 0FH 751Counts any cycles the Instruction Length Decoder is stalled. 752.It Li BR_INST_EXEC.COND 753.Pq Event 88H , Umask 01H 754Counts the number of conditional near branch instructions executed, but not 755necessarily retired. 756.It Li BR_INST_EXEC.DIRECT 757.Pq Event 88H , Umask 02H 758Counts all unconditional near branch instructions excluding calls and 759indirect branches. 760.It Li BR_INST_EXEC.INDIRECT_NON_CALL 761.Pq Event 88H , Umask 04H 762Counts the number of executed indirect near branch instructions that are not 763calls. 764.It Li BR_INST_EXEC.NON_CALLS 765.Pq Event 88H , Umask 07H 766Counts all non call near branch instructions executed, but not necessarily 767retired. 768.It Li BR_INST_EXEC.RETURN_NEAR 769.Pq Event 88H , Umask 08H 770Counts indirect near branches that have a return mnemonic. 771.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 772.Pq Event 88H , Umask 10H 773Counts unconditional near call branch instructions, excluding non call 774branch, executed. 775.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 776.Pq Event 88H , Umask 20H 777Counts indirect near calls, including both register and memory indirect, 778executed. 779.It Li BR_INST_EXEC.NEAR_CALLS 780.Pq Event 88H , Umask 30H 781Counts all near call branches executed, but not necessarily retired. 782.It Li BR_INST_EXEC.TAKEN 783.Pq Event 88H , Umask 40H 784Counts taken near branches executed, but not necessarily retired. 785.It Li BR_INST_EXEC.ANY 786.Pq Event 88H , Umask 7FH 787Counts all near executed branches (not necessarily retired). 788This includes only instructions and not micro-op branches. 789Frequent branching is not necessarily a major performance issue. 790However frequent branch mispredictions may be a problem. 791.It Li BR_MISP_EXEC.COND 792.Pq Event 89H , Umask 01H 793Counts the number of mispredicted conditional near branch instructions 794executed, but not necessarily retired. 795.It Li BR_MISP_EXEC.DIRECT 796.Pq Event 89H , Umask 02H 797Counts mispredicted macro unconditional near branch instructions, excluding 798calls and indirect branches (should always be 0). 799.It Li BR_MISP_EXEC.INDIRECT_NON_CALL 800.Pq Event 89H , Umask 04H 801Counts the number of executed mispredicted indirect near branch instructions 802that are not calls. 803.It Li BR_MISP_EXEC.NON_CALLS 804.Pq Event 89H , Umask 07H 805Counts mispredicted non call near branches executed, but not necessarily 806retired. 807.It Li BR_MISP_EXEC.RETURN_NEAR 808.Pq Event 89H , Umask 08H 809Counts mispredicted indirect branches that have a rear return mnemonic. 810.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 811.Pq Event 89H , Umask 10H 812Counts mispredicted non-indirect near calls executed, (should always be 0). 813.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 814.Pq Event 89H , Umask 20H 815Counts mispredicted indirect near calls executed, including both register 816and memory indirect. 817.It Li BR_MISP_EXEC.NEAR_CALLS 818.Pq Event 89H , Umask 30H 819Counts all mispredicted near call branches executed, but not necessarily 820retired. 821.It Li BR_MISP_EXEC.TAKEN 822.Pq Event 89H , Umask 40H 823Counts executed mispredicted near branches that are taken, but not 824necessarily retired. 825.It Li BR_MISP_EXEC.ANY 826.Pq Event 89H , Umask 7FH 827Counts the number of mispredicted near branch instructions that were 828executed, but not necessarily retired. 829.It Li RESOURCE_STALLS.ANY 830.Pq Event A2H , Umask 01H 831Counts the number of Allocator resource related stalls. 832Includes register renaming buffer entries, memory buffer entries. 833In addition to resource related stalls, this event counts some other events. 834Includes stalls arising 835during branch misprediction recovery, such as if retirement of the 836mispredicted branch is delayed and stalls arising while store buffer is 837draining from synchronizing operations. 838Does not include stalls due to SuperQ (off core) queue full, too many cache 839misses, etc. 840.It Li RESOURCE_STALLS.LOAD 841.Pq Event A2H , Umask 02H 842Counts the cycles of stall due to lack of load buffer for load operation. 843.It Li RESOURCE_STALLS.RS_FULL 844.Pq Event A2H , Umask 04H 845This event counts the number of cycles when the number of instructions in 846the pipeline waiting for execution reaches the limit the processor can 847handle. 848A high count of this event indicates that there are long latency 849operations in the pipe (possibly load and store operations that miss the L2 850cache, or instructions dependent upon instructions further down the pipeline 851that have yet to retire. 852When RS is full, new instructions can not enter the reservation station and 853start execution. 854.It Li RESOURCE_STALLS.STORE 855.Pq Event A2H , Umask 08H 856This event counts the number of cycles that a resource related stall will 857occur due to the number of store instructions reaching the limit of the 858pipeline, (i.e. all store buffers are used). 859The stall ends when a store 860instruction commits its data to the cache or memory. 861.It Li RESOURCE_STALLS.ROB_FULL 862.Pq Event A2H , Umask 10H 863Counts the cycles of stall due to re- order buffer full. 864.It Li RESOURCE_STALLS.FPCW 865.Pq Event A2H , Umask 20H 866Counts the number of cycles while execution was stalled due to writing the 867floating-point unit (FPU) control word. 868.It Li RESOURCE_STALLS.MXCSR 869.Pq Event A2H , Umask 40H 870Stalls due to the MXCSR register rename occurring to close to a previous 871MXCSR rename. 872The MXCSR provides control and status for the MMX registers. 873.It Li RESOURCE_STALLS.OTHER 874.Pq Event A2H , Umask 80H 875Counts the number of cycles while execution was stalled due to other 876resource issues. 877.It Li MACRO_INSTS.FUSIONS_DECODED 878.Pq Event A6H , Umask 01H 879Counts the number of instructions decoded that are macro-fused but not 880necessarily executed or retired. 881.It Li BACLEAR_FORCE_IQ 882.Pq Event A7H , Umask 01H 883Counts number of times a BACLEAR was forced by the Instruction Queue. 884The IQ is also responsible for providing conditional branch prediction 885direction based on a static scheme and dynamic data provided by the L2 886Branch Prediction Unit. 887If the conditional branch target is not found in the Target 888Array and the IQ predicts that the branch is taken, then the IQ will force 889the Branch Address Calculator to issue a BACLEAR. 890Each BACLEAR asserted by 891the BAC generates approximately an 8 cycle bubble in the instruction fetch 892pipeline. 893.It Li LSD.UOPS 894.Pq Event A8H , Umask 01H 895Counts the number of micro-ops delivered by loop stream detector 896Use cmask=1 and invert to count cycles 897.It Li ITLB_FLUSH 898.Pq Event AEH , Umask 01H 899Counts the number of ITLB flushes 900.It Li OFFCORE_REQUESTS.DEMAND.READ_DATA 901.Pq Event B0H , Umask 01H 902Counts number of offcore demand data read requests. 903Does not count L2 prefetch requests. 904.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE 905.Pq Event B0H , Umask 02H 906Counts number of offcore demand code read requests. 907Does not count L2 prefetch requests. 908.It Li OFFCORE_REQUESTS.DEMAND.RFO 909.Pq Event B0H , Umask 04H 910Counts number of offcore demand RFO requests. 911Does not count L2 prefetch requests. 912.It Li OFFCORE_REQUESTS.ANY.READ 913.Pq Event B0H , Umask 08H 914Counts number of offcore read requests. 915Includes L2 prefetch requests. 916.It Li OFFCORE_REQUESTS.ANY.RFO 917.Pq Event 80H , Umask 10H 918Counts number of offcore RFO requests. 919Includes L2 prefetch requests. 920.It Li OFFCORE_REQUESTS.L1D_WRITEBACK 921.Pq Event B0H , Umask 40H 922Counts number of L1D writebacks to the uncore. 923.It Li OFFCORE_REQUESTS.ANY 924.Pq Event B0H , Umask 80H 925Counts all offcore requests. 926.It Li UOPS_EXECUTED.PORT0 927.Pq Event B1H , Umask 01H 928Counts number of Uops executed that were issued on port 0. 929Port 0 handles integer arithmetic, SIMD and FP add Uops. 930.It Li UOPS_EXECUTED.PORT1 931.Pq Event B1H , Umask 02H 932Counts number of Uops executed that were issued on port 1. 933Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and 934FP divide Uops. 935.It Li UOPS_EXECUTED.PORT2_CORE 936.Pq Event B1H , Umask 04H 937Counts number of Uops executed that were issued on port 2. 938Port 2 handles the load Uops. 939This is a core count only and can not be collected per 940thread. 941.It Li UOPS_EXECUTED.PORT3_CORE 942.Pq Event B1H , Umask 08H 943Counts number of Uops executed that were issued on port 3. 944Port 3 handles store Uops. 945This is a core count only and can not be collected per thread. 946.It Li UOPS_EXECUTED.PORT4_CORE 947.Pq Event B1H , Umask 10H 948Counts number of Uops executed that where issued on port 4. 949Port 4 handles the value to be stored for the store Uops issued on port 3. 950This is a core count only and can not be collected per thread. 951.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 952.Pq Event B1H , Umask 1FH 953Counts number of cycles there are one or more uops being executed and were 954issued on ports 0-4. 955This is a core count only and can not be collected per thread. 956.It Li UOPS_EXECUTED.PORT5 957.Pq Event B1H , Umask 20H 958Counts number of Uops executed that where issued on port 5. 959.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES 960.Pq Event B1H , Umask 3FH 961Counts number of cycles there are one or more uops being executed on any 962ports. 963This is a core count only and can not be collected per thread. 964.It Li UOPS_EXECUTED.PORT015 965.Pq Event B1H , Umask 40H 966Counts number of Uops executed that where issued on port 0, 1, or 5. 967Use cmask=1, invert=1 to count stall cycles. 968.It Li UOPS_EXECUTED.PORT234 969.Pq Event B1H , Umask 80H 970Counts number of Uops executed that where issued on port 2, 3, or 4. 971.It Li OFFCORE_REQUESTS_SQ_FULL 972.Pq Event B2H , Umask 01H 973Counts number of cycles the SQ is full to handle off-core requests. 974.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA 975.Pq Event B3H , Umask 01H 976Counts weighted cycles of snoopq requests for data. 977Counter 0 only 978Use cmask=1 to count cycles not empty. 979.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE 980.Pq Event B3H , Umask 02H 981Counts weighted cycles of snoopq invalidate requests. 982Counter 0 only. 983Use cmask=1 to count cycles not empty. 984.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 985.Pq Event B3H , Umask 04H 986Counts weighted cycles of snoopq requests for code. 987Counter 0 only. 988Use cmask=1 to count cycles not empty. 989.It Li SNOOPQ_REQUESTS.CODE 990.Pq Event B4H , Umask 01H 991Counts the number of snoop code requests. 992.It Li SNOOPQ_REQUESTS.DATA 993.Pq Event B4H , Umask 02H 994Counts the number of snoop data requests. 995.It Li SNOOPQ_REQUESTS.INVALIDATE 996.Pq Event B4H , Umask 04H 997Counts the number of snoop invalidate requests 998.It Li OFF_CORE_RESPONSE_0 999.Pq Event B7H , Umask 01H 1000see Section 30.6.1.3, Off-core Response Performance Monitoring in the 1001Processor Core. 1002Requires programming MSR 01A6H. 1003.It Li SNOOP_RESPONSE.HIT 1004.Pq Event B8H , Umask 01H 1005Counts HIT snoop response sent by this thread in response to a snoop 1006request. 1007.It Li SNOOP_RESPONSE.HITE 1008.Pq Event B8H , Umask 02H 1009Counts HIT E snoop response sent by this thread in response to a snoop 1010request. 1011.It Li SNOOP_RESPONSE.HITM 1012.Pq Event B8H , Umask 04H 1013Counts HIT M snoop response sent by this thread in response to a snoop 1014request. 1015.It Li OFF_CORE_RESPONSE_1 1016.Pq Event BBH , Umask 01H 1017see Section 30.6.1.3, Off-core Response Performance Monitoring in the 1018Processor Core. 1019Use MSR 01A7H. 1020.It Li INST_RETIRED.ANY_P 1021.Pq Event C0H , Umask 01H 1022See Table A-1 1023Notes: INST_RETIRED.ANY is counted by a designated fixed counter. 1024INST_RETIRED.ANY_P is counted by a programmable counter and is an 1025architectural performance event. 1026Event is supported if CPUID.A.EBX[1] = 0. 1027Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not 1028count as retired instructions. 1029.It Li INST_RETIRED.X87 1030.Pq Event C0H , Umask 02H 1031Counts the number of floating point computational operations retired 1032floating point computational operations executed by the assist handler and 1033sub-operations of complex floating point instructions like transcendental 1034instructions. 1035.It Li INST_RETIRED.MMX 1036.Pq Event C0H , Umask 04H 1037Counts the number of retired: MMX instructions. 1038.It Li UOPS_RETIRED.ANY 1039.Pq Event C2H , Umask 01H 1040Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, 1041others=1; maximum count of 8 per cycle). 1042Most instructions are composed of one or two micro-ops. 1043Some instructions are decoded into longer sequences 1044such as repeat instructions, floating point transcendental instructions, and 1045assists. 1046Use cmask=1 and invert to count active cycles or stalled cycles 1047.It Li UOPS_RETIRED.RETIRE_SLOTS 1048.Pq Event C2H , Umask 02H 1049Counts the number of retirement slots used each cycle 1050.It Li UOPS_RETIRED.MACRO_FUSED 1051.Pq Event C2H , Umask 04H 1052Counts number of macro-fused uops retired. 1053.It Li MACHINE_CLEARS.CYCLES 1054.Pq Event C3H , Umask 01H 1055Counts the cycles machine clear is asserted. 1056.It Li MACHINE_CLEARS.MEM_ORDER 1057.Pq Event C3H , Umask 02H 1058Counts the number of machine clears due to memory order conflicts. 1059.It Li MACHINE_CLEARS.SMC 1060.Pq Event C3H , Umask 04H 1061Counts the number of times that a program writes to a code section. 1062Self-modifying code causes a sever penalty in all Intel 64 and IA-32 1063processors. 1064The modified cache line is written back to the L2 and L3caches. 1065.It Li BR_INST_RETIRED.ANY_P 1066.Pq Event C4H , Umask 00H 1067See Table A-1. 1068.It Li BR_INST_RETIRED.CONDITIONAL 1069.Pq Event C4H , Umask 01H 1070Counts the number of conditional branch instructions retired. 1071.It Li BR_INST_RETIRED.NEAR_CALL 1072.Pq Event C4H , Umask 02H 1073Counts the number of direct & indirect near unconditional calls retired. 1074.It Li BR_INST_RETIRED.ALL_BRANCHES 1075.Pq Event C4H , Umask 04H 1076Counts the number of branch instructions retired. 1077.It Li BR_MISP_RETIRED.ANY_P 1078.Pq Event C5H , Umask 00H 1079See Table A-1. 1080.It Li BR_MISP_RETIRED.CONDITIONAL 1081.Pq Event C5H , Umask 01H 1082Counts mispredicted conditional retired calls. 1083.It Li BR_MISP_RETIRED.NEAR_CALL 1084.Pq Event C5H , Umask 02H 1085Counts mispredicted direct & indirect near unconditional retired calls. 1086.It Li BR_MISP_RETIRED.ALL_BRANCHES 1087.Pq Event C5H , Umask 04H 1088Counts all mispredicted retired calls. 1089.It Li SSEX_UOPS_RETIRED.PACKED_SINGLE 1090.Pq Event C7H , Umask 01H 1091Counts SIMD packed single-precision floating point Uops retired. 1092.It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE 1093.Pq Event C7H , Umask 02H 1094Counts SIMD calar single-precision floating point Uops retired. 1095.It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE 1096.Pq Event C7H , Umask 04H 1097Counts SIMD packed double- precision floating point Uops retired. 1098.It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE 1099.Pq Event C7H , Umask 08H 1100Counts SIMD scalar double-precision floating point Uops retired. 1101.It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER 1102.Pq Event C7H , Umask 10H 1103Counts 128-bit SIMD vector integer Uops retired. 1104.It Li ITLB_MISS_RETIRED 1105.Pq Event C8H , Umask 20H 1106Counts the number of retired instructions that missed the ITLB when the 1107instruction was fetched. 1108.It Li MEM_LOAD_RETIRED.L1D_HIT 1109.Pq Event CBH , Umask 01H 1110Counts number of retired loads that hit the L1 data cache. 1111.It Li MEM_LOAD_RETIRED.L2_HIT 1112.Pq Event CBH , Umask 02H 1113Counts number of retired loads that hit the L2 data cache. 1114.It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT 1115.Pq Event CBH , Umask 04H 1116Counts number of retired loads that hit their own, unshared lines in the L3 1117cache. 1118.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM 1119.Pq Event CBH , Umask 08H 1120Counts number of retired loads that hit in a sibling core's L2 (on die 1121core). 1122Since the L3 is inclusive of all cores on the package, this is an L3 hit. 1123This counts both clean or modified hits. 1124.It Li MEM_LOAD_RETIRED.L3_MISS 1125.Pq Event CBH , Umask 10H 1126Counts number of retired loads that miss the L3 cache. 1127The load was satisfied by a remote socket, local memory or an IOH. 1128.It Li MEM_LOAD_RETIRED.HIT_LFB 1129.Pq Event CBH , Umask 40H 1130Counts number of retired loads that miss the L1D and the address is located 1131in an allocated line fill buffer and will soon be committed to cache. 1132This is counting secondary L1D misses. 1133.It Li MEM_LOAD_RETIRED.DTLB_MISS 1134.Pq Event CBH , Umask 80H 1135Counts the number of retired loads that missed the DTLB. 1136The DTLB miss is not counted if the load operation causes a fault. 1137This event counts loads from cacheable memory only. 1138The event does not count loads by software prefetches. 1139Counts both primary and secondary misses to the TLB. 1140.It Li FP_MMX_TRANS.TO_FP 1141.Pq Event CCH , Umask 01H 1142Counts the first floating-point instruction following any MMX instruction. 1143You can use this event to estimate the penalties for the transitions between 1144floating-point and MMX technology states. 1145.It Li FP_MMX_TRANS.TO_MMX 1146.Pq Event CCH , Umask 02H 1147Counts the first MMX instruction following a floating-point instruction. 1148You can use this event to estimate the penalties for the transitions between 1149floating-point and MMX technology states. 1150.It Li FP_MMX_TRANS.ANY 1151.Pq Event CCH , Umask 03H 1152Counts all transitions from floating point to MMX instructions and from MMX 1153instructions to floating point instructions. 1154You can use this event to estimate the penalties for the transitions between 1155floating-point and MMX technology states. 1156.It Li MACRO_INSTS.DECODED 1157.Pq Event D0H , Umask 01H 1158Counts the number of instructions decoded, (but not necessarily executed or 1159retired). 1160.It Li UOPS_DECODED.STALL_CYCLES 1161.Pq Event D1H , Umask 01H 1162Counts the cycles of decoder stalls. 1163.It Li UOPS_DECODED.MS 1164.Pq Event D1H , Umask 02H 1165Counts the number of Uops decoded by the Microcode Sequencer, MS. 1166The MS delivers uops when the instruction is more than 4 uops long or a 1167microcode assist is occurring. 1168.It Li UOPS_DECODED.ESP_FOLDING 1169.Pq Event D1H , Umask 04H 1170Counts number of stack pointer (ESP) instructions decoded: push , pop , call 1171, ret, etc. ESP instructions do not generate a Uop to increment or decrement 1172ESP. 1173Instead, they update an ESP_Offset register that keeps track of the 1174delta to the current value of the ESP register. 1175.It Li UOPS_DECODED.ESP_SYNC 1176.Pq Event D1H , Umask 08H 1177Counts number of stack pointer (ESP) sync operations where an ESP 1178instruction is corrected by adding the ESP offset register to the current 1179value of the ESP register. 1180.It Li RAT_STALLS.FLAGS 1181.Pq Event D2H , Umask 01H 1182Counts the number of cycles during which execution stalled due to several 1183reasons, one of which is a partial flag register stall. 1184A partial register 1185stall may occur when two conditions are met: 1) an instruction modifies 1186some, but not all, of the flags in the flag register and 2) the next 1187instruction, which depends on flags, depends on flags that were not modified 1188by this instruction. 1189.It Li RAT_STALLS.REGISTERS 1190.Pq Event D2H , Umask 02H 1191This event counts the number of cycles instruction execution latency became 1192longer than the defined latency because the instruction used a register that 1193was partially written by previous instruction. 1194.It Li RAT_STALLS.ROB_READ_PORT 1195.Pq Event D2H , Umask 04H 1196Counts the number of cycles when ROB read port stalls occurred, which did 1197not allow new micro-ops to enter the out-of-order pipeline. 1198Note that, at 1199this stage in the pipeline, additional stalls may occur at the same cycle 1200and prevent the stalled micro-ops from entering the pipe. 1201In such a case, 1202micro-ops retry entering the execution pipe in the next cycle and the 1203ROB-read port stall is counted again. 1204.It Li RAT_STALLS.SCOREBOARD 1205.Pq Event D2H , Umask 08H 1206Counts the cycles where we stall due to microarchitecturally required 1207serialization. 1208Microcode scoreboarding stalls. 1209.It Li RAT_STALLS.ANY 1210.Pq Event D2H , Umask 0FH 1211Counts all Register Allocation Table stall cycles due to: Cycles when ROB 1212read port stalls occurred, which did not allow new micro-ops to enter the 1213execution pipe. 1214Cycles when partial register stalls occurred Cycles when 1215flag stalls occurred Cycles floating-point unit (FPU) status word stalls 1216occurred. 1217To count each of these conditions separately use the events: 1218RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and 1219RAT_STALLS.FPSW. 1220.It Li SEG_RENAME_STALLS 1221.Pq Event D4H , Umask 01H 1222Counts the number of stall cycles due to the lack of renaming resources for 1223the ES, DS, FS, and GS segment registers. 1224If a segment is renamed but not 1225retired and a second update to the same segment occurs, a stall occurs in 1226the front- end of the pipeline until the renamed segment retires. 1227.It Li ES_REG_RENAMES 1228.Pq Event D5H , Umask 01H 1229Counts the number of times the ES segment register is renamed. 1230.It Li UOP_UNFUSION 1231.Pq Event DBH , Umask 01H 1232Counts unfusion events due to floating point exception to a fused uop. 1233.It Li BR_INST_DECODED 1234.Pq Event E0H , Umask 01H 1235Counts the number of branch instructions decoded. 1236.It Li BPU_MISSED_CALL_RET 1237.Pq Event E5H , Umask 01H 1238Counts number of times the Branch Prediction Unit missed predicting a call 1239or return branch. 1240.It Li BACLEAR.CLEAR 1241.Pq Event E6H , Umask 01H 1242Counts the number of times the front end is resteered, mainly when the 1243Branch Prediction Unit cannot provide a correct prediction and this is 1244corrected by the Branch Address Calculator at the front end. 1245This can occur 1246if the code has many branches such that they cannot be consumed by the BPU. 1247Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble 1248in the instruction fetch pipeline. 1249The effect on total execution time depends on the surrounding code. 1250.It Li BACLEAR.BAD_TARGET 1251.Pq Event E6H , Umask 02H 1252Counts number of Branch Address Calculator clears (BACLEAR) asserted due to 1253conditional branch instructions in which there was a target hit but the 1254direction was wrong. 1255Each BACLEAR asserted by the BAC generates 1256approximately an 8 cycle bubble in the instruction fetch pipeline. 1257.It Li BPU_CLEARS.EARLY 1258.Pq Event E8H , Umask 01H 1259Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken 1260branch after incorrectly assuming that it was not taken. 1261The BPU clear leads to 2 cycle bubble in the Front End. 1262.It Li BPU_CLEARS.LATE 1263.Pq Event E8H , Umask 02H 1264Counts late Branch Prediction Unit clears due to Most Recently Used 1265conflicts. 1266The PBU clear leads to a 3 cycle bubble in the Front End. 1267.It Li THREAD_ACTIVE 1268.Pq Event ECH , Umask 01H 1269Counts cycles threads are active. 1270.It Li L2_TRANSACTIONS.LOAD 1271.Pq Event F0H , Umask 01H 1272Counts L2 load operations due to HW prefetch or demand loads. 1273.It Li L2_TRANSACTIONS.RFO 1274.Pq Event F0H , Umask 02H 1275Counts L2 RFO operations due to HW prefetch or demand RFOs. 1276.It Li L2_TRANSACTIONS.IFETCH 1277.Pq Event F0H , Umask 04H 1278Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. 1279.It Li L2_TRANSACTIONS.PREFETCH 1280.Pq Event F0H , Umask 08H 1281Counts L2 prefetch operations. 1282.It Li L2_TRANSACTIONS.L1D_WB 1283.Pq Event F0H , Umask 10H 1284Counts L1D writeback operations to the L2. 1285.It Li L2_TRANSACTIONS.FILL 1286.Pq Event F0H , Umask 20H 1287Counts L2 cache line fill operations due to load, RFO, L1D writeback or 1288prefetch. 1289.It Li L2_TRANSACTIONS.WB 1290.Pq Event F0H , Umask 40H 1291Counts L2 writeback operations to the L3. 1292.It Li L2_TRANSACTIONS.ANY 1293.Pq Event F0H , Umask 80H 1294Counts all L2 cache operations. 1295.It Li L2_LINES_IN.S_STATE 1296.Pq Event F1H , Umask 02H 1297Counts the number of cache lines allocated in the L2 cache in the S (shared) 1298state. 1299.It Li L2_LINES_IN.E_STATE 1300.Pq Event F1H , Umask 04H 1301Counts the number of cache lines allocated in the L2 cache in the E 1302(exclusive) state. 1303.It Li L2_LINES_IN.ANY 1304.Pq Event F1H , Umask 07H 1305Counts the number of cache lines allocated in the L2 cache. 1306.It Li L2_LINES_OUT.DEMAND_CLEAN 1307.Pq Event F2H , Umask 01H 1308Counts L2 clean cache lines evicted by a demand request. 1309.It Li L2_LINES_OUT.DEMAND_DIRTY 1310.Pq Event F2H , Umask 02H 1311Counts L2 dirty (modified) cache lines evicted by a demand request. 1312.It Li L2_LINES_OUT.PREFETCH_CLEAN 1313.Pq Event F2H , Umask 04H 1314Counts L2 clean cache line evicted by a prefetch request. 1315.It Li L2_LINES_OUT.PREFETCH_DIRTY 1316.Pq Event F2H , Umask 08H 1317Counts L2 modified cache line evicted by a prefetch request. 1318.It Li L2_LINES_OUT.ANY 1319.Pq Event F2H , Umask 0FH 1320Counts all L2 cache lines evicted for any reason. 1321.It Li SQ_MISC.LRU_HINTS 1322.Pq Event F4H , Umask 04H 1323Counts number of Super Queue LRU hints sent to L3. 1324.It Li SQ_MISC.SPLIT_LOCK 1325.Pq Event F4H , Umask 10H 1326Counts the number of SQ lock splits across a cache line. 1327.It Li SQ_FULL_STALL_CYCLES 1328.Pq Event F6H , Umask 01H 1329Counts cycles the Super Queue is full. 1330Neither of the threads on this core will be able to access the uncore. 1331.It Li FP_ASSIST.ALL 1332.Pq Event F7H , Umask 01H 1333Counts the number of floating point operations executed that required 1334micro-code assist intervention. 1335Assists are required in the following cases: 1336SSE instructions, (Denormal input when the DAZ flag is off or Underflow 1337result when the FTZ flag is off): x87 instructions, (NaN or denormal are 1338loaded to a register or used as input from memory, Division by 0 or 1339Underflow output). 1340.It Li FP_ASSIST.OUTPUT 1341.Pq Event F7H , Umask 02H 1342Counts number of floating point micro-code assist when the output value 1343(destination register) is invalid. 1344.It Li FP_ASSIST.INPUT 1345.Pq Event F7H , Umask 04H 1346Counts number of floating point micro-code assist when the input value (one 1347of the source operands to an FP instruction) is invalid. 1348.It Li SIMD_INT_64.PACKED_MPY 1349.Pq Event FDH , Umask 01H 1350Counts number of SID integer 64 bit packed multiply operations. 1351.It Li SIMD_INT_64.PACKED_SHIFT 1352.Pq Event FDH , Umask 02H 1353Counts number of SID integer 64 bit packed shift operations. 1354.It Li SIMD_INT_64.PACK 1355.Pq Event FDH , Umask 04H 1356Counts number of SID integer 64 bit pack operations. 1357.It Li SIMD_INT_64.UNPACK 1358.Pq Event FDH , Umask 08H 1359Counts number of SID integer 64 bit unpack operations. 1360.It Li SIMD_INT_64.PACKED_LOGICAL 1361.Pq Event FDH , Umask 10H 1362Counts number of SID integer 64 bit logical operations. 1363.It Li SIMD_INT_64.PACKED_ARITH 1364.Pq Event FDH , Umask 20H 1365Counts number of SID integer 64 bit arithmetic operations. 1366.It Li SIMD_INT_64.SHUFFLE_MOVE 1367.Pq Event FDH , Umask 40H 1368Counts number of SID integer 64 bit shift or move operations. 1369.El 1370.Sh SEE ALSO 1371.Xr pmc 3 , 1372.Xr pmc.atom 3 , 1373.Xr pmc.core 3 , 1374.Xr pmc.corei7 3 , 1375.Xr pmc.corei7uc 3 , 1376.Xr pmc.iaf 3 , 1377.Xr pmc.k7 3 , 1378.Xr pmc.k8 3 , 1379.Xr pmc.p4 3 , 1380.Xr pmc.p5 3 , 1381.Xr pmc.p6 3 , 1382.Xr pmc.soft 3 , 1383.Xr pmc.tsc 3 , 1384.Xr pmc.ucf 3 , 1385.Xr pmc.westmereuc 3 , 1386.Xr pmc_cpuinfo 3 , 1387.Xr pmclog 3 , 1388.Xr hwpmc 4 1389.Sh HISTORY 1390The 1391.Nm pmc 1392library first appeared in 1393.Fx 6.0 . 1394.Sh AUTHORS 1395The 1396.Lb libpmc 1397library was written by 1398.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1399