xref: /freebsd/lib/libpmc/pmc.westmere.3 (revision c2025a76606b44c4d5367b7509fbc0285ae1e7f8)
11fa7f10bSFabien Thomas.\" Copyright (c) 2010 Fabien Thomas.  All rights reserved.
21fa7f10bSFabien Thomas.\"
31fa7f10bSFabien Thomas.\" Redistribution and use in source and binary forms, with or without
41fa7f10bSFabien Thomas.\" modification, are permitted provided that the following conditions
51fa7f10bSFabien Thomas.\" are met:
61fa7f10bSFabien Thomas.\" 1. Redistributions of source code must retain the above copyright
71fa7f10bSFabien Thomas.\"    notice, this list of conditions and the following disclaimer.
81fa7f10bSFabien Thomas.\" 2. Redistributions in binary form must reproduce the above copyright
91fa7f10bSFabien Thomas.\"    notice, this list of conditions and the following disclaimer in the
101fa7f10bSFabien Thomas.\"    documentation and/or other materials provided with the distribution.
111fa7f10bSFabien Thomas.\"
121fa7f10bSFabien Thomas.\" This software is provided by Joseph Koshy ``as is'' and
131fa7f10bSFabien Thomas.\" any express or implied warranties, including, but not limited to, the
141fa7f10bSFabien Thomas.\" implied warranties of merchantability and fitness for a particular purpose
151fa7f10bSFabien Thomas.\" are disclaimed.  in no event shall Joseph Koshy be liable
161fa7f10bSFabien Thomas.\" for any direct, indirect, incidental, special, exemplary, or consequential
171fa7f10bSFabien Thomas.\" damages (including, but not limited to, procurement of substitute goods
181fa7f10bSFabien Thomas.\" or services; loss of use, data, or profits; or business interruption)
191fa7f10bSFabien Thomas.\" however caused and on any theory of liability, whether in contract, strict
201fa7f10bSFabien Thomas.\" liability, or tort (including negligence or otherwise) arising in any way
211fa7f10bSFabien Thomas.\" out of the use of this software, even if advised of the possibility of
221fa7f10bSFabien Thomas.\" such damage.
231fa7f10bSFabien Thomas.\"
241fa7f10bSFabien Thomas.\" $FreeBSD$
251fa7f10bSFabien Thomas.\"
261fa7f10bSFabien Thomas.Dd March 24, 2010
271fa7f10bSFabien Thomas.Dt PMC.WESTMERE 3
28aa12cea2SUlrich Spörlein.Os
291fa7f10bSFabien Thomas.Sh NAME
301fa7f10bSFabien Thomas.Nm pmc.westmere
311fa7f10bSFabien Thomas.Nd measurement events for
321fa7f10bSFabien Thomas.Tn Intel
331fa7f10bSFabien Thomas.Tn Westmere
341fa7f10bSFabien Thomasfamily CPUs
351fa7f10bSFabien Thomas.Sh LIBRARY
361fa7f10bSFabien Thomas.Lb libpmc
371fa7f10bSFabien Thomas.Sh SYNOPSIS
381fa7f10bSFabien Thomas.In pmc.h
391fa7f10bSFabien Thomas.Sh DESCRIPTION
401fa7f10bSFabien Thomas.Tn Intel
411fa7f10bSFabien Thomas.Tn "Westmere"
421fa7f10bSFabien ThomasCPUs contain PMCs conforming to version 2 of the
431fa7f10bSFabien Thomas.Tn Intel
441fa7f10bSFabien Thomasperformance measurement architecture.
451fa7f10bSFabien ThomasThese CPUs may contain up to three classes of PMCs:
461fa7f10bSFabien Thomas.Bl -tag -width "Li PMC_CLASS_IAP"
471fa7f10bSFabien Thomas.It Li PMC_CLASS_IAF
481fa7f10bSFabien ThomasFixed-function counters that count only one hardware event per counter.
491fa7f10bSFabien Thomas.It Li PMC_CLASS_IAP
501fa7f10bSFabien ThomasProgrammable counters that may be configured to count one of a defined
511fa7f10bSFabien Thomasset of hardware events.
521fa7f10bSFabien Thomas.El
531fa7f10bSFabien Thomas.Pp
541fa7f10bSFabien ThomasThe number of PMCs available in each class and their widths need to be
551fa7f10bSFabien Thomasdetermined at run time by calling
561fa7f10bSFabien Thomas.Xr pmc_cpuinfo 3 .
571fa7f10bSFabien Thomas.Pp
581fa7f10bSFabien ThomasIntel Westmere PMCs are documented in
591fa7f10bSFabien Thomas.Rs
601fa7f10bSFabien Thomas.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
611fa7f10bSFabien Thomas.%T "Volume 3B: System Programming Guide, Part 2"
621fa7f10bSFabien Thomas.%N "Order Number: 253669-033US"
631fa7f10bSFabien Thomas.%D December 2009
641fa7f10bSFabien Thomas.%Q "Intel Corporation"
651fa7f10bSFabien Thomas.Re
661fa7f10bSFabien Thomas.Ss WESTMERE FIXED FUNCTION PMCS
671fa7f10bSFabien ThomasThese PMCs and their supported events are documented in
681fa7f10bSFabien Thomas.Xr pmc.iaf 3 .
691fa7f10bSFabien Thomas.Ss WESTMERE PROGRAMMABLE PMCS
701fa7f10bSFabien ThomasThe programmable PMCs support the following capabilities:
711fa7f10bSFabien Thomas.Bl -column "PMC_CAP_INTERRUPT" "Support"
721fa7f10bSFabien Thomas.It Em Capability Ta Em Support
731fa7f10bSFabien Thomas.It PMC_CAP_CASCADE Ta \&No
741fa7f10bSFabien Thomas.It PMC_CAP_EDGE Ta Yes
751fa7f10bSFabien Thomas.It PMC_CAP_INTERRUPT Ta Yes
761fa7f10bSFabien Thomas.It PMC_CAP_INVERT Ta Yes
771fa7f10bSFabien Thomas.It PMC_CAP_READ Ta Yes
781fa7f10bSFabien Thomas.It PMC_CAP_PRECISE Ta \&No
791fa7f10bSFabien Thomas.It PMC_CAP_SYSTEM Ta Yes
801fa7f10bSFabien Thomas.It PMC_CAP_TAGGING Ta \&No
811fa7f10bSFabien Thomas.It PMC_CAP_THRESHOLD Ta Yes
821fa7f10bSFabien Thomas.It PMC_CAP_USER Ta Yes
831fa7f10bSFabien Thomas.It PMC_CAP_WRITE Ta Yes
841fa7f10bSFabien Thomas.El
851fa7f10bSFabien Thomas.Ss Event Qualifiers
861fa7f10bSFabien ThomasEvent specifiers for these PMCs support the following common
871fa7f10bSFabien Thomasqualifiers:
881fa7f10bSFabien Thomas.Bl -tag -width indent
891fa7f10bSFabien Thomas.It Li rsp= Ns Ar value
901fa7f10bSFabien ThomasConfigure the Off-core Response bits.
911fa7f10bSFabien Thomas.Bl -tag -width indent
921fa7f10bSFabien Thomas.It Li DMND_DATA_RD
931fa7f10bSFabien ThomasCounts the number of demand and DCU prefetch data reads of full
941fa7f10bSFabien Thomasand partial cachelines as well as demand data page table entry
951fa7f10bSFabien Thomascacheline reads. Does not count L2 data read prefetches or
961fa7f10bSFabien Thomasinstruction fetches.
971fa7f10bSFabien Thomas.It Li DMND_RFO
981fa7f10bSFabien ThomasCounts the number of demand and DCU prefetch reads for ownership
991fa7f10bSFabien Thomas(RFO) requests generated by a write to data cacheline. Does not
1001fa7f10bSFabien Thomascount L2 RFO.
1011fa7f10bSFabien Thomas.It Li DMND_IFETCH
1021fa7f10bSFabien ThomasCounts the number of demand and DCU prefetch instruction cacheline
1031fa7f10bSFabien Thomasreads. Does not count L2 code read prefetches.
1041fa7f10bSFabien ThomasWB
1051fa7f10bSFabien ThomasCounts the number of writeback (modified to exclusive) transactions.
1061fa7f10bSFabien Thomas.It Li PF_DATA_RD
1071fa7f10bSFabien ThomasCounts the number of data cacheline reads generated by L2 prefetchers.
1081fa7f10bSFabien Thomas.It Li PF_RFO
1091fa7f10bSFabien ThomasCounts the number of RFO requests generated by L2 prefetchers.
1101fa7f10bSFabien Thomas.It Li PF_IFETCH
1111fa7f10bSFabien ThomasCounts the number of code reads generated by L2 prefetchers.
1121fa7f10bSFabien Thomas.It Li OTHER
1131fa7f10bSFabien ThomasCounts one of the following transaction types, including L3 invalidate,
1141fa7f10bSFabien ThomasI/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
1151fa7f10bSFabien Thomaslock, unlock, split lock.
1161fa7f10bSFabien Thomas.It Li UNCORE_HIT
1171fa7f10bSFabien ThomasL3 Hit: local or remote home requests that hit L3 cache in the uncore
1181fa7f10bSFabien Thomaswith no coherency actions required (snooping).
1191fa7f10bSFabien Thomas.It Li OTHER_CORE_HIT_SNP
1201fa7f10bSFabien ThomasL3 Hit: local or remote home requests that hit L3 cache in the uncore
1211fa7f10bSFabien Thomasand was serviced by another core with a cross core snoop where no modified
1221fa7f10bSFabien Thomascopies were found (clean).
1231fa7f10bSFabien Thomas.It Li OTHER_CORE_HITM
1241fa7f10bSFabien ThomasL3 Hit: local or remote home requests that hit L3 cache in the uncore
1251fa7f10bSFabien Thomasand was serviced by another core with a cross core snoop where modified
1261fa7f10bSFabien Thomascopies were found (HITM).
1271fa7f10bSFabien Thomas.It Li REMOTE_CACHE_FWD
1281fa7f10bSFabien ThomasL3 Miss: local homed requests that missed the L3 cache and was serviced
1291fa7f10bSFabien Thomasby forwarded data following a cross package snoop where no modified
1301fa7f10bSFabien Thomascopies found. (Remote home requests are not counted)
1311fa7f10bSFabien Thomas.It Li REMOTE_DRAM
1321fa7f10bSFabien ThomasL3 Miss: remote home requests that missed the L3 cache and were serviced
1331fa7f10bSFabien Thomasby remote DRAM.
1341fa7f10bSFabien Thomas.It Li LOCAL_DRAM
1351fa7f10bSFabien ThomasL3 Miss: local home requests that missed the L3 cache and were serviced
1361fa7f10bSFabien Thomasby local DRAM.
1371fa7f10bSFabien Thomas.It Li NON_DRAM
1381fa7f10bSFabien ThomasNon-DRAM requests that were serviced by IOH.
1391fa7f10bSFabien Thomas.El
1401fa7f10bSFabien Thomas.It Li cmask= Ns Ar value
1411fa7f10bSFabien ThomasConfigure the PMC to increment only if the number of configured
1421fa7f10bSFabien Thomasevents measured in a cycle is greater than or equal to
1431fa7f10bSFabien Thomas.Ar value .
1441fa7f10bSFabien Thomas.It Li edge
1451fa7f10bSFabien ThomasConfigure the PMC to count the number of de-asserted to asserted
1461fa7f10bSFabien Thomastransitions of the conditions expressed by the other qualifiers.
1471fa7f10bSFabien ThomasIf specified, the counter will increment only once whenever a
1481fa7f10bSFabien Thomascondition becomes true, irrespective of the number of clocks during
1491fa7f10bSFabien Thomaswhich the condition remains true.
1501fa7f10bSFabien Thomas.It Li inv
1511fa7f10bSFabien ThomasInvert the sense of comparison when the
1521fa7f10bSFabien Thomas.Dq Li cmask
1531fa7f10bSFabien Thomasqualifier is present, making the counter increment when the number of
1541fa7f10bSFabien Thomasevents per cycle is less than the value specified by the
1551fa7f10bSFabien Thomas.Dq Li cmask
1561fa7f10bSFabien Thomasqualifier.
1571fa7f10bSFabien Thomas.It Li os
1581fa7f10bSFabien ThomasConfigure the PMC to count events happening at processor privilege
1591fa7f10bSFabien Thomaslevel 0.
1601fa7f10bSFabien Thomas.It Li usr
1611fa7f10bSFabien ThomasConfigure the PMC to count events occurring at privilege levels 1, 2
1621fa7f10bSFabien Thomasor 3.
1631fa7f10bSFabien Thomas.El
1641fa7f10bSFabien Thomas.Pp
1651fa7f10bSFabien ThomasIf neither of the
1661fa7f10bSFabien Thomas.Dq Li os
1671fa7f10bSFabien Thomasor
1681fa7f10bSFabien Thomas.Dq Li usr
1691fa7f10bSFabien Thomasqualifiers are specified, the default is to enable both.
1701fa7f10bSFabien Thomas.Ss Event Specifiers (Programmable PMCs)
1711fa7f10bSFabien ThomasWestmere programmable PMCs support the following events:
1721fa7f10bSFabien Thomas.Bl -tag -width indent
1731fa7f10bSFabien Thomas.It Li LOAD_BLOCK.OVERLAP_STORE
1741fa7f10bSFabien Thomas.Pq Event 03H , Umask 02H
1751fa7f10bSFabien ThomasLoads that partially overlap an earlier store
1761fa7f10bSFabien Thomas.It Li SB_DRAIN.ANY
1771fa7f10bSFabien Thomas.Pq Event 04H , Umask 07H
1781fa7f10bSFabien ThomasAll Store buffer stall cycles
1791fa7f10bSFabien Thomas.It Li MISALIGN_MEMORY.STORE
1801fa7f10bSFabien Thomas.Pq Event 05H , Umask 02H
1811fa7f10bSFabien ThomasAll store referenced with misaligned address
1821fa7f10bSFabien Thomas.It Li STORE_BLOCKS.AT_RET
1831fa7f10bSFabien Thomas.Pq Event 06H , Umask 04H
1841fa7f10bSFabien ThomasCounts number of loads delayed with at-Retirement block code. The following
1851fa7f10bSFabien Thomasloads need to be executed at retirement and wait for all senior stores on
1861fa7f10bSFabien Thomasthe same thread to be drained: load splitting across 4K boundary (page
1871fa7f10bSFabien Thomassplit), load accessing uncacheable (UC or USWC) memory, load lock, and load
1881fa7f10bSFabien Thomaswith page table in UC or USWC memory region.
1891fa7f10bSFabien Thomas.It Li STORE_BLOCKS.L1D_BLOCK
1901fa7f10bSFabien Thomas.Pq Event 06H , Umask 08H
1911fa7f10bSFabien ThomasCacheable loads delayed with L1D block code
1921fa7f10bSFabien Thomas.It Li PARTIAL_ADDRESS_ALIAS
1931fa7f10bSFabien Thomas.Pq Event 07H , Umask 01H
1941fa7f10bSFabien ThomasCounts false dependency due to partial address aliasing
1951fa7f10bSFabien Thomas.It Li DTLB_LOAD_MISSES.ANY
1961fa7f10bSFabien Thomas.Pq Event 08H , Umask 01H
1971fa7f10bSFabien ThomasCounts all load misses that cause a page walk
1981fa7f10bSFabien Thomas.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
1991fa7f10bSFabien Thomas.Pq Event 08H , Umask 02H
2001fa7f10bSFabien ThomasCounts number of completed page walks due to load miss in the STLB.
2011fa7f10bSFabien Thomas.It Li DTLB_LOAD_MISSES.WALK_CYCLES
2021fa7f10bSFabien Thomas.Pq Event 08H , Umask 04H
2031fa7f10bSFabien ThomasCycles PMH is busy with a page walk due to a load miss in the STLB.
2041fa7f10bSFabien Thomas.It Li DTLB_LOAD_MISSES.STLB_HIT
2051fa7f10bSFabien Thomas.Pq Event 08H , Umask 10H
2061fa7f10bSFabien ThomasNumber of cache load STLB hits
2071fa7f10bSFabien Thomas.It Li DTLB_LOAD_MISSES.PDE_MISS
2081fa7f10bSFabien Thomas.Pq Event 08H , Umask 20H
2091fa7f10bSFabien ThomasNumber of DTLB cache load misses where the low part of the linear to
2101fa7f10bSFabien Thomasphysical address translation was missed.
2111fa7f10bSFabien Thomas.It Li MEM_INST_RETIRED.LOADS
2121fa7f10bSFabien Thomas.Pq Event 0BH , Umask 01H
2131fa7f10bSFabien ThomasCounts the number of instructions with an architecturally-visible store
2141fa7f10bSFabien Thomasretired on the architected path.
2151fa7f10bSFabien ThomasIn conjunction with ld_lat facility
2161fa7f10bSFabien Thomas.It Li MEM_INST_RETIRED.STORES
2171fa7f10bSFabien Thomas.Pq Event 0BH , Umask 02H
2181fa7f10bSFabien ThomasCounts the number of instructions with an architecturally-visible store
2191fa7f10bSFabien Thomasretired on the architected path.
2201fa7f10bSFabien ThomasIn conjunction with ld_lat facility
2211fa7f10bSFabien Thomas.It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD
2221fa7f10bSFabien Thomas.Pq Event 0BH , Umask 10H
2231fa7f10bSFabien ThomasCounts the number of instructions exceeding the latency specified with
2241fa7f10bSFabien Thomasld_lat facility.
2251fa7f10bSFabien ThomasIn conjunction with ld_lat facility
2261fa7f10bSFabien Thomas.It Li MEM_STORE_RETIRED.DTLB_MISS
2271fa7f10bSFabien Thomas.Pq Event 0CH , Umask 01H
2281fa7f10bSFabien ThomasThe event counts the number of retired stores that missed the DTLB. The DTLB
2291fa7f10bSFabien Thomasmiss is not counted if the store operation causes a fault. Does not counter
2301fa7f10bSFabien Thomasprefetches. Counts both primary and secondary misses to the TLB
2311fa7f10bSFabien Thomas.It Li UOPS_ISSUED.ANY
2321fa7f10bSFabien Thomas.Pq Event 0EH , Umask 01H
2331fa7f10bSFabien ThomasCounts the number of Uops issued by the Register Allocation Table to the
2341fa7f10bSFabien ThomasReservation Station, i.e. the UOPs issued from the front end to the back
2351fa7f10bSFabien Thomasend.
2361fa7f10bSFabien Thomas.It Li UOPS_ISSUED.STALLED_CYCLES
2371fa7f10bSFabien Thomas.Pq Event 0EH , Umask 01H
2381fa7f10bSFabien ThomasCounts the number of cycles no Uops issued by the Register Allocation Table
2391fa7f10bSFabien Thomasto the Reservation Station, i.e. the UOPs issued from the front end to the
2401fa7f10bSFabien Thomasback end.
2411fa7f10bSFabien Thomasset invert=1, cmask = 1
2421fa7f10bSFabien Thomas.It Li UOPS_ISSUED.FUSED
2431fa7f10bSFabien Thomas.Pq Event 0EH , Umask 02H
2441fa7f10bSFabien ThomasCounts the number of fused Uops that were issued from the Register
2451fa7f10bSFabien ThomasAllocation Table to the Reservation Station.
2461fa7f10bSFabien Thomas.It Li MEM_UNCORE_RETIRED.LOCAL_HITM
2471fa7f10bSFabien Thomas.Pq Event 0FH , Umask 02H
2481fa7f10bSFabien ThomasLoad instructions retired that HIT modified data in sibling core (Precise
2491fa7f10bSFabien ThomasEvent)
2501fa7f10bSFabien Thomas.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT
2511fa7f10bSFabien Thomas.Pq Event 0FH , Umask 08H
2521fa7f10bSFabien ThomasLoad instructions retired local dram and remote cache HIT data sources
2531fa7f10bSFabien Thomas(Precise Event)
2541fa7f10bSFabien Thomas.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM
2551fa7f10bSFabien Thomas.Pq Event 0FH , Umask 10H
2561fa7f10bSFabien ThomasLoad instructions retired with a data source of local DRAM or locally homed
2571fa7f10bSFabien Thomasremote cache HITM (Precise Event)
2581fa7f10bSFabien Thomas.It Li MEM_UNCORE_RETIRED.REMOTE_DRAM
2591fa7f10bSFabien Thomas.Pq Event 0FH , Umask 20H
2601fa7f10bSFabien ThomasLoad instructions retired remote DRAM and remote home-remote cache HITM
2611fa7f10bSFabien Thomas(Precise Event)
2621fa7f10bSFabien Thomas.It Li MEM_UNCORE_RETIRED.UNCACHEABLE
2631fa7f10bSFabien Thomas.Pq Event 0FH , Umask 80H
2641fa7f10bSFabien ThomasLoad instructions retired I/O (Precise Event)
2651fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.X87
2661fa7f10bSFabien Thomas.Pq Event 10H , Umask 01H
2671fa7f10bSFabien ThomasCounts the number of FP Computational Uops Executed. The number of FADD,
2681fa7f10bSFabien ThomasFSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer
2691fa7f10bSFabien ThomasDIVs, and IDIVs. This event does not distinguish an FADD used in the middle
2701fa7f10bSFabien Thomasof a transcendental flow from a separate FADD instruction.
2711fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.MMX
2721fa7f10bSFabien Thomas.Pq Event 10H , Umask 02H
2731fa7f10bSFabien ThomasCounts number of MMX Uops executed.
2741fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE_FP
2751fa7f10bSFabien Thomas.Pq Event 10H , Umask 04H
2761fa7f10bSFabien ThomasCounts number of SSE and SSE2 FP uops executed.
2771fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE2_INTEGER
2781fa7f10bSFabien Thomas.Pq Event 10H , Umask 08H
2791fa7f10bSFabien ThomasCounts number of SSE2 integer uops executed.
2801fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED
2811fa7f10bSFabien Thomas.Pq Event 10H , Umask 10H
2821fa7f10bSFabien ThomasCounts number of SSE FP packed uops executed.
2831fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR
2841fa7f10bSFabien Thomas.Pq Event 10H , Umask 20H
2851fa7f10bSFabien ThomasCounts number of SSE FP scalar uops executed.
2861fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION
2871fa7f10bSFabien Thomas.Pq Event 10H , Umask 40H
2881fa7f10bSFabien ThomasCounts number of SSE* FP single precision uops executed.
2891fa7f10bSFabien Thomas.It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION
2901fa7f10bSFabien Thomas.Pq Event 10H , Umask 80H
2911fa7f10bSFabien ThomasCounts number of SSE* FP double precision uops executed.
2921fa7f10bSFabien Thomas.It Li SIMD_INT_128.PACKED_MPY
2931fa7f10bSFabien Thomas.Pq Event 12H , Umask 01H
2941fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer multiply operations.
2951fa7f10bSFabien Thomas.It Li SIMD_INT_128.PACKED_SHIFT
2961fa7f10bSFabien Thomas.Pq Event 12H , Umask 02H
2971fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer shift operations.
2981fa7f10bSFabien Thomas.It Li SIMD_INT_128.PACK
2991fa7f10bSFabien Thomas.Pq Event 12H , Umask 04H
3001fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer pack operations.
3011fa7f10bSFabien Thomas.It Li SIMD_INT_128.UNPACK
3021fa7f10bSFabien Thomas.Pq Event 12H , Umask 08H
3031fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer unpack operations.
3041fa7f10bSFabien Thomas.It Li SIMD_INT_128.PACKED_LOGICAL
3051fa7f10bSFabien Thomas.Pq Event 12H , Umask 10H
3061fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer logical operations.
3071fa7f10bSFabien Thomas.It Li SIMD_INT_128.PACKED_ARITH
3081fa7f10bSFabien Thomas.Pq Event 12H , Umask 20H
3091fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer arithmetic operations.
3101fa7f10bSFabien Thomas.It Li SIMD_INT_128.SHUFFLE_MOVE
3111fa7f10bSFabien Thomas.Pq Event 12H , Umask 40H
3121fa7f10bSFabien ThomasCounts number of 128 bit SIMD integer shuffle and move operations.
3131fa7f10bSFabien Thomas.It Li LOAD_DISPATCH.RS
3141fa7f10bSFabien Thomas.Pq Event 13H , Umask 01H
3151fa7f10bSFabien ThomasCounts number of loads dispatched from the Reservation Station that bypass
3161fa7f10bSFabien Thomasthe Memory Order Buffer.
3171fa7f10bSFabien Thomas.It Li LOAD_DISPATCH.RS_DELAYED
3181fa7f10bSFabien Thomas.Pq Event 13H , Umask 02H
3191fa7f10bSFabien ThomasCounts the number of delayed RS dispatches at the stage latch. If an RS
3201fa7f10bSFabien Thomasdispatch can not bypass to LB, it has another chance to dispatch from the
3211fa7f10bSFabien Thomasone-cycle delayed staging latch before it is written into the LB.
3221fa7f10bSFabien Thomas.It Li LOAD_DISPATCH.MOB
3231fa7f10bSFabien Thomas.Pq Event 13H , Umask 04H
3241fa7f10bSFabien ThomasCounts the number of loads dispatched from the Reservation Station to the
3251fa7f10bSFabien ThomasMemory Order Buffer.
3261fa7f10bSFabien Thomas.It Li LOAD_DISPATCH.ANY
3271fa7f10bSFabien Thomas.Pq Event 13H , Umask 07H
3281fa7f10bSFabien ThomasCounts all loads dispatched from the Reservation Station.
3291fa7f10bSFabien Thomas.It Li ARITH.CYCLES_DIV_BUSY
3301fa7f10bSFabien Thomas.Pq Event 14H , Umask 01H
3311fa7f10bSFabien ThomasCounts the number of cycles the divider is busy executing divide or square
3321fa7f10bSFabien Thomasroot operations. The divide can be integer, X87 or Streaming SIMD Extensions
3331fa7f10bSFabien Thomas(SSE). The square root operation can be either X87 or SSE.
3341fa7f10bSFabien ThomasSet 'edge =1, invert=1, cmask=1' to count the number of divides.
3351fa7f10bSFabien ThomasCount may be incorrect When SMT is on
3361fa7f10bSFabien Thomas.It Li ARITH.MUL
3371fa7f10bSFabien Thomas.Pq Event 14H , Umask 02H
3381fa7f10bSFabien ThomasCounts the number of multiply operations executed. This includes integer as
3391fa7f10bSFabien Thomaswell as floating point multiply operations but excludes DPPS mul and MPSAD.
3401fa7f10bSFabien ThomasCount may be incorrect When SMT is on
3411fa7f10bSFabien Thomas.It Li INST_QUEUE_WRITES
3421fa7f10bSFabien Thomas.Pq Event 17H , Umask 01H
3431fa7f10bSFabien ThomasCounts the number of instructions written into the instruction queue every
3441fa7f10bSFabien Thomascycle.
3451fa7f10bSFabien Thomas.It Li INST_DECODED.DEC0
3461fa7f10bSFabien Thomas.Pq Event 18H , Umask 01H
3471fa7f10bSFabien ThomasCounts number of instructions that require decoder 0 to be decoded. Usually,
3481fa7f10bSFabien Thomasthis means that the instruction maps to more than 1 uop
3491fa7f10bSFabien Thomas.It Li TWO_UOP_INSTS_DECODED
3501fa7f10bSFabien Thomas.Pq Event 19H , Umask 01H
3511fa7f10bSFabien ThomasAn instruction that generates two uops was decoded
3521fa7f10bSFabien Thomas.It Li INST_QUEUE_WRITE_CYCLES
3531fa7f10bSFabien Thomas.Pq Event 1EH , Umask 01H
3541fa7f10bSFabien ThomasThis event counts the number of cycles during which instructions are written
3551fa7f10bSFabien Thomasto the instruction queue. Dividing this counter by the number of
3561fa7f10bSFabien Thomasinstructions written to the instruction queue (INST_QUEUE_WRITES) yields the
3571fa7f10bSFabien Thomasaverage number of instructions decoded each cycle. If this number is less
3581fa7f10bSFabien Thomasthan four and the pipe stalls, this indicates that the decoder is failing to
3591fa7f10bSFabien Thomasdecode enough instructions per cycle to sustain the 4-wide pipeline.
3601fa7f10bSFabien ThomasIf SSE* instructions that are 6 bytes or longer arrive one after another,
3611fa7f10bSFabien Thomasthen front end throughput may limit execution speed. In such case,
3621fa7f10bSFabien Thomas.It Li LSD_OVERFLOW
3631fa7f10bSFabien Thomas.Pq Event 20H , Umask 01H
3641fa7f10bSFabien ThomasNumber of loops that can not stream from the instruction queue.
3651fa7f10bSFabien Thomas.It Li L2_RQSTS.LD_HIT
3661fa7f10bSFabien Thomas.Pq Event 24H , Umask 01H
3671fa7f10bSFabien ThomasCounts number of loads that hit the L2 cache. L2 loads include both L1D
3681fa7f10bSFabien Thomasdemand misses as well as L1D prefetches. L2 loads can be rejected for
3691fa7f10bSFabien Thomasvarious reasons. Only non rejected loads are counted.
3701fa7f10bSFabien Thomas.It Li L2_RQSTS.LD_MISS
3711fa7f10bSFabien Thomas.Pq Event 24H , Umask 02H
3721fa7f10bSFabien ThomasCounts the number of loads that miss the L2 cache. L2 loads include both L1D
3731fa7f10bSFabien Thomasdemand misses as well as L1D prefetches.
3741fa7f10bSFabien Thomas.It Li L2_RQSTS.LOADS
3751fa7f10bSFabien Thomas.Pq Event 24H , Umask 03H
3761fa7f10bSFabien ThomasCounts all L2 load requests. L2 loads include both L1D demand misses as well
3771fa7f10bSFabien Thomasas L1D prefetches.
3781fa7f10bSFabien Thomas.It Li L2_RQSTS.RFO_HIT
3791fa7f10bSFabien Thomas.Pq Event 24H , Umask 04H
3801fa7f10bSFabien ThomasCounts the number of store RFO requests that hit the L2 cache. L2 RFO
3811fa7f10bSFabien Thomasrequests include both L1D demand RFO misses as well as L1D RFO prefetches.
3821fa7f10bSFabien ThomasCount includes WC memory requests, where the data is not fetched but the
3831fa7f10bSFabien Thomaspermission to write the line is required.
3841fa7f10bSFabien Thomas.It Li L2_RQSTS.RFO_MISS
3851fa7f10bSFabien Thomas.Pq Event 24H , Umask 08H
3861fa7f10bSFabien ThomasCounts the number of store RFO requests that miss the L2 cache. L2 RFO
3871fa7f10bSFabien Thomasrequests include both L1D demand RFO misses as well as L1D RFO prefetches.
3881fa7f10bSFabien Thomas.It Li L2_RQSTS.RFOS
3891fa7f10bSFabien Thomas.Pq Event 24H , Umask 0CH
3901fa7f10bSFabien ThomasCounts all L2 store RFO requests. L2 RFO requests include both L1D demand
3911fa7f10bSFabien ThomasRFO misses as well as L1D RFO prefetches..
3921fa7f10bSFabien Thomas.It Li L2_RQSTS.IFETCH_HIT
3931fa7f10bSFabien Thomas.Pq Event 24H , Umask 10H
3941fa7f10bSFabien ThomasCounts number of instruction fetches that hit the L2 cache. L2 instruction
3951fa7f10bSFabien Thomasfetches include both L1I demand misses as well as L1I instruction
3961fa7f10bSFabien Thomasprefetches.
3971fa7f10bSFabien Thomas.It Li L2_RQSTS.IFETCH_MISS
3981fa7f10bSFabien Thomas.Pq Event 24H , Umask 20H
3991fa7f10bSFabien ThomasCounts number of instruction fetches that miss the L2 cache. L2 instruction
4001fa7f10bSFabien Thomasfetches include both L1I demand misses as well as L1I instruction
4011fa7f10bSFabien Thomasprefetches.
4021fa7f10bSFabien Thomas.It Li L2_RQSTS.IFETCHES
4031fa7f10bSFabien Thomas.Pq Event 24H , Umask 30H
4041fa7f10bSFabien ThomasCounts all instruction fetches. L2 instruction fetches include both L1I
4051fa7f10bSFabien Thomasdemand misses as well as L1I instruction prefetches.
4061fa7f10bSFabien Thomas.It Li L2_RQSTS.PREFETCH_HIT
4071fa7f10bSFabien Thomas.Pq Event 24H , Umask 40H
4081fa7f10bSFabien ThomasCounts L2 prefetch hits for both code and data.
4091fa7f10bSFabien Thomas.It Li L2_RQSTS.PREFETCH_MISS
4101fa7f10bSFabien Thomas.Pq Event 24H , Umask 80H
4111fa7f10bSFabien ThomasCounts L2 prefetch misses for both code and data.
4121fa7f10bSFabien Thomas.It Li L2_RQSTS.PREFETCHES
4131fa7f10bSFabien Thomas.Pq Event 24H , Umask C0H
4141fa7f10bSFabien ThomasCounts all L2 prefetches for both code and data.
4151fa7f10bSFabien Thomas.It Li L2_RQSTS.MISS
4161fa7f10bSFabien Thomas.Pq Event 24H , Umask AAH
4171fa7f10bSFabien ThomasCounts all L2 misses for both code and data.
4181fa7f10bSFabien Thomas.It Li L2_RQSTS.REFERENCES
4191fa7f10bSFabien Thomas.Pq Event 24H , Umask FFH
4201fa7f10bSFabien ThomasCounts all L2 requests for both code and data.
4211fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.DEMAND.I_STATE
4221fa7f10bSFabien Thomas.Pq Event 26H , Umask 01H
4231fa7f10bSFabien ThomasCounts number of L2 data demand loads where the cache line to be loaded is
4241fa7f10bSFabien Thomasin the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D
4251fa7f10bSFabien Thomasdemand misses and L1D prefetches.
4261fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.DEMAND.S_STATE
4271fa7f10bSFabien Thomas.Pq Event 26H , Umask 02H
4281fa7f10bSFabien ThomasCounts number of L2 data demand loads where the cache line to be loaded is
4291fa7f10bSFabien Thomasin the S (shared) state. L2 demand loads are both L1D demand misses and L1D
4301fa7f10bSFabien Thomasprefetches.
4311fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.DEMAND.E_STATE
4321fa7f10bSFabien Thomas.Pq Event 26H , Umask 04H
4331fa7f10bSFabien ThomasCounts number of L2 data demand loads where the cache line to be loaded is
4341fa7f10bSFabien Thomasin the E (exclusive) state. L2 demand loads are both L1D demand misses and
4351fa7f10bSFabien ThomasL1D prefetches.
4361fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.DEMAND.M_STATE
4371fa7f10bSFabien Thomas.Pq Event 26H , Umask 08H
4381fa7f10bSFabien ThomasCounts number of L2 data demand loads where the cache line to be loaded is
4391fa7f10bSFabien Thomasin the M (modified) state. L2 demand loads are both L1D demand misses and
4401fa7f10bSFabien ThomasL1D prefetches.
4411fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.DEMAND.MESI
4421fa7f10bSFabien Thomas.Pq Event 26H , Umask 0FH
4431fa7f10bSFabien ThomasCounts all L2 data demand requests. L2 demand loads are both L1D demand
4441fa7f10bSFabien Thomasmisses and L1D prefetches.
4451fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.PREFETCH.I_STATE
4461fa7f10bSFabien Thomas.Pq Event 26H , Umask 10H
4471fa7f10bSFabien ThomasCounts number of L2 prefetch data loads where the cache line to be loaded is
4481fa7f10bSFabien Thomasin the I (invalid) state, i.e. a cache miss.
4491fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.PREFETCH.S_STATE
4501fa7f10bSFabien Thomas.Pq Event 26H , Umask 20H
4511fa7f10bSFabien ThomasCounts number of L2 prefetch data loads where the cache line to be loaded is
4521fa7f10bSFabien Thomasin the S (shared) state. A prefetch RFO will miss on an S state line, while
4531fa7f10bSFabien Thomasa prefetch read will hit on an S state line.
4541fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.PREFETCH.E_STATE
4551fa7f10bSFabien Thomas.Pq Event 26H , Umask 40H
4561fa7f10bSFabien ThomasCounts number of L2 prefetch data loads where the cache line to be loaded is
4571fa7f10bSFabien Thomasin the E (exclusive) state.
4581fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.PREFETCH.M_STATE
4591fa7f10bSFabien Thomas.Pq Event 26H , Umask 80H
4601fa7f10bSFabien ThomasCounts number of L2 prefetch data loads where the cache line to be loaded is
4611fa7f10bSFabien Thomasin the M (modified) state.
4621fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.PREFETCH.MESI
4631fa7f10bSFabien Thomas.Pq Event 26H , Umask F0H
4641fa7f10bSFabien ThomasCounts all L2 prefetch requests.
4651fa7f10bSFabien Thomas.It Li L2_DATA_RQSTS.ANY
4661fa7f10bSFabien Thomas.Pq Event 26H , Umask FFH
4671fa7f10bSFabien ThomasCounts all L2 data requests.
4681fa7f10bSFabien Thomas.It Li L2_WRITE.RFO.I_STATE
4691fa7f10bSFabien Thomas.Pq Event 27H , Umask 01H
4701fa7f10bSFabien ThomasCounts number of L2 demand store RFO requests where the cache line to be
4711fa7f10bSFabien Thomasloaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher
4721fa7f10bSFabien Thomasdoes not issue a RFO prefetch.
4731fa7f10bSFabien ThomasThis is a demand RFO request
4741fa7f10bSFabien Thomas.It Li L2_WRITE.RFO.S_STATE
4751fa7f10bSFabien Thomas.Pq Event 27H , Umask 02H
4761fa7f10bSFabien ThomasCounts number of L2 store RFO requests where the cache line to be loaded is
4771fa7f10bSFabien Thomasin the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,.
4781fa7f10bSFabien ThomasThis is a demand RFO request
4791fa7f10bSFabien Thomas.It Li L2_WRITE.RFO.M_STATE
4801fa7f10bSFabien Thomas.Pq Event 27H , Umask 08H
4811fa7f10bSFabien ThomasCounts number of L2 store RFO requests where the cache line to be loaded is
4821fa7f10bSFabien Thomasin the M (modified) state. The L1D prefetcher does not issue a RFO prefetch.
4831fa7f10bSFabien ThomasThis is a demand RFO request
4841fa7f10bSFabien Thomas.It Li L2_WRITE.RFO.HIT
4851fa7f10bSFabien Thomas.Pq Event 27H , Umask 0EH
4861fa7f10bSFabien ThomasCounts number of L2 store RFO requests where the cache line to be loaded is
4871fa7f10bSFabien Thomasin either the S, E or M states. The L1D prefetcher does not issue a RFO
4881fa7f10bSFabien Thomasprefetch.
4891fa7f10bSFabien ThomasThis is a demand RFO request
4901fa7f10bSFabien Thomas.It Li L2_WRITE.RFO.MESI
4911fa7f10bSFabien Thomas.Pq Event 27H , Umask 0FH
4921fa7f10bSFabien ThomasCounts all L2 store RFO requests.The L1D prefetcher does not issue a RFO
4931fa7f10bSFabien Thomasprefetch.
4941fa7f10bSFabien ThomasThis is a demand RFO request
4951fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.I_STATE
4961fa7f10bSFabien Thomas.Pq Event 27H , Umask 10H
4971fa7f10bSFabien ThomasCounts number of L2 demand lock RFO requests where the cache line to be
4981fa7f10bSFabien Thomasloaded is in the I (invalid) state, i.e. a cache miss.
4991fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.S_STATE
5001fa7f10bSFabien Thomas.Pq Event 27H , Umask 20H
5011fa7f10bSFabien ThomasCounts number of L2 lock RFO requests where the cache line to be loaded is
5021fa7f10bSFabien Thomasin the S (shared) state.
5031fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.E_STATE
5041fa7f10bSFabien Thomas.Pq Event 27H , Umask 40H
5051fa7f10bSFabien ThomasCounts number of L2 demand lock RFO requests where the cache line to be
5061fa7f10bSFabien Thomasloaded is in the E (exclusive) state.
5071fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.M_STATE
5081fa7f10bSFabien Thomas.Pq Event 27H , Umask 80H
5091fa7f10bSFabien ThomasCounts number of L2 demand lock RFO requests where the cache line to be
5101fa7f10bSFabien Thomasloaded is in the M (modified) state.
5111fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.HIT
5121fa7f10bSFabien Thomas.Pq Event 27H , Umask E0H
5131fa7f10bSFabien ThomasCounts number of L2 demand lock RFO requests where the cache line to be
5141fa7f10bSFabien Thomasloaded is in either the S, E, or M state.
5151fa7f10bSFabien Thomas.It Li L2_WRITE.LOCK.MESI
5161fa7f10bSFabien Thomas.Pq Event 27H , Umask F0H
5171fa7f10bSFabien ThomasCounts all L2 demand lock RFO requests.
5181fa7f10bSFabien Thomas.It Li L1D_WB_L2.I_STATE
5191fa7f10bSFabien Thomas.Pq Event 28H , Umask 01H
5201fa7f10bSFabien ThomasCounts number of L1 writebacks to the L2 where the cache line to be written
5211fa7f10bSFabien Thomasis in the I (invalid) state, i.e. a cache miss.
5221fa7f10bSFabien Thomas.It Li L1D_WB_L2.S_STATE
5231fa7f10bSFabien Thomas.Pq Event 28H , Umask 02H
5241fa7f10bSFabien ThomasCounts number of L1 writebacks to the L2 where the cache line to be written
5251fa7f10bSFabien Thomasis in the S state.
5261fa7f10bSFabien Thomas.It Li L1D_WB_L2.E_STATE
5271fa7f10bSFabien Thomas.Pq Event 28H , Umask 04H
5281fa7f10bSFabien ThomasCounts number of L1 writebacks to the L2 where the cache line to be written
5291fa7f10bSFabien Thomasis in the E (exclusive) state.
5301fa7f10bSFabien Thomas.It Li L1D_WB_L2.M_STATE
5311fa7f10bSFabien Thomas.Pq Event 28H , Umask 08H
5321fa7f10bSFabien ThomasCounts number of L1 writebacks to the L2 where the cache line to be written
5331fa7f10bSFabien Thomasis in the M (modified) state.
5341fa7f10bSFabien Thomas.It Li L1D_WB_L2.MESI
5351fa7f10bSFabien Thomas.Pq Event 28H , Umask 0FH
5361fa7f10bSFabien ThomasCounts all L1 writebacks to the L2.
5371fa7f10bSFabien Thomas.It Li L3_LAT_CACHE.REFERENCE
5381fa7f10bSFabien Thomas.Pq Event 2EH , Umask 02H
5391fa7f10bSFabien ThomasCounts uncore Last Level Cache references. Because cache hierarchy, cache
5401fa7f10bSFabien Thomassizes and other implementation-specific characteristics; value comparison to
5411fa7f10bSFabien Thomasestimate performance differences is not recommended.
5421fa7f10bSFabien Thomassee Table A-1
5431fa7f10bSFabien Thomas.It Li L3_LAT_CACHE.MISS
5441fa7f10bSFabien Thomas.Pq Event 2EH , Umask 01H
5451fa7f10bSFabien ThomasCounts uncore Last Level Cache misses. Because cache hierarchy, cache sizes
5461fa7f10bSFabien Thomasand other implementation-specific characteristics; value comparison to
5471fa7f10bSFabien Thomasestimate performance differences is not recommended.
5481fa7f10bSFabien Thomassee Table A-1
5491fa7f10bSFabien Thomas.It Li CPU_CLK_UNHALTED.THREAD_P
5501fa7f10bSFabien Thomas.Pq Event 3CH , Umask 00H
5511fa7f10bSFabien ThomasCounts the number of thread cycles while the thread is not in a halt state.
5521fa7f10bSFabien ThomasThe thread enters the halt state when it is running the HLT instruction. The
5531fa7f10bSFabien Thomascore frequency may change from time to time due to power or thermal
5541fa7f10bSFabien Thomasthrottling.
5551fa7f10bSFabien Thomassee Table A-1
5561fa7f10bSFabien Thomas.It Li CPU_CLK_UNHALTED.REF_P
5571fa7f10bSFabien Thomas.Pq Event 3CH , Umask 01H
5581fa7f10bSFabien ThomasIncrements at the frequency of TSC when not halted.
5591fa7f10bSFabien Thomassee Table A-1
5601fa7f10bSFabien Thomas.It Li DTLB_MISSES.ANY
5611fa7f10bSFabien Thomas.Pq Event 49H , Umask 01H
5621fa7f10bSFabien ThomasCounts the number of misses in the STLB which causes a page walk.
5631fa7f10bSFabien Thomas.It Li DTLB_MISSES.WALK_COMPLETED
5641fa7f10bSFabien Thomas.Pq Event 49H , Umask 02H
5651fa7f10bSFabien ThomasCounts number of misses in the STLB which resulted in a completed page walk.
5661fa7f10bSFabien Thomas.It Li DTLB_MISSES.WALK_CYCLES
5671fa7f10bSFabien Thomas.Pq Event 49H , Umask 04H
5681fa7f10bSFabien ThomasCounts cycles of page walk due to misses in the STLB.
5691fa7f10bSFabien Thomas.It Li DTLB_MISSES.STLB_HIT
5701fa7f10bSFabien Thomas.Pq Event 49H , Umask 10H
5711fa7f10bSFabien ThomasCounts the number of DTLB first level misses that hit in the second level
5721fa7f10bSFabien ThomasTLB. This event is only relevant if the core contains multiple DTLB levels.
5731fa7f10bSFabien Thomas.It Li DTLB_MISSES.LARGE_WALK_COMPLETED
5741fa7f10bSFabien Thomas.Pq Event 49H , Umask 80H
5751fa7f10bSFabien ThomasCounts number of completed large page walks due to misses in the STLB.
5761fa7f10bSFabien Thomas.It Li LOAD_HIT_PRE
5771fa7f10bSFabien Thomas.Pq Event 4CH , Umask 01H
5781fa7f10bSFabien ThomasCounts load operations sent to the L1 data cache while a previous SSE
5791fa7f10bSFabien Thomasprefetch instruction to the same cache line has started prefetching but has
5801fa7f10bSFabien Thomasnot yet finished.
5811fa7f10bSFabien Thomas.It Li L1D_PREFETCH.REQUESTS
5821fa7f10bSFabien Thomas.Pq Event 4EH , Umask 01H
5831fa7f10bSFabien ThomasCounts number of hardware prefetch requests dispatched out of the prefetch
5841fa7f10bSFabien ThomasFIFO.
5851fa7f10bSFabien Thomas.It Li L1D_PREFETCH.MISS
5861fa7f10bSFabien Thomas.Pq Event 4EH , Umask 02H
5871fa7f10bSFabien ThomasCounts number of hardware prefetch requests that miss the L1D. There are two
5881fa7f10bSFabien Thomasprefetchers in the L1D. A streamer, which predicts lines sequentially after
5891fa7f10bSFabien Thomasthis one should be fetched, and the IP prefetcher that remembers access
5901fa7f10bSFabien Thomaspatterns for the current instruction. The streamer prefetcher stops on an
5911fa7f10bSFabien ThomasL1D hit, while the IP prefetcher does not.
5921fa7f10bSFabien Thomas.It Li L1D_PREFETCH.TRIGGERS
5931fa7f10bSFabien Thomas.Pq Event 4EH , Umask 04H
5941fa7f10bSFabien ThomasCounts number of prefetch requests triggered by the Finite State Machine and
5951fa7f10bSFabien Thomaspushed into the prefetch FIFO. Some of the prefetch requests are dropped due
5961fa7f10bSFabien Thomasto overwrites or competition between the IP index prefetcher and streamer
5971fa7f10bSFabien Thomasprefetcher. The prefetch FIFO contains 4 entries.
5981fa7f10bSFabien Thomas.It Li EPT.WALK_CYCLES
5991fa7f10bSFabien Thomas.Pq Event 4FH , Umask 10H
6001fa7f10bSFabien ThomasCounts Extended Page walk cycles.
6011fa7f10bSFabien Thomas.It Li L1D.REPL
6021fa7f10bSFabien Thomas.Pq Event 51H , Umask 01H
6031fa7f10bSFabien ThomasCounts the number of lines brought into the L1 data cache.
6041fa7f10bSFabien ThomasCounter 0, 1 only
6051fa7f10bSFabien Thomas.It Li L1D.M_REPL
6061fa7f10bSFabien Thomas.Pq Event 51H , Umask 02H
6071fa7f10bSFabien ThomasCounts the number of modified lines brought into the L1 data cache.
6081fa7f10bSFabien ThomasCounter 0, 1 only
6091fa7f10bSFabien Thomas.It Li L1D.M_EVICT
6101fa7f10bSFabien Thomas.Pq Event 51H , Umask 04H
6111fa7f10bSFabien ThomasCounts the number of modified lines evicted from the L1 data cache due to
6121fa7f10bSFabien Thomasreplacement.
6131fa7f10bSFabien ThomasCounter 0, 1 only
6141fa7f10bSFabien Thomas.It Li L1D.M_SNOOP_EVICT
6151fa7f10bSFabien Thomas.Pq Event 51H , Umask 08H
6161fa7f10bSFabien ThomasCounts the number of modified lines evicted from the L1 data cache due to
6171fa7f10bSFabien Thomassnoop HITM intervention.
6181fa7f10bSFabien ThomasCounter 0, 1 only
6191fa7f10bSFabien Thomas.It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT
6201fa7f10bSFabien Thomas.Pq Event 52H , Umask 01H
6211fa7f10bSFabien ThomasCounts the number of cacheable load lock speculated instructions accepted
6221fa7f10bSFabien Thomasinto the fill buffer.
6231fa7f10bSFabien Thomas.It Li L1D_CACHE_LOCK_FB_HIT
6241fa7f10bSFabien Thomas.Pq Event 53H , Umask 01H
6251fa7f10bSFabien ThomasCounts the number of cacheable load lock speculated or retired instructions
6261fa7f10bSFabien Thomasaccepted into the fill buffer.
6271fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA
6281fa7f10bSFabien Thomas.Pq Event 60H , Umask 01H
6291fa7f10bSFabien ThomasCounts weighted cycles of offcore demand data read requests. Does not
6301fa7f10bSFabien Thomasinclude L2 prefetch requests.
6311fa7f10bSFabien Thomascounter 0
6321fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE
6331fa7f10bSFabien Thomas.Pq Event 60H , Umask 02H
6341fa7f10bSFabien ThomasCounts weighted cycles of offcore demand code read requests. Does not
6351fa7f10bSFabien Thomasinclude L2 prefetch requests.
6361fa7f10bSFabien Thomascounter 0
6371fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO
6381fa7f10bSFabien Thomas.Pq Event 60H , Umask 04H
6391fa7f10bSFabien ThomasCounts weighted cycles of offcore demand RFO requests. Does not include L2
6401fa7f10bSFabien Thomasprefetch requests.
6411fa7f10bSFabien Thomascounter 0
6421fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ
6431fa7f10bSFabien Thomas.Pq Event 60H , Umask 08H
6441fa7f10bSFabien ThomasCounts weighted cycles of offcore read requests of any kind. Include L2
6451fa7f10bSFabien Thomasprefetch requests.
6461fa7f10bSFabien Thomascounter 0
6471fa7f10bSFabien Thomas.It Li CACHE_LOCK_CYCLES.L1D_L2
6481fa7f10bSFabien Thomas.Pq Event 63H , Umask 01H
6491fa7f10bSFabien ThomasCycle count during which the L1D and L2 are locked. A lock is asserted when
6501fa7f10bSFabien Thomasthere is a locked memory access, due to uncacheable memory, a locked
6511fa7f10bSFabien Thomasoperation that spans two cache lines, or a page walk from an uncacheable
6521fa7f10bSFabien Thomaspage table.
6531fa7f10bSFabien ThomasCounter 0, 1 only. L1D and L2 locks have a very high performance penalty and
6541fa7f10bSFabien Thomasit is highly recommended to avoid such accesses.
6551fa7f10bSFabien Thomas.It Li CACHE_LOCK_CYCLES.L1D
6561fa7f10bSFabien Thomas.Pq Event 63H , Umask 02H
6571fa7f10bSFabien ThomasCounts the number of cycles that cacheline in the L1 data cache unit is
6581fa7f10bSFabien Thomaslocked.
6591fa7f10bSFabien ThomasCounter 0, 1 only.
6601fa7f10bSFabien Thomas.It Li IO_TRANSACTIONS
6611fa7f10bSFabien Thomas.Pq Event 6CH , Umask 01H
6621fa7f10bSFabien ThomasCounts the number of completed I/O transactions.
6631fa7f10bSFabien Thomas.It Li L1I.HITS
6641fa7f10bSFabien Thomas.Pq Event 80H , Umask 01H
6651fa7f10bSFabien ThomasCounts all instruction fetches that hit the L1 instruction cache.
6661fa7f10bSFabien Thomas.It Li L1I.MISSES
6671fa7f10bSFabien Thomas.Pq Event 80H , Umask 02H
6681fa7f10bSFabien ThomasCounts all instruction fetches that miss the L1I cache. This includes
6691fa7f10bSFabien Thomasinstruction cache misses, streaming buffer misses, victim cache misses and
6701fa7f10bSFabien Thomasuncacheable fetches. An instruction fetch miss is counted only once and not
6711fa7f10bSFabien Thomasonce for every cycle it is outstanding.
6721fa7f10bSFabien Thomas.It Li L1I.READS
6731fa7f10bSFabien Thomas.Pq Event 80H , Umask 03H
6741fa7f10bSFabien ThomasCounts all instruction fetches, including uncacheable fetches that bypass
6751fa7f10bSFabien Thomasthe L1I.
6761fa7f10bSFabien Thomas.It Li L1I.CYCLES_STALLED
6771fa7f10bSFabien Thomas.Pq Event 80H , Umask 04H
6781fa7f10bSFabien ThomasCycle counts for which an instruction fetch stalls due to a L1I cache miss,
6791fa7f10bSFabien ThomasITLB miss or ITLB fault.
6801fa7f10bSFabien Thomas.It Li LARGE_ITLB.HIT
6811fa7f10bSFabien Thomas.Pq Event 82H , Umask 01H
6821fa7f10bSFabien ThomasCounts number of large ITLB hits.
6831fa7f10bSFabien Thomas.It Li ITLB_MISSES.ANY
6841fa7f10bSFabien Thomas.Pq Event 85H , Umask 01H
6851fa7f10bSFabien ThomasCounts the number of misses in all levels of the ITLB which causes a page
6861fa7f10bSFabien Thomaswalk.
6871fa7f10bSFabien Thomas.It Li ITLB_MISSES.WALK_COMPLETED
6881fa7f10bSFabien Thomas.Pq Event 85H , Umask 02H
6891fa7f10bSFabien ThomasCounts number of misses in all levels of the ITLB which resulted in a
6901fa7f10bSFabien Thomascompleted page walk.
6911fa7f10bSFabien Thomas.It Li ITLB_MISSES.WALK_CYCLES
6921fa7f10bSFabien Thomas.Pq Event 85H , Umask 04H
6931fa7f10bSFabien ThomasCounts ITLB miss page walk cycles.
6941fa7f10bSFabien Thomas.It Li ITLB_MISSES.LARGE_WALK_COMPLETED
6951fa7f10bSFabien Thomas.Pq Event 85H , Umask 80H
6961fa7f10bSFabien ThomasCounts number of completed large page walks due to misses in the STLB.
6971fa7f10bSFabien Thomas.It Li ILD_STALL.LCP
6981fa7f10bSFabien Thomas.Pq Event 87H , Umask 01H
6991fa7f10bSFabien ThomasCycles Instruction Length Decoder stalls due to length changing prefixes:
7001fa7f10bSFabien Thomas66, 67 or REX.W (for EM64T) instructions which change the length of the
7011fa7f10bSFabien Thomasdecoded instruction.
7021fa7f10bSFabien Thomas.It Li ILD_STALL.MRU
7031fa7f10bSFabien Thomas.Pq Event 87H , Umask 02H
7041fa7f10bSFabien ThomasInstruction Length Decoder stall cycles due to Brand Prediction Unit (PBU)
7051fa7f10bSFabien ThomasMost Recently Used (MRU) bypass.
7061fa7f10bSFabien Thomas.It Li ILD_STALL.IQ_FULL
7071fa7f10bSFabien Thomas.Pq Event 87H , Umask 04H
7081fa7f10bSFabien ThomasStall cycles due to a full instruction queue.
7091fa7f10bSFabien Thomas.It Li ILD_STALL.REGEN
7101fa7f10bSFabien Thomas.Pq Event 87H , Umask 08H
7111fa7f10bSFabien ThomasCounts the number of regen stalls.
7121fa7f10bSFabien Thomas.It Li ILD_STALL.ANY
7131fa7f10bSFabien Thomas.Pq Event 87H , Umask 0FH
7141fa7f10bSFabien ThomasCounts any cycles the Instruction Length Decoder is stalled.
7151fa7f10bSFabien Thomas.It Li BR_INST_EXEC.COND
7161fa7f10bSFabien Thomas.Pq Event 88H , Umask 01H
7171fa7f10bSFabien ThomasCounts the number of conditional near branch instructions executed, but not
7181fa7f10bSFabien Thomasnecessarily retired.
7191fa7f10bSFabien Thomas.It Li BR_INST_EXEC.DIRECT
7201fa7f10bSFabien Thomas.Pq Event 88H , Umask 02H
7211fa7f10bSFabien ThomasCounts all unconditional near branch instructions excluding calls and
7221fa7f10bSFabien Thomasindirect branches.
7231fa7f10bSFabien Thomas.It Li BR_INST_EXEC.INDIRECT_NON_CALL
7241fa7f10bSFabien Thomas.Pq Event 88H , Umask 04H
7251fa7f10bSFabien ThomasCounts the number of executed indirect near branch instructions that are not
7261fa7f10bSFabien Thomascalls.
7271fa7f10bSFabien Thomas.It Li BR_INST_EXEC.NON_CALLS
7281fa7f10bSFabien Thomas.Pq Event 88H , Umask 07H
7291fa7f10bSFabien ThomasCounts all non call near branch instructions executed, but not necessarily
7301fa7f10bSFabien Thomasretired.
7311fa7f10bSFabien Thomas.It Li BR_INST_EXEC.RETURN_NEAR
7321fa7f10bSFabien Thomas.Pq Event 88H , Umask 08H
7331fa7f10bSFabien ThomasCounts indirect near branches that have a return mnemonic.
7341fa7f10bSFabien Thomas.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
7351fa7f10bSFabien Thomas.Pq Event 88H , Umask 10H
7361fa7f10bSFabien ThomasCounts unconditional near call branch instructions, excluding non call
7371fa7f10bSFabien Thomasbranch, executed.
7381fa7f10bSFabien Thomas.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
7391fa7f10bSFabien Thomas.Pq Event 88H , Umask 20H
7401fa7f10bSFabien ThomasCounts indirect near calls, including both register and memory indirect,
7411fa7f10bSFabien Thomasexecuted.
7421fa7f10bSFabien Thomas.It Li BR_INST_EXEC.NEAR_CALLS
7431fa7f10bSFabien Thomas.Pq Event 88H , Umask 30H
7441fa7f10bSFabien ThomasCounts all near call branches executed, but not necessarily retired.
7451fa7f10bSFabien Thomas.It Li BR_INST_EXEC.TAKEN
7461fa7f10bSFabien Thomas.Pq Event 88H , Umask 40H
7471fa7f10bSFabien ThomasCounts taken near branches executed, but not necessarily retired.
7481fa7f10bSFabien Thomas.It Li BR_INST_EXEC.ANY
7491fa7f10bSFabien Thomas.Pq Event 88H , Umask 7FH
7501fa7f10bSFabien ThomasCounts all near executed branches (not necessarily retired). This includes
7511fa7f10bSFabien Thomasonly instructions and not micro-op branches. Frequent branching is not
7521fa7f10bSFabien Thomasnecessarily a major performance issue. However frequent branch
7531fa7f10bSFabien Thomasmispredictions may be a problem.
7541fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.COND
7551fa7f10bSFabien Thomas.Pq Event 89H , Umask 01H
7561fa7f10bSFabien ThomasCounts the number of mispredicted conditional near branch instructions
7571fa7f10bSFabien Thomasexecuted, but not necessarily retired.
7581fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.DIRECT
7591fa7f10bSFabien Thomas.Pq Event 89H , Umask 02H
7601fa7f10bSFabien ThomasCounts mispredicted macro unconditional near branch instructions, excluding
7611fa7f10bSFabien Thomascalls and indirect branches (should always be 0).
7621fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.INDIRECT_NON_CALL
7631fa7f10bSFabien Thomas.Pq Event 89H , Umask 04H
7641fa7f10bSFabien ThomasCounts the number of executed mispredicted indirect near branch instructions
7651fa7f10bSFabien Thomasthat are not calls.
7661fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.NON_CALLS
7671fa7f10bSFabien Thomas.Pq Event 89H , Umask 07H
7681fa7f10bSFabien ThomasCounts mispredicted non call near branches executed, but not necessarily
7691fa7f10bSFabien Thomasretired.
7701fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.RETURN_NEAR
7711fa7f10bSFabien Thomas.Pq Event 89H , Umask 08H
7721fa7f10bSFabien ThomasCounts mispredicted indirect branches that have a rear return mnemonic.
7731fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
7741fa7f10bSFabien Thomas.Pq Event 89H , Umask 10H
7751fa7f10bSFabien ThomasCounts mispredicted non-indirect near calls executed, (should always be 0).
7761fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
7771fa7f10bSFabien Thomas.Pq Event 89H , Umask 20H
778f6ac2391SJoel DahlCounts mispredicted indirect near calls executed, including both register
7791fa7f10bSFabien Thomasand memory indirect.
7801fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.NEAR_CALLS
7811fa7f10bSFabien Thomas.Pq Event 89H , Umask 30H
7821fa7f10bSFabien ThomasCounts all mispredicted near call branches executed, but not necessarily
7831fa7f10bSFabien Thomasretired.
7841fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.TAKEN
7851fa7f10bSFabien Thomas.Pq Event 89H , Umask 40H
7861fa7f10bSFabien ThomasCounts executed mispredicted near branches that are taken, but not
7871fa7f10bSFabien Thomasnecessarily retired.
7881fa7f10bSFabien Thomas.It Li BR_MISP_EXEC.ANY
7891fa7f10bSFabien Thomas.Pq Event 89H , Umask 7FH
7901fa7f10bSFabien ThomasCounts the number of mispredicted near branch instructions that were
7911fa7f10bSFabien Thomasexecuted, but not necessarily retired.
7921fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.ANY
7931fa7f10bSFabien Thomas.Pq Event A2H , Umask 01H
7941fa7f10bSFabien ThomasCounts the number of Allocator resource related stalls. Includes register
7951fa7f10bSFabien Thomasrenaming buffer entries, memory buffer entries. In addition to resource
7961fa7f10bSFabien Thomasrelated stalls, this event counts some other events. Includes stalls arising
7971fa7f10bSFabien Thomasduring branch misprediction recovery, such as if retirement of the
7981fa7f10bSFabien Thomasmispredicted branch is delayed and stalls arising while store buffer is
7991fa7f10bSFabien Thomasdraining from synchronizing operations.
8001fa7f10bSFabien ThomasDoes not include stalls due to SuperQ (off core) queue full, too many cache
8011fa7f10bSFabien Thomasmisses, etc.
8021fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.LOAD
8031fa7f10bSFabien Thomas.Pq Event A2H , Umask 02H
8041fa7f10bSFabien ThomasCounts the cycles of stall due to lack of load buffer for load operation.
8051fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.RS_FULL
8061fa7f10bSFabien Thomas.Pq Event A2H , Umask 04H
8071fa7f10bSFabien ThomasThis event counts the number of cycles when the number of instructions in
8081fa7f10bSFabien Thomasthe pipeline waiting for execution reaches the limit the processor can
8091fa7f10bSFabien Thomashandle. A high count of this event indicates that there are long latency
8101fa7f10bSFabien Thomasoperations in the pipe (possibly load and store operations that miss the L2
8111fa7f10bSFabien Thomascache, or instructions dependent upon instructions further down the pipeline
8121fa7f10bSFabien Thomasthat have yet to retire.
8131fa7f10bSFabien ThomasWhen RS is full, new instructions can not enter the reservation station and
8141fa7f10bSFabien Thomasstart execution.
8151fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.STORE
8161fa7f10bSFabien Thomas.Pq Event A2H , Umask 08H
8171fa7f10bSFabien ThomasThis event counts the number of cycles that a resource related stall will
8181fa7f10bSFabien Thomasoccur due to the number of store instructions reaching the limit of the
8191fa7f10bSFabien Thomaspipeline, (i.e. all store buffers are used). The stall ends when a store
8201fa7f10bSFabien Thomasinstruction commits its data to the cache or memory.
8211fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.ROB_FULL
8221fa7f10bSFabien Thomas.Pq Event A2H , Umask 10H
8231fa7f10bSFabien ThomasCounts the cycles of stall due to re- order buffer full.
8241fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.FPCW
8251fa7f10bSFabien Thomas.Pq Event A2H , Umask 20H
8261fa7f10bSFabien ThomasCounts the number of cycles while execution was stalled due to writing the
8271fa7f10bSFabien Thomasfloating-point unit (FPU) control word.
8281fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.MXCSR
8291fa7f10bSFabien Thomas.Pq Event A2H , Umask 40H
8301fa7f10bSFabien ThomasStalls due to the MXCSR register rename occurring to close to a previous
8311fa7f10bSFabien ThomasMXCSR rename. The MXCSR provides control and status for the MMX registers.
8321fa7f10bSFabien Thomas.It Li RESOURCE_STALLS.OTHER
8331fa7f10bSFabien Thomas.Pq Event A2H , Umask 80H
8341fa7f10bSFabien ThomasCounts the number of cycles while execution was stalled due to other
8351fa7f10bSFabien Thomasresource issues.
8361fa7f10bSFabien Thomas.It Li MACRO_INSTS.FUSIONS_DECODED
8371fa7f10bSFabien Thomas.Pq Event A6H , Umask 01H
8381fa7f10bSFabien ThomasCounts the number of instructions decoded that are macro-fused but not
8391fa7f10bSFabien Thomasnecessarily executed or retired.
8401fa7f10bSFabien Thomas.It Li BACLEAR_FORCE_IQ
8411fa7f10bSFabien Thomas.Pq Event A7H , Umask 01H
8421fa7f10bSFabien ThomasCounts number of times a BACLEAR was forced by the Instruction Queue. The IQ
843799162a6SJoel Dahlis also responsible for providing conditional branch prediction direction
8441fa7f10bSFabien Thomasbased on a static scheme and dynamic data provided by the L2 Branch
8451fa7f10bSFabien ThomasPrediction Unit. If the conditional branch target is not found in the Target
8461fa7f10bSFabien ThomasArray and the IQ predicts that the branch is taken, then the IQ will force
8471fa7f10bSFabien Thomasthe Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by
8481fa7f10bSFabien Thomasthe BAC generates approximately an 8 cycle bubble in the instruction fetch
8491fa7f10bSFabien Thomaspipeline.
8501fa7f10bSFabien Thomas.It Li LSD.UOPS
8511fa7f10bSFabien Thomas.Pq Event A8H , Umask 01H
8521fa7f10bSFabien ThomasCounts the number of micro-ops delivered by loop stream detector
8531fa7f10bSFabien ThomasUse cmask=1 and invert to count cycles
8541fa7f10bSFabien Thomas.It Li ITLB_FLUSH
8551fa7f10bSFabien Thomas.Pq Event AEH , Umask 01H
8561fa7f10bSFabien ThomasCounts the number of ITLB flushes
8571fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.DEMAND.READ_DATA
8581fa7f10bSFabien Thomas.Pq Event B0H , Umask 01H
8591fa7f10bSFabien ThomasCounts number of offcore demand data read requests. Does not count L2
8601fa7f10bSFabien Thomasprefetch requests.
8611fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE
8621fa7f10bSFabien Thomas.Pq Event B0H , Umask 02H
8631fa7f10bSFabien ThomasCounts number of offcore demand code read requests. Does not count L2
8641fa7f10bSFabien Thomasprefetch requests.
8651fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.DEMAND.RFO
8661fa7f10bSFabien Thomas.Pq Event B0H , Umask 04H
8671fa7f10bSFabien ThomasCounts number of offcore demand RFO requests. Does not count L2 prefetch
8681fa7f10bSFabien Thomasrequests.
8691fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.ANY.READ
8701fa7f10bSFabien Thomas.Pq Event B0H , Umask 08H
8711fa7f10bSFabien ThomasCounts number of offcore read requests. Includes L2 prefetch requests.
8721fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.ANY.RFO
8731fa7f10bSFabien Thomas.Pq Event 80H , Umask 10H
8741fa7f10bSFabien ThomasCounts number of offcore RFO requests. Includes L2 prefetch requests.
8751fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.L1D_WRITEBACK
8761fa7f10bSFabien Thomas.Pq Event B0H , Umask 40H
8771fa7f10bSFabien ThomasCounts number of L1D writebacks to the uncore.
8781fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS.ANY
8791fa7f10bSFabien Thomas.Pq Event B0H , Umask 80H
8801fa7f10bSFabien ThomasCounts all offcore requests.
8811fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT0
8821fa7f10bSFabien Thomas.Pq Event B1H , Umask 01H
8831fa7f10bSFabien ThomasCounts number of Uops executed that were issued on port 0. Port 0 handles
8841fa7f10bSFabien Thomasinteger arithmetic, SIMD and FP add Uops.
8851fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT1
8861fa7f10bSFabien Thomas.Pq Event B1H , Umask 02H
8871fa7f10bSFabien ThomasCounts number of Uops executed that were issued on port 1. Port 1 handles
8881fa7f10bSFabien Thomasinteger arithmetic, SIMD, integer shift, FP multiply and FP divide Uops.
8891fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT2_CORE
8901fa7f10bSFabien Thomas.Pq Event B1H , Umask 04H
8911fa7f10bSFabien ThomasCounts number of Uops executed that were issued on port 2. Port 2 handles
8921fa7f10bSFabien Thomasthe load Uops. This is a core count only and can not be collected per
8931fa7f10bSFabien Thomasthread.
8941fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT3_CORE
8951fa7f10bSFabien Thomas.Pq Event B1H , Umask 08H
8961fa7f10bSFabien ThomasCounts number of Uops executed that were issued on port 3. Port 3 handles
8971fa7f10bSFabien Thomasstore Uops. This is a core count only and can not be collected per thread.
8981fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT4_CORE
8991fa7f10bSFabien Thomas.Pq Event B1H , Umask 10H
9001fa7f10bSFabien ThomasCounts number of Uops executed that where issued on port 4. Port 4 handles
9011fa7f10bSFabien Thomasthe value to be stored for the store Uops issued on port 3. This is a core
9021fa7f10bSFabien Thomascount only and can not be collected per thread.
9031fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5
9041fa7f10bSFabien Thomas.Pq Event B1H , Umask 1FH
9051fa7f10bSFabien ThomasCounts number of cycles there are one or more uops being executed and were
9061fa7f10bSFabien Thomasissued on ports 0-4. This is a core count only and can not be collected per
9071fa7f10bSFabien Thomasthread.
9081fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT5
9091fa7f10bSFabien Thomas.Pq Event B1H , Umask 20H
9101fa7f10bSFabien ThomasCounts number of Uops executed that where issued on port 5.
9111fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES
9121fa7f10bSFabien Thomas.Pq Event B1H , Umask 3FH
9131fa7f10bSFabien ThomasCounts number of cycles there are one or more uops being executed on any
9141fa7f10bSFabien Thomasports. This is a core count only and can not be collected per thread.
9151fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT015
9161fa7f10bSFabien Thomas.Pq Event B1H , Umask 40H
9171fa7f10bSFabien ThomasCounts number of Uops executed that where issued on port 0, 1, or 5.
9181fa7f10bSFabien Thomasuse cmask=1, invert=1 to count stall cycles
9191fa7f10bSFabien Thomas.It Li UOPS_EXECUTED.PORT234
9201fa7f10bSFabien Thomas.Pq Event B1H , Umask 80H
9211fa7f10bSFabien ThomasCounts number of Uops executed that where issued on port 2, 3, or 4.
9221fa7f10bSFabien Thomas.It Li OFFCORE_REQUESTS_SQ_FULL
9231fa7f10bSFabien Thomas.Pq Event B2H , Umask 01H
9241fa7f10bSFabien ThomasCounts number of cycles the SQ is full to handle off-core requests.
9251fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA
9261fa7f10bSFabien Thomas.Pq Event B3H , Umask 01H
9271fa7f10bSFabien ThomasCounts weighted cycles of snoopq requests for data. Counter 0 only
9281fa7f10bSFabien ThomasUse cmask=1 to count cycles not empty.
9291fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE
9301fa7f10bSFabien Thomas.Pq Event B3H , Umask 02H
9311fa7f10bSFabien ThomasCounts weighted cycles of snoopq invalidate requests. Counter 0 only
9321fa7f10bSFabien ThomasUse cmask=1 to count cycles not empty.
9331fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE
9341fa7f10bSFabien Thomas.Pq Event B3H , Umask 04H
9351fa7f10bSFabien ThomasCounts weighted cycles of snoopq requests for code. Counter 0 only
9361fa7f10bSFabien ThomasUse cmask=1 to count cycles not empty.
9371fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS.CODE
9381fa7f10bSFabien Thomas.Pq Event B4H , Umask 01H
9391fa7f10bSFabien ThomasCounts the number of snoop code requests
9401fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS.DATA
9411fa7f10bSFabien Thomas.Pq Event B4H , Umask 02H
9421fa7f10bSFabien ThomasCounts the number of snoop data requests
9431fa7f10bSFabien Thomas.It Li SNOOPQ_REQUESTS.INVALIDATE
9441fa7f10bSFabien Thomas.Pq Event B4H , Umask 04H
9451fa7f10bSFabien ThomasCounts the number of snoop invalidate requests
9461fa7f10bSFabien Thomas.It Li OFF_CORE_RESPONSE_0
9471fa7f10bSFabien Thomas.Pq Event B7H , Umask 01H
9481fa7f10bSFabien Thomassee Section 30.6.1.3, Off-core Response Performance Monitoring in the
9491fa7f10bSFabien ThomasProcessor Core.
9501fa7f10bSFabien ThomasRequires programming MSR 01A6H
9511fa7f10bSFabien Thomas.It Li SNOOP_RESPONSE.HIT
9521fa7f10bSFabien Thomas.Pq Event B8H , Umask 01H
9531fa7f10bSFabien ThomasCounts HIT snoop response sent by this thread in response to a snoop
9541fa7f10bSFabien Thomasrequest.
9551fa7f10bSFabien Thomas.It Li SNOOP_RESPONSE.HITE
9561fa7f10bSFabien Thomas.Pq Event B8H , Umask 02H
9571fa7f10bSFabien ThomasCounts HIT E snoop response sent by this thread in response to a snoop
9581fa7f10bSFabien Thomasrequest.
9591fa7f10bSFabien Thomas.It Li SNOOP_RESPONSE.HITM
9601fa7f10bSFabien Thomas.Pq Event B8H , Umask 04H
9611fa7f10bSFabien ThomasCounts HIT M snoop response sent by this thread in response to a snoop
9621fa7f10bSFabien Thomasrequest.
9631fa7f10bSFabien Thomas.It Li OFF_CORE_RESPONSE_1
9641fa7f10bSFabien Thomas.Pq Event BBH , Umask 01H
9651fa7f10bSFabien Thomassee Section 30.6.1.3, Off-core Response Performance Monitoring in the
9661fa7f10bSFabien ThomasProcessor Core
9671fa7f10bSFabien ThomasUse MSR 01A7H
9681fa7f10bSFabien Thomas.It Li INST_RETIRED.ANY_P
9691fa7f10bSFabien Thomas.Pq Event C0H , Umask 01H
9701fa7f10bSFabien ThomasSee Table A-1
9711fa7f10bSFabien ThomasNotes: INST_RETIRED.ANY is counted by a designated fixed counter.
9721fa7f10bSFabien ThomasINST_RETIRED.ANY_P is counted by a programmable counter and is an
9731fa7f10bSFabien Thomasarchitectural performance event. Event is supported if CPUID.A.EBX[1] = 0.
9741fa7f10bSFabien ThomasCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not
9751fa7f10bSFabien Thomascount as retired instructions.
9761fa7f10bSFabien Thomas.It Li INST_RETIRED.X87
9771fa7f10bSFabien Thomas.Pq Event C0H , Umask 02H
978*c2025a76SJoel DahlCounts the number of floating point computational operations retired
9791fa7f10bSFabien Thomasfloating point computational operations executed by the assist handler and
9801fa7f10bSFabien Thomassub-operations of complex floating point instructions like transcendental
9811fa7f10bSFabien Thomasinstructions.
9821fa7f10bSFabien Thomas.It Li INST_RETIRED.MMX
9831fa7f10bSFabien Thomas.Pq Event C0H , Umask 04H
9841fa7f10bSFabien ThomasCounts the number of retired: MMX instructions.
9851fa7f10bSFabien Thomas.It Li UOPS_RETIRED.ANY
9861fa7f10bSFabien Thomas.Pq Event C2H , Umask 01H
9871fa7f10bSFabien ThomasCounts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
9881fa7f10bSFabien Thomasothers=1; maximum count of 8 per cycle). Most instructions are composed of
9891fa7f10bSFabien Thomasone or two micro-ops. Some instructions are decoded into longer sequences
9901fa7f10bSFabien Thomassuch as repeat instructions, floating point transcendental instructions, and
9911fa7f10bSFabien Thomasassists.
9921fa7f10bSFabien ThomasUse cmask=1 and invert to count active cycles or stalled cycles
9931fa7f10bSFabien Thomas.It Li UOPS_RETIRED.RETIRE_SLOTS
9941fa7f10bSFabien Thomas.Pq Event C2H , Umask 02H
9951fa7f10bSFabien ThomasCounts the number of retirement slots used each cycle
9961fa7f10bSFabien Thomas.It Li UOPS_RETIRED.MACRO_FUSED
9971fa7f10bSFabien Thomas.Pq Event C2H , Umask 04H
9981fa7f10bSFabien ThomasCounts number of macro-fused uops retired.
9991fa7f10bSFabien Thomas.It Li MACHINE_CLEARS.CYCLES
10001fa7f10bSFabien Thomas.Pq Event C3H , Umask 01H
10011fa7f10bSFabien ThomasCounts the cycles machine clear is asserted.
10021fa7f10bSFabien Thomas.It Li MACHINE_CLEARS.MEM_ORDER
10031fa7f10bSFabien Thomas.Pq Event C3H , Umask 02H
10041fa7f10bSFabien ThomasCounts the number of machine clears due to memory order conflicts.
10051fa7f10bSFabien Thomas.It Li MACHINE_CLEARS.SMC
10061fa7f10bSFabien Thomas.Pq Event C3H , Umask 04H
10071fa7f10bSFabien ThomasCounts the number of times that a program writes to a code section.
10081fa7f10bSFabien ThomasSelf-modifying code causes a sever penalty in all Intel 64 and IA-32
10091fa7f10bSFabien Thomasprocessors. The modified cache line is written back to the L2 and L3caches.
10101fa7f10bSFabien Thomas.It Li BR_INST_RETIRED.ALL_BRANCHES
10111fa7f10bSFabien Thomas.Pq Event C4H , Umask 00H
10121fa7f10bSFabien ThomasSee Table A-1
10131fa7f10bSFabien Thomas.It Li BR_INST_RETIRED.CONDITIONAL
10141fa7f10bSFabien Thomas.Pq Event C4H , Umask 01H
10151fa7f10bSFabien ThomasCounts the number of conditional branch instructions retired.
10161fa7f10bSFabien Thomas.It Li BR_INST_RETIRED.NEAR_CALL
10171fa7f10bSFabien Thomas.Pq Event C4H , Umask 02H
10181fa7f10bSFabien ThomasCounts the number of direct & indirect near unconditional calls retired
10191fa7f10bSFabien Thomas.It Li BR_INST_RETIRED.ALL_BRANCHES
10201fa7f10bSFabien Thomas.Pq Event C4H , Umask 04H
10211fa7f10bSFabien ThomasCounts the number of branch instructions retired
10221fa7f10bSFabien Thomas.It Li BR_MISP_RETIRED.ALL_BRANCHES
10231fa7f10bSFabien Thomas.Pq Event C5H , Umask 00H
10241fa7f10bSFabien ThomasSee Table A-1
10251fa7f10bSFabien Thomas.It Li BR_MISP_RETIRED.CONDITIONAL
10261fa7f10bSFabien Thomas.Pq Event C5H , Umask 01H
10271fa7f10bSFabien ThomasCounts mispredicted conditional retired calls.
10281fa7f10bSFabien Thomas.It Li BR_MISP_RETIRED.NEAR_CALL
10291fa7f10bSFabien Thomas.Pq Event C5H , Umask 02H
10301fa7f10bSFabien ThomasCounts mispredicted direct & indirect near unconditional retired calls.
10311fa7f10bSFabien Thomas.It Li BR_MISP_RETIRED.ALL_BRANCHES
10321fa7f10bSFabien Thomas.Pq Event C5H , Umask 04H
10331fa7f10bSFabien ThomasCounts all mispredicted retired calls.
10341fa7f10bSFabien Thomas.It Li SSEX_UOPS_RETIRED.PACKED_SINGLE
10351fa7f10bSFabien Thomas.Pq Event C7H , Umask 01H
10361fa7f10bSFabien ThomasCounts SIMD packed single-precision floating point Uops retired.
10371fa7f10bSFabien Thomas.It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE
10381fa7f10bSFabien Thomas.Pq Event C7H , Umask 02H
10391fa7f10bSFabien ThomasCounts SIMD calar single-precision floating point Uops retired.
10401fa7f10bSFabien Thomas.It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE
10411fa7f10bSFabien Thomas.Pq Event C7H , Umask 04H
10421fa7f10bSFabien ThomasCounts SIMD packed double- precision floating point Uops retired.
10431fa7f10bSFabien Thomas.It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE
10441fa7f10bSFabien Thomas.Pq Event C7H , Umask 08H
10451fa7f10bSFabien ThomasCounts SIMD scalar double-precision floating point Uops retired.
10461fa7f10bSFabien Thomas.It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER
10471fa7f10bSFabien Thomas.Pq Event C7H , Umask 10H
10481fa7f10bSFabien ThomasCounts 128-bit SIMD vector integer Uops retired.
10491fa7f10bSFabien Thomas.It Li ITLB_MISS_RETIRED
10501fa7f10bSFabien Thomas.Pq Event C8H , Umask 20H
10511fa7f10bSFabien ThomasCounts the number of retired instructions that missed the ITLB when the
10521fa7f10bSFabien Thomasinstruction was fetched.
10531fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.L1D_HIT
10541fa7f10bSFabien Thomas.Pq Event CBH , Umask 01H
10551fa7f10bSFabien ThomasCounts number of retired loads that hit the L1 data cache.
10561fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.L2_HIT
10571fa7f10bSFabien Thomas.Pq Event CBH , Umask 02H
10581fa7f10bSFabien ThomasCounts number of retired loads that hit the L2 data cache.
10591fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT
10601fa7f10bSFabien Thomas.Pq Event CBH , Umask 04H
10611fa7f10bSFabien ThomasCounts number of retired loads that hit their own, unshared lines in the L3
10621fa7f10bSFabien Thomascache.
10631fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM
10641fa7f10bSFabien Thomas.Pq Event CBH , Umask 08H
10651fa7f10bSFabien ThomasCounts number of retired loads that hit in a sibling core's L2 (on die
10661fa7f10bSFabien Thomascore). Since the L3 is inclusive of all cores on the package, this is an L3
10671fa7f10bSFabien Thomashit. This counts both clean or modified hits.
10681fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.L3_MISS
10691fa7f10bSFabien Thomas.Pq Event CBH , Umask 10H
10701fa7f10bSFabien ThomasCounts number of retired loads that miss the L3 cache. The load was
10711fa7f10bSFabien Thomassatisfied by a remote socket, local memory or an IOH.
10721fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.HIT_LFB
10731fa7f10bSFabien Thomas.Pq Event CBH , Umask 40H
10741fa7f10bSFabien ThomasCounts number of retired loads that miss the L1D and the address is located
10751fa7f10bSFabien Thomasin an allocated line fill buffer and will soon be committed to cache. This
10761fa7f10bSFabien Thomasis counting secondary L1D misses.
10771fa7f10bSFabien Thomas.It Li MEM_LOAD_RETIRED.DTLB_MISS
10781fa7f10bSFabien Thomas.Pq Event CBH , Umask 80H
10791fa7f10bSFabien ThomasCounts the number of retired loads that missed the DTLB. The DTLB miss is
10801fa7f10bSFabien Thomasnot counted if the load operation causes a fault. This event counts loads
10811fa7f10bSFabien Thomasfrom cacheable memory only. The event does not count loads by software
10821fa7f10bSFabien Thomasprefetches. Counts both primary and secondary misses to the TLB.
10831fa7f10bSFabien Thomas.It Li FP_MMX_TRANS.TO_FP
10841fa7f10bSFabien Thomas.Pq Event CCH , Umask 01H
10851fa7f10bSFabien ThomasCounts the first floating-point instruction following any MMX instruction.
10861fa7f10bSFabien ThomasYou can use this event to estimate the penalties for the transitions between
10871fa7f10bSFabien Thomasfloating-point and MMX technology states.
10881fa7f10bSFabien Thomas.It Li FP_MMX_TRANS.TO_MMX
10891fa7f10bSFabien Thomas.Pq Event CCH , Umask 02H
10901fa7f10bSFabien ThomasCounts the first MMX instruction following a floating-point instruction. You
10911fa7f10bSFabien Thomascan use this event to estimate the penalties for the transitions between
10921fa7f10bSFabien Thomasfloating-point and MMX technology states.
10931fa7f10bSFabien Thomas.It Li FP_MMX_TRANS.ANY
10941fa7f10bSFabien Thomas.Pq Event CCH , Umask 03H
10951fa7f10bSFabien ThomasCounts all transitions from floating point to MMX instructions and from MMX
10961fa7f10bSFabien Thomasinstructions to floating point instructions. You can use this event to
10971fa7f10bSFabien Thomasestimate the penalties for the transitions between floating-point and MMX
10981fa7f10bSFabien Thomastechnology states.
10991fa7f10bSFabien Thomas.It Li MACRO_INSTS.DECODED
11001fa7f10bSFabien Thomas.Pq Event D0H , Umask 01H
11011fa7f10bSFabien ThomasCounts the number of instructions decoded, (but not necessarily executed or
11021fa7f10bSFabien Thomasretired).
11031fa7f10bSFabien Thomas.It Li UOPS_DECODED.STALL_CYCLES
11041fa7f10bSFabien Thomas.Pq Event D1H , Umask 01H
11051fa7f10bSFabien ThomasCounts the cycles of decoder stalls.
11061fa7f10bSFabien Thomas.It Li UOPS_DECODED.MS
11071fa7f10bSFabien Thomas.Pq Event D1H , Umask 02H
11081fa7f10bSFabien ThomasCounts the number of Uops decoded by the Microcode Sequencer, MS. The MS
11091fa7f10bSFabien Thomasdelivers uops when the instruction is more than 4 uops long or a microcode
11101fa7f10bSFabien Thomasassist is occurring.
11111fa7f10bSFabien Thomas.It Li UOPS_DECODED.ESP_FOLDING
11121fa7f10bSFabien Thomas.Pq Event D1H , Umask 04H
11131fa7f10bSFabien ThomasCounts number of stack pointer (ESP) instructions decoded: push , pop , call
11141fa7f10bSFabien Thomas, ret, etc. ESP instructions do not generate a Uop to increment or decrement
11151fa7f10bSFabien ThomasESP. Instead, they update an ESP_Offset register that keeps track of the
11161fa7f10bSFabien Thomasdelta to the current value of the ESP register.
11171fa7f10bSFabien Thomas.It Li UOPS_DECODED.ESP_SYNC
11181fa7f10bSFabien Thomas.Pq Event D1H , Umask 08H
11191fa7f10bSFabien ThomasCounts number of stack pointer (ESP) sync operations where an ESP
11201fa7f10bSFabien Thomasinstruction is corrected by adding the ESP offset register to the current
11211fa7f10bSFabien Thomasvalue of the ESP register.
11221fa7f10bSFabien Thomas.It Li RAT_STALLS.FLAGS
11231fa7f10bSFabien Thomas.Pq Event D2H , Umask 01H
11241fa7f10bSFabien ThomasCounts the number of cycles during which execution stalled due to several
11251fa7f10bSFabien Thomasreasons, one of which is a partial flag register stall. A partial register
11261fa7f10bSFabien Thomasstall may occur when two conditions are met: 1) an instruction modifies
11271fa7f10bSFabien Thomassome, but not all, of the flags in the flag register and 2) the next
11281fa7f10bSFabien Thomasinstruction, which depends on flags, depends on flags that were not modified
11291fa7f10bSFabien Thomasby this instruction.
11301fa7f10bSFabien Thomas.It Li RAT_STALLS.REGISTERS
11311fa7f10bSFabien Thomas.Pq Event D2H , Umask 02H
11321fa7f10bSFabien ThomasThis event counts the number of cycles instruction execution latency became
11331fa7f10bSFabien Thomaslonger than the defined latency because the instruction used a register that
11341fa7f10bSFabien Thomaswas partially written by previous instruction.
11351fa7f10bSFabien Thomas.It Li RAT_STALLS.ROB_READ_PORT
11361fa7f10bSFabien Thomas.Pq Event D2H , Umask 04H
11371fa7f10bSFabien ThomasCounts the number of cycles when ROB read port stalls occurred, which did
11381fa7f10bSFabien Thomasnot allow new micro-ops to enter the out-of-order pipeline. Note that, at
11391fa7f10bSFabien Thomasthis stage in the pipeline, additional stalls may occur at the same cycle
11401fa7f10bSFabien Thomasand prevent the stalled micro-ops from entering the pipe. In such a case,
11411fa7f10bSFabien Thomasmicro-ops retry entering the execution pipe in the next cycle and the
11421fa7f10bSFabien ThomasROB-read port stall is counted again.
11431fa7f10bSFabien Thomas.It Li RAT_STALLS.SCOREBOARD
11441fa7f10bSFabien Thomas.Pq Event D2H , Umask 08H
11451fa7f10bSFabien ThomasCounts the cycles where we stall due to microarchitecturally required
11461fa7f10bSFabien Thomasserialization. Microcode scoreboarding stalls.
11471fa7f10bSFabien Thomas.It Li RAT_STALLS.ANY
11481fa7f10bSFabien Thomas.Pq Event D2H , Umask 0FH
11491fa7f10bSFabien ThomasCounts all Register Allocation Table stall cycles due to: Cycles when ROB
11501fa7f10bSFabien Thomasread port stalls occurred, which did not allow new micro-ops to enter the
11511fa7f10bSFabien Thomasexecution pipe. Cycles when partial register stalls occurred Cycles when
11521fa7f10bSFabien Thomasflag stalls occurred Cycles floating-point unit (FPU) status word stalls
11531fa7f10bSFabien Thomasoccurred. To count each of these conditions separately use the events:
11541fa7f10bSFabien ThomasRAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and
11551fa7f10bSFabien ThomasRAT_STALLS.FPSW.
11561fa7f10bSFabien Thomas.It Li SEG_RENAME_STALLS
11571fa7f10bSFabien Thomas.Pq Event D4H , Umask 01H
11581fa7f10bSFabien ThomasCounts the number of stall cycles due to the lack of renaming resources for
11591fa7f10bSFabien Thomasthe ES, DS, FS, and GS segment registers. If a segment is renamed but not
11601fa7f10bSFabien Thomasretired and a second update to the same segment occurs, a stall occurs in
11611fa7f10bSFabien Thomasthe front- end of the pipeline until the renamed segment retires.
11621fa7f10bSFabien Thomas.It Li ES_REG_RENAMES
11631fa7f10bSFabien Thomas.Pq Event D5H , Umask 01H
11641fa7f10bSFabien ThomasCounts the number of times the ES segment register is renamed.
11651fa7f10bSFabien Thomas.It Li UOP_UNFUSION
11661fa7f10bSFabien Thomas.Pq Event DBH , Umask 01H
11671fa7f10bSFabien ThomasCounts unfusion events due to floating point exception to a fused uop.
11681fa7f10bSFabien Thomas.It Li BR_INST_DECODED
11691fa7f10bSFabien Thomas.Pq Event E0H , Umask 01H
11701fa7f10bSFabien ThomasCounts the number of branch instructions decoded.
11711fa7f10bSFabien Thomas.It Li BPU_MISSED_CALL_RET
11721fa7f10bSFabien Thomas.Pq Event E5H , Umask 01H
1173799162a6SJoel DahlCounts number of times the Branch Prediction Unit missed predicting a call
11741fa7f10bSFabien Thomasor return branch.
11751fa7f10bSFabien Thomas.It Li BACLEAR.CLEAR
11761fa7f10bSFabien Thomas.Pq Event E6H , Umask 01H
11771fa7f10bSFabien ThomasCounts the number of times the front end is resteered, mainly when the
11781fa7f10bSFabien ThomasBranch Prediction Unit cannot provide a correct prediction and this is
11791fa7f10bSFabien Thomascorrected by the Branch Address Calculator at the front end. This can occur
11801fa7f10bSFabien Thomasif the code has many branches such that they cannot be consumed by the BPU.
11811fa7f10bSFabien ThomasEach BACLEAR asserted by the BAC generates approximately an 8 cycle bubble
11821fa7f10bSFabien Thomasin the instruction fetch pipeline. The effect on total execution time
11831fa7f10bSFabien Thomasdepends on the surrounding code.
11841fa7f10bSFabien Thomas.It Li BACLEAR.BAD_TARGET
11851fa7f10bSFabien Thomas.Pq Event E6H , Umask 02H
11861fa7f10bSFabien ThomasCounts number of Branch Address Calculator clears (BACLEAR) asserted due to
11871fa7f10bSFabien Thomasconditional branch instructions in which there was a target hit but the
11881fa7f10bSFabien Thomasdirection was wrong. Each BACLEAR asserted by the BAC generates
11891fa7f10bSFabien Thomasapproximately an 8 cycle bubble in the instruction fetch pipeline.
11901fa7f10bSFabien Thomas.It Li BPU_CLEARS.EARLY
11911fa7f10bSFabien Thomas.Pq Event E8H , Umask 01H
11921fa7f10bSFabien ThomasCounts early (normal) Branch Prediction Unit clears: BPU predicted a taken
11931fa7f10bSFabien Thomasbranch after incorrectly assuming that it was not taken.
11941fa7f10bSFabien ThomasThe BPU clear leads to 2 cycle bubble in the Front End.
11951fa7f10bSFabien Thomas.It Li BPU_CLEARS.LATE
11961fa7f10bSFabien Thomas.Pq Event E8H , Umask 02H
11971fa7f10bSFabien ThomasCounts late Branch Prediction Unit clears due to Most Recently Used
11981fa7f10bSFabien Thomasconflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
11991fa7f10bSFabien Thomas.It Li THREAD_ACTIVE
12001fa7f10bSFabien Thomas.Pq Event ECH , Umask 01H
12011fa7f10bSFabien ThomasCounts cycles threads are active.
12021fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.LOAD
12031fa7f10bSFabien Thomas.Pq Event F0H , Umask 01H
12041fa7f10bSFabien ThomasCounts L2 load operations due to HW prefetch or demand loads.
12051fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.RFO
12061fa7f10bSFabien Thomas.Pq Event F0H , Umask 02H
12071fa7f10bSFabien ThomasCounts L2 RFO operations due to HW prefetch or demand RFOs.
12081fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.IFETCH
12091fa7f10bSFabien Thomas.Pq Event F0H , Umask 04H
12101fa7f10bSFabien ThomasCounts L2 instruction fetch operations due to HW prefetch or demand ifetch.
12111fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.PREFETCH
12121fa7f10bSFabien Thomas.Pq Event F0H , Umask 08H
12131fa7f10bSFabien ThomasCounts L2 prefetch operations.
12141fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.L1D_WB
12151fa7f10bSFabien Thomas.Pq Event F0H , Umask 10H
12161fa7f10bSFabien ThomasCounts L1D writeback operations to the L2.
12171fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.FILL
12181fa7f10bSFabien Thomas.Pq Event F0H , Umask 20H
12191fa7f10bSFabien ThomasCounts L2 cache line fill operations due to load, RFO, L1D writeback or
12201fa7f10bSFabien Thomasprefetch.
12211fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.WB
12221fa7f10bSFabien Thomas.Pq Event F0H , Umask 40H
12231fa7f10bSFabien ThomasCounts L2 writeback operations to the L3.
12241fa7f10bSFabien Thomas.It Li L2_TRANSACTIONS.ANY
12251fa7f10bSFabien Thomas.Pq Event F0H , Umask 80H
12261fa7f10bSFabien ThomasCounts all L2 cache operations.
12271fa7f10bSFabien Thomas.It Li L2_LINES_IN.S_STATE
12281fa7f10bSFabien Thomas.Pq Event F1H , Umask 02H
12291fa7f10bSFabien ThomasCounts the number of cache lines allocated in the L2 cache in the S (shared)
12301fa7f10bSFabien Thomasstate.
12311fa7f10bSFabien Thomas.It Li L2_LINES_IN.E_STATE
12321fa7f10bSFabien Thomas.Pq Event F1H , Umask 04H
12331fa7f10bSFabien ThomasCounts the number of cache lines allocated in the L2 cache in the E
12341fa7f10bSFabien Thomas(exclusive) state.
12351fa7f10bSFabien Thomas.It Li L2_LINES_IN.ANY
12361fa7f10bSFabien Thomas.Pq Event F1H , Umask 07H
12371fa7f10bSFabien ThomasCounts the number of cache lines allocated in the L2 cache.
12381fa7f10bSFabien Thomas.It Li L2_LINES_OUT.DEMAND_CLEAN
12391fa7f10bSFabien Thomas.Pq Event F2H , Umask 01H
12401fa7f10bSFabien ThomasCounts L2 clean cache lines evicted by a demand request.
12411fa7f10bSFabien Thomas.It Li L2_LINES_OUT.DEMAND_DIRTY
12421fa7f10bSFabien Thomas.Pq Event F2H , Umask 02H
12431fa7f10bSFabien ThomasCounts L2 dirty (modified) cache lines evicted by a demand request.
12441fa7f10bSFabien Thomas.It Li L2_LINES_OUT.PREFETCH_CLEAN
12451fa7f10bSFabien Thomas.Pq Event F2H , Umask 04H
12461fa7f10bSFabien ThomasCounts L2 clean cache line evicted by a prefetch request.
12471fa7f10bSFabien Thomas.It Li L2_LINES_OUT.PREFETCH_DIRTY
12481fa7f10bSFabien Thomas.Pq Event F2H , Umask 08H
12491fa7f10bSFabien ThomasCounts L2 modified cache line evicted by a prefetch request.
12501fa7f10bSFabien Thomas.It Li L2_LINES_OUT.ANY
12511fa7f10bSFabien Thomas.Pq Event F2H , Umask 0FH
12521fa7f10bSFabien ThomasCounts all L2 cache lines evicted for any reason.
12531fa7f10bSFabien Thomas.It Li SQ_MISC.LRU_HINTS
12541fa7f10bSFabien Thomas.Pq Event F4H , Umask 04H
12551fa7f10bSFabien ThomasCounts number of Super Queue LRU hints sent to L3.
12561fa7f10bSFabien Thomas.It Li SQ_MISC.SPLIT_LOCK
12571fa7f10bSFabien Thomas.Pq Event F4H , Umask 10H
12581fa7f10bSFabien ThomasCounts the number of SQ lock splits across a cache line.
12591fa7f10bSFabien Thomas.It Li SQ_FULL_STALL_CYCLES
12601fa7f10bSFabien Thomas.Pq Event F6H , Umask 01H
12611fa7f10bSFabien ThomasCounts cycles the Super Queue is full. Neither of the threads on this core
12621fa7f10bSFabien Thomaswill be able to access the uncore.
12631fa7f10bSFabien Thomas.It Li FP_ASSIST.ALL
12641fa7f10bSFabien Thomas.Pq Event F7H , Umask 01H
12651fa7f10bSFabien ThomasCounts the number of floating point operations executed that required
12661fa7f10bSFabien Thomasmicro-code assist intervention. Assists are required in the following cases:
12671fa7f10bSFabien ThomasSSE instructions, (Denormal input when the DAZ flag is off or Underflow
12681fa7f10bSFabien Thomasresult when the FTZ flag is off): x87 instructions, (NaN or denormal are
12691fa7f10bSFabien Thomasloaded to a register or used as input from memory, Division by 0 or
12701fa7f10bSFabien ThomasUnderflow output).
12711fa7f10bSFabien Thomas.It Li FP_ASSIST.OUTPUT
12721fa7f10bSFabien Thomas.Pq Event F7H , Umask 02H
12731fa7f10bSFabien ThomasCounts number of floating point micro-code assist when the output value
12741fa7f10bSFabien Thomas(destination register) is invalid.
12751fa7f10bSFabien Thomas.It Li FP_ASSIST.INPUT
12761fa7f10bSFabien Thomas.Pq Event F7H , Umask 04H
12771fa7f10bSFabien ThomasCounts number of floating point micro-code assist when the input value (one
12781fa7f10bSFabien Thomasof the source operands to an FP instruction) is invalid.
12791fa7f10bSFabien Thomas.It Li SIMD_INT_64.PACKED_MPY
12801fa7f10bSFabien Thomas.Pq Event FDH , Umask 01H
12811fa7f10bSFabien ThomasCounts number of SID integer 64 bit packed multiply operations.
12821fa7f10bSFabien Thomas.It Li SIMD_INT_64.PACKED_SHIFT
12831fa7f10bSFabien Thomas.Pq Event FDH , Umask 02H
12841fa7f10bSFabien ThomasCounts number of SID integer 64 bit packed shift operations.
12851fa7f10bSFabien Thomas.It Li SIMD_INT_64.PACK
12861fa7f10bSFabien Thomas.Pq Event FDH , Umask 04H
12871fa7f10bSFabien ThomasCounts number of SID integer 64 bit pack operations.
12881fa7f10bSFabien Thomas.It Li SIMD_INT_64.UNPACK
12891fa7f10bSFabien Thomas.Pq Event FDH , Umask 08H
12901fa7f10bSFabien ThomasCounts number of SID integer 64 bit unpack operations.
12911fa7f10bSFabien Thomas.It Li SIMD_INT_64.PACKED_LOGICAL
12921fa7f10bSFabien Thomas.Pq Event FDH , Umask 10H
12931fa7f10bSFabien ThomasCounts number of SID integer 64 bit logical operations.
12941fa7f10bSFabien Thomas.It Li SIMD_INT_64.PACKED_ARITH
12951fa7f10bSFabien Thomas.Pq Event FDH , Umask 20H
12961fa7f10bSFabien ThomasCounts number of SID integer 64 bit arithmetic operations.
12971fa7f10bSFabien Thomas.It Li SIMD_INT_64.SHUFFLE_MOVE
12981fa7f10bSFabien Thomas.Pq Event FDH , Umask 40H
12991fa7f10bSFabien ThomasCounts number of SID integer 64 bit shift or move operations.
13001fa7f10bSFabien Thomas.El
13011fa7f10bSFabien Thomas.Sh SEE ALSO
13021fa7f10bSFabien Thomas.Xr pmc 3 ,
13031fa7f10bSFabien Thomas.Xr pmc.atom 3 ,
13041fa7f10bSFabien Thomas.Xr pmc.core 3 ,
13051fa7f10bSFabien Thomas.Xr pmc.iaf 3 ,
13061fa7f10bSFabien Thomas.Xr pmc.ucf 3 ,
13071fa7f10bSFabien Thomas.Xr pmc.k7 3 ,
13081fa7f10bSFabien Thomas.Xr pmc.k8 3 ,
13091fa7f10bSFabien Thomas.Xr pmc.p4 3 ,
13101fa7f10bSFabien Thomas.Xr pmc.p5 3 ,
13111fa7f10bSFabien Thomas.Xr pmc.p6 3 ,
13121fa7f10bSFabien Thomas.Xr pmc.corei7 3 ,
13131fa7f10bSFabien Thomas.Xr pmc.corei7uc 3 ,
13141fa7f10bSFabien Thomas.Xr pmc.westmereuc 3 ,
13151fa7f10bSFabien Thomas.Xr pmc.tsc 3 ,
13161fa7f10bSFabien Thomas.Xr pmc_cpuinfo 3 ,
13171fa7f10bSFabien Thomas.Xr pmclog 3 ,
13181fa7f10bSFabien Thomas.Xr hwpmc 4
13191fa7f10bSFabien Thomas.Sh HISTORY
13201fa7f10bSFabien ThomasThe
13211fa7f10bSFabien Thomas.Nm pmc
13221fa7f10bSFabien Thomaslibrary first appeared in
13231fa7f10bSFabien Thomas.Fx 6.0 .
13241fa7f10bSFabien Thomas.Sh AUTHORS
13251fa7f10bSFabien ThomasThe
13261fa7f10bSFabien Thomas.Lb libpmc
13271fa7f10bSFabien Thomaslibrary was written by
13281fa7f10bSFabien Thomas.An "Joseph Koshy"
13291fa7f10bSFabien Thomas.Aq jkoshy@FreeBSD.org .
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